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SRTSC A LabVIEW based Test and Hardware Configuration System for SRS Volkan Gezer Eskisehir Osmangazi University & CERN

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SRTSC. A LabVIEW based Test and Hardware Configuration System f or SRS. Volkan Gezer Eskisehir Osmangazi University & CERN. Aim of SRT CS. Test of SRS electronics cards for production conformance Configuration or Reconfiguration of parameters - PowerPoint PPT Presentation

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Page 1: SRTSC

SRTSC

A LabVIEW based Test and Hardware Configuration System

for SRS

Volkan GezerEskisehir Osmangazi University

& CERN

Page 2: SRTSC

Volkan Gezer - [email protected] 2

Aim of SRTCS

• Test of SRS electronics cards for production conformance

• Configuration or Reconfiguration of parameters

• To be used both for production (PRISMA) and end-users

• Scope: FEC card, ADC card, (Hybrid)• More SRS cards to be added

SRTCS

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Volkan Gezer - [email protected] 3SRTCS

SRS test infrastructure• Laptop / PC with LabVIEW 2010 and ethernet cable• SRS Crate-HP or desktop ATX –SRS power• 1 FEC Reference card with 1000BASE-T SFP-ethernet plugin• 1 SRS ADC Reference card• 1 SRS CTF Reference card• 1 HDMI cable A-D*• 2 APV hybrids V4 (Master & Slave) + SAMTEC flat cable• 1 DTC link cable (special)• 1 Ethernet Cross cable• 1 Coaxial cable 50 OHM • 1 LVDS – RJ45 cable (special)• 1 Digital Voltmeter• 1 Xilinx USB programmer head • Xilinx iMPACT programming tool (free WEB version)• SRS FEC Firmware (latest version)

* Older versions of hybrids need special HDMI cable

Page 4: SRTSC

Volkan Gezer - [email protected] 4SRTCS

Test setup overview

FEC ADC

chip

chip

CTF

Ethernet

SRTCS

ATX power

SRS crate

HDMI cable

Clock and trigger generation

FPGA

Loop cable

diff LVDS cable

Operator

dtc cable

Page 5: SRTSC

Volkan Gezer - [email protected] 5SRTCS

Jumpers and Microswitches

Jumper positions Microswitches on ADC

Don’t start tests before verification of these

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Volkan Gezer - [email protected] 6SRTCS

Firmware Programming

lamp must be green!

Xilinx iMPACT Program

Page 7: SRTSC

Volkan Gezer - [email protected] 7

Test overview*

1. Basic tests:– Voltages are good– FPGA works– Connectors work (soldered etc…)

2. Functionality tests– SRTCS and Firmware

SRTCS

* Tests may not cover 100% functionality in first version

Page 8: SRTSC

Volkan Gezer - [email protected] 8

SRTCS features*

• Full range of conformance tests• User-friendly error reporting• Auto-increment serial number• Auto MAC address generation and programming• Fully documented buttons with context help • Save as HTML and/or Print Reports with success or

fail messages• Expert mode, enabling manual commands and

error decoding.

SRTCS

* beta version 1.0a

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Volkan Gezer - [email protected] 9

SRTCS User InterfaceRun button on toolbar

SRTCS

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Volkan Gezer - [email protected] 10SRTCS

FEC Configuration

Password protected increment

Page 11: SRTSC

Volkan Gezer - [email protected] 11

FEC: MAC address allocation

• Auto-generation based on serial number• Two types of allocation:– 1k CERN Range: SRS-MAC = 08-00-30-F2-00-00 … 08-00-30-F2-FF-FF– External User: Xilinx MAC range (to be discussed),

starting with 00-0A-35

SRTCS

Page 12: SRTSC

Volkan Gezer - [email protected] 12

Done

SRTCS

Finalize Configuration button

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Volkan Gezer - [email protected] 13

FEC Configuration Report

SRTCS

Should be printed after each successful test and configuration

Page 14: SRTSC

Volkan Gezer - [email protected] 14SRTCS

A. FEC Card Test

Dialog appears for each test button

Page 15: SRTSC

Volkan Gezer - [email protected] 15

A.1. Setup of FEC Front Panel Tests (with Reference CTF)

CTF Switch in Internal Clock and Trigger Mode

SRTCS

Page 16: SRTSC

Volkan Gezer - [email protected] 16

A.2. DTC Link Cross Cable Between J1 and J2

1 (orange white) 4

2 (orange) 5

3 (green white) 7

4 (blue) 1

5 (blue white) 2

6 (green) 8

7 (brown white) 3

8 (brown) 6

J1

J2

Cross cable pinout*

SRTCS

*standard ethernet cross cable

needed for test button “check J1-J2“

Page 17: SRTSC

Volkan Gezer - [email protected] 17

A.3. CTF link cable between CTF OUT and J2 on FEC card& LVDS Clock Cable

8 White-orange 7

7 Orange 8

6 White-green 2 (CLK-)

5 Blue 4

4 White-blue 5

3 Green 1 (Clk+)

2 White-brown 6 (Trg-)

1 Brown 3 (Trg+)

J2

CTF OUT CTF –J2 special cable pinout

SRTCS

needed for CTF clock test button

LVDS In

Page 18: SRTSC

Volkan Gezer - [email protected] 18SRTCS

B. ADC Card Test

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Volkan Gezer - [email protected] 19

B.1. Setup of ADC Card Test requires reference CTF, FEC, and 2 Hybrids

SRTCS

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Volkan Gezer - [email protected] 20SRTCS

C. Hybrid Test (planned test screen)

•JTAG link to Hybrids OK•All channels work•Chip Works•Pedestal Values are OK•Register configuration OK•Incoming chip data OK

Page 21: SRTSC

Volkan Gezer - [email protected] 21

SRTCS Error reporting

SRTCS

Error 1 occurred at srtcs.vi

Possible reason(s):

LabVIEW: An input parameter is invalid. For example if the input is a path, the path might contain a character not allowed by the OS such as ? or @.=========================NI-488: Command requires GPIB Controller to be Controller-In-Charge.

Page 22: SRTSC

Volkan Gezer - [email protected] 22

D. Expert -> Expert Tab

SRTCS

Page 23: SRTSC

Volkan Gezer - [email protected] 23

Thank you for listening.

Your suggestions are welcome

Volkan [email protected]

[email protected]

SRTCS

Page 24: SRTSC

Volkan Gezer - [email protected] 24

Backup

SRTCS

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Volkan Gezer - [email protected] 25

D. Expert -> UDP Flow Tab

6006

6519:

FFFFFFFFAAAAFFFF00000000000000000000000000000001000000000002000000000000000300000000000000040000 0000000050000000000000006000000FF00000000000000FF

6263:

FFFFFFFFAAAAFFFF000000000000001000000064000000110000003C0000001200000022000000130000002200000014000000220000001500000037000000160000000A00000017000000000001800000064000000190000001E0000001A0000003C0000001B000000280000001C000000EF0000001D000000FE0000 00010000001900000002000000840000000300000004

6039:

FFFFFFFFAAAAFFFF0000000000000000000000030000000100000005000000080000FFFF0000000F00000001

SRTCS

Page 26: SRTSC

Volkan Gezer - [email protected] 26

ISE iMPACT and Programming

SRTCS

http://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.htm

Free version available:

You need to turn FEC on for status led of the programmer go green

Page 27: SRTSC

Volkan Gezer - [email protected] 27

FEC Voltage test points

SRTCS

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Volkan Gezer - [email protected] 28

FEC backside test points

SRTCS

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Volkan Gezer - [email protected] 29

ADC Voltage test points

SRTCS

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Volkan Gezer - [email protected] 30

SRTCS Block Diagram

SRTCS

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Volkan Gezer - [email protected] 31SRTCS

SRTCS: To do