spin-transfer torque ram technology: review and prospect

Microelectronics Reliability 52 (2012) 613–627

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Microelectronics Reliability

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Review

Spin-transfer torque RAM technology: Review and prospect

T. Kawahara a,⇑, K. Ito a, R. Takemura a, H. Ohno b,c

a Central Research Laboratory, Hitachi Ltd., Kokubunji, Tokyo 185-8601, Japanb Center for Spintronics Integrated Systems, Tohoku University, Aoba-ku, Sendai 980-8577, Japanc Laboratory for Nanoelectronics and Spintronics, Research Institute of Electrical Communication, Tohoku University, Japan

a r t i c l e i n f o a b s t r a c t

Article history:Received 28 August 2011Accepted 30 September 2011Available online 1 November 2011

0026-2714/$ - see front matter � 2011 Elsevier Ltd. Adoi:10.1016/j.microrel.2011.09.028

⇑ Corresponding author.E-mail address: [email protected]

Non-volatile RAM (NV-RAM) enables instant-on/off computing, which drastically reduces power con-sumption. One of the most promising candidates for NV-RAM technology is the spin-transfer torqueRAM (SPRAM) based on magnetic tunnel junction (MTJ) device technology. This paper reviews the devel-opment of MTJ device technology and formulates considerations regarding its memory application,including SPRAM memory cell structure and operation, write voltage limitation, and thermal stability.At the circuit level, a disruptive read operation for future large integration scale is described. A 4F2 mem-ory cell and a multi-bit cell approach are also presented. Finally, the potential value of instant-on/offcomputing through NV-RAM and its impact are explored.

� 2011 Elsevier Ltd. All rights reserved.

Contents

1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6132. Magnetic tunnel junction (MTJ) device technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614

2.1. Development of MTJs with high tunnel magneto-resistance (TMR) ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6142.2. Spin transfer toque magnetization switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615

3. Memory cell scalability and reliability with MTJs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
3.1. Memory cell scalability in terms of write current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6173.2. Reliability of MgO layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6183.3. Required thermal stability of MTJ for NV-RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619
4. Spin-transfer torque RAM circuit technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620
4.1. Memory cell layout and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6204.2. Write circuits (write current control with write data, hierarchical configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6214.3. Future technology for higher density SPRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6224.4. 4F2 cell structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6224.5. Multi-level cell and its operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623
5. Non-volatile architecture for green computing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623
5.1. Basic circuitry layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6235.2. Board/chip and main memory level layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6245.3. System layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
6. Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626

1. Introduction

An innovation in computing architecture based on non-volatileRAM (NV-RAM), featuring instant-ON/OFF capability [1,2], is now

ll rights reserved.

(T. Kawahara).

advancing to enable further power reduction in addition to con-ventional low-voltage technology [3–6]. The main goal is to designcomputing equipment that quickly turns off when not in use andstays in the turn-off state as long as possible but can be turnedon instantly, with full performance capabilities, when needed. Thisis consistent with the overall increasing interest in a more sustain-able world. What is actually needed is a union or harmonization of

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Selectingtransistor

Word Line(WL)

Bit Line (BL)

(a) Inplane Magnetic Tunnel Junction(IMTJ)

Source Line(SL)

Barrier

Free layer

Pinned layer

(b) Perpendicular Magnetic Tunnel Junction(PMTJ)

SelectingtransistorWL

BL

SL

Barrier

Free layer

Pinned layer

Fig. 1. Memory cell structure with MTJs.

614 T. Kawahara et al. / Microelectronics Reliability 52 (2012) 613–627

power control and information–communication technologies. Thekey to achieving this is making sure that any internal status ofcomputation is stored before power is turned off, without consum-ing power. Non-volatile RAM is therefore a critical component. Itoffers an infinite number of fast write and read operations as wellas non-volatility. Furthermore, this memory is free of soft-errorscaused by radiation. Spin-transfer torque RAM (SPRAM) [7–10] isthe most promising solution among various candidates.

In this paper we review and discuss the prospects of SPRAMtechnology. In Section 2 the focus will be on the characteristicsof magnetic tunnel junction (MTJ) devices, from principles tomemory function, along with future prospects such as the perpen-dicular magnetization. Section 3 examines the issues of memorycell application of MTJs, with a roadmap of memory cell specifica-tions. Section 4 describes the design approach for large scale mem-ory chips. A description of a 4F2 memory cell and a multi-bit cellapproach are also provided. Section 5 summarizes the currentknowledge on non-volatile architecture, which ensures that anyinternal status of computation is stored before power is turnedoff, without consuming power.

2. Magnetic tunnel junction (MTJ) device technology

2.1. Development of MTJs with high tunnel magneto-resistance (TMR)ratio

An MTJ consists of two ferromagnetic thin films separated by atunnel barrier, as shown in Fig. 1. There are two kinds of MTJs;

CoFeB

MgO

5 nm

CoFeB

(a) TEM image for CoFeB/MgO/CoFeBMTJ just after deposition

(

Fig. 2. TEM ima

In-plane MTJ (IMTJ) where magnetization of ferromagnetic layerslies in the film plane, as shown in Fig. 1a, and perpendicular MTJ(PMTJ) where magnetization direction is perpendicular to the filmplane, as shown in Fig. 1b. Recently, PMTJs are being vigorouslydeveloped.

The resistance of MTJs depends on the relative orientation ofmagnetization in two ferromagnetic layers. This resistance changeis called the tunnel magneto-resistance (TMR) ratio, defined byDR/R = (Rap � Rp)/Rp, where Rap and Rp are the resistances for anti-parallel (AP) and parallel (P) magnetization configurations be-tween the two ferromagnetic films, respectively. Normally, themagnetization direction of one ferromagnetic layer, called a pinnedlayer, is fixed by exchange interaction with an adjacent anti-ferro-magnetic (AFM) layer, and the magnetization direction of the otherferromagnetic layer, called a free layer, can freely rotate.

The TMR effect was discovered by Julliere for a Fe/Ge/Co IMTJ atlow temperature in 1975 [11]. In 1995, a TMR ratio of more than10% at room temperature was first reported for IMTJs withamorphous alumina oxide (AlOx) barriers [12,13]. Since these re-ports, many research groups have gradually improved the TMR ra-tio using IMTJs with AlOx barriers. However, it was quite difficultto obtain a TMR ratio of more than 70% because the value is closeto the theoretical upper limit [14] predicted with Julliere’s formula[11], in which the TMR ratio only depends on the spin polarizationof two ferromagnetic layers.

In 2001, Butler et al. [15] and Mathon and Umerski [16] theoret-ically proposed the possibility of obtaining a remarkably high TMRratio of more than 1000% for fully crystallized (001) Fe/MgO/FeMTJs. They pointed out that this large TMR ratio originates from

5 nm

CoFeB

MgO

CoFeB

b) TEM image for CoFeB/MgO/CoFeBMTJ just after annealing at 375ºC

ges of MTJ.

T. Kawahara et al. / Microelectronics Reliability 52 (2012) 613–627 615

much larger transmittance of the electrons in the highly spin-polar-ized D1 band than those in other bands (D2 and D5) in (001) direc-tion of the bcc-Fe/MgO/Fe structure. In 2004, Yuasa et al. [17]demonstrated a TMR ratio of 88% at room temperature for fullyepitaxial Fe/MgO/Fe IMTJs deposited by molecular beam epitaxy(MBE), and Parkin et al. [18] demonstrated a TMR ratio of 220% atroom temperature for a highly oriented (001) MgO barrier and CoFelayers deposited by sputtering. Furthermore, Djavaprawira et al.demonstrated a TMR ratio of 230% at room temperature forsputtered Co60Fe20B20/MgO/Co60Fe20B20 IMTJs [19], and Hayakawaet al. demonstrated a TMR ratio of 260% for Co40Fe40B20/MgO/Co40Fe40B20 IMTJs [20]. The last two results are important becausethe IMTJs were deposited with a standard spin-valve structure withan AFM layer on a thermally oxidized Si wafer using a conventionalsputtering machine. In their examples, just after the film deposition,CoFeB layers were amorphous while an MgO layer had a highly(001) oriented poly-crystalline structure, as shown in Fig. 2a. Byannealing with a magnetic field of 4 kOe, the CoFeB layers werecrystallized in (001) direction, as shown in Fig. 2b. The TMR ratioincreased up to 350% after annealing at 400 �C, indicating that theformation of a highly oriented (001) CoFeB/MgO/CoFeB structureis essential to obtain a high TMR ratio. When annealing temperatureincreases to more than 400 �C, the TMR ratio of CoFeB/MgO/CoFeBspin-valve-type IMTJs decreases, which is attributed to the diffusionof Mn in an AFM layer into an MgO barrier. Recently, Ikeda et al. [21]demonstrated a TMR ratio of more than 600% at room temperatureand 1100% at 5 K using pseudo-spin-valve MTJs without an AFMlayer annealed at 525 �C. This TMR ratio at 5 K is compatible to thetheoretical expectation [15,16].

Regarding the development of PMTJs, it was not easy to deposithighly oriented bcc-(001) CoFeB/MgO/CoFeB on conventional per-pendicular ferromagnetic materials, such as CoCrPt alloy or Co/Ptmulti-layer, because these materials have different crystal struc-tures such as fcc or hcp types. Yoshikawa et al. [22] obtained aTMR ratio of more than 100% for L10-ordered FePt/MgO/Fe/ L10-or-dered FePt, and Yakushiji et al. [23] demonstrated a TMR ratio of90% with small resistance area product for Co/Pt supper lattice/Co-FeB/CoFe/MgO/CoFe/CoFeB/TbFeCo PMTJs. However, a complicateddeposition procedure for combining materials with different crystalorientation is necessary. Recently, Ikeda et al. [24] reported thatvery thin CoFeB film has perpendicular anisotropy and demon-strated a TMR ratio of more than 100% for simple CoFeB/MgO/CoFeBPMTJs. This discovery is valuable in triggering a paradigm shift fromIMTJs to PMTJs and leads to the mass production of PMTJs.

2.2. Spin transfer toque magnetization switching

Magnetic memories with an MTJ are considered a goodcandidate for NV-RAM. There are two kinds of magnetic memories

(a) Conventional MRAM using write methodwith magnetic field

RWL

WWL

WL

SLMTJMTJMTJ

BLIWWL

IBL

u

CMOS Transistor

Fig. 3. Comparison of magneti

characterized by their writing mechanism, as shown in Fig. 3.Fig. 3a illustrates a conventional magnetoresisitive RAM (MRAM)cell [25], which is based on magnetic field writing induced by cur-rent passing through a write word line (WWL) and a bit line (BL).This type of MRAM requires a larger current to reduce the MTJ sizebecause the required magnetic field increases inversely propor-tional to the width of the MTJ size. Fig. 3b illustrates a SPRAM cellwhich is based on spin transfer torque magnetization switching. Inthis new type of MRAM, the write operation can be performed bycurrent passing through MTJs, and there is no additional WWL,which leads to the reduction in cell size. Furthermore, since writecurrent can be reduced inversely proportional to the area of MTJs,as will be explained below, SPRAM is valuable for advanced scaling.

Spin-transfer torque (STT) magnetization switching was inde-pendently proposed by Berger [26] and Slonczwski [27] in 1996.Experiments soon followed where the phenomenon of large mag-netoresistance was used to detect magnetization reversal in ferro-magnetic multi-layers with large current densities flowingperpendicular to the plane of the layers [28–30]. Spin transfer tor-que reveals a new type of interaction between magnetization and aspin-polarized current, which is attributed to angular momentumexchange between the spins of local magnetic moment and freeelectrons passing through MTJs. The STT switching process is out-lined in Fig. 4. In AP to P switching, as shown in Fig. 4a, electronsshould flow from a pinned layer to a free layer. After electrons passthrough the pinned layer, the electrons with the same spin direc-tion as that of the magnetization in the pinned layer mainly remainand the current is spin-polarized. This spin-polarized current ex-erts STT on the magnetization of the free layer, and when theamount of spin-polarized current exceeds the threshold value,the magnetization of the free layer is switched. In P to AP switch-ing, as shown in Fig. 4b, electrons should flow from the free layer tothe pinned layer. After electrons pass through the free layer, theelectrons with the same spin direction as that of the magnetizationin the pinned layer pass through that layer. However, the electronswith the opposite spin direction is reflected at the boundarybetween an MgO barrier and the pinned layer and injected intothe free layer. This current exerts STT on the magnetization ofthe free layer, and when the amount of the spin-polarized currentexceeds the threshold value, the magnetization of the free layer isswitched.

The intrinsic threshold current density Jc0 is the most importantparameter that characterizes STT magnetization switching. Thethreshold current density for IMTJs is expressed by the followingequations [31,32]:

JP!APc0 ¼ aceMst=ðlBgð0ÞÞ � ½ðHex þ HdipÞ þ ðHki þ HdÞ� ð1Þ

JAP!Pc0 ¼ aceMst=ðlBgðpÞÞ � ½ðHex þ HdipÞ � ðHki þ HdÞ� ð2Þ

WL

SL

BL

MTJMTJ

(b) Spin transfer torque RAM (SPRAM)sing write method with spin-polarized current

CMOS Transistor

IBL

IMTJ

zation switching method.

BL

Free layer

Barrier

Pinned layer

Electron

SLCurrent

(b) Parallel (P) to Anti-Parallel (AP) switching(a) Anti-Parallel (AP) to Parallel (P) switching

BL

Free layer

Barrier

Pinned layer

Electron

SLCurrent

Spin transfer torque Spin transfer torque

Fig. 4. Spin transfer torque magnetization switching.

0

2

4

6

8

1 10 100 1000Pulse width p (ns)

Cur

rent

den

sity

Jc

(x10

6A/

cm2 )

Precession region

Thermal activationregion

Jc=Jc0[1-(kBT/E)ln( p/ 0)]

Jc0

Fig. 5. Switching current density (Jc) as function of pulse duration.

10

8

6

4

2

0

J c0

(MA/

cm2 )

(2) Co40Fe40B20based SyF

(1)SingleCo40Fe40B20

(3)Co20Fe60B20based SyF

(100x200nm2)

(4) SingleCo20Fe60B20

Ru

MgO

0 20 40 60 80 100 120 140

SyF freelayer

Pinnedlayer

Fig. 6. Switching current density (Jc0) vs. thermal stability factor D defined bythermal stability E/kBT.


gðhÞ ¼ P=½2ð1þ P2Þ cos hÞ� ð3Þ

where a is the Gilbert damping constant, c is the gyromagnetic con-stant, e is the charge of electrons, t is the thickness of the free layer,lB is the Bohr magneton, Ms is the saturation magnetization of thefree layer, g(h) is the STT efficiency defined by Eq. (2), and h is the an-gle of the magnetizations between the free and pinned layers. Thenotations Hex, Hki, and Hdip are the inplane applied, in-plane anisot-ropy, and dipole fields from the pinned layer acting on the free layer,respectively. The notation Hd is the effective demagnetization field,and if the magnetization of the free layer has the perpendicularanisotropy field Hkp, Hd = Ms/l0 � Hkp. The threshold current densityfor PMTJs is expressed by the following equations [31,33]:

JP!APc0 ¼ aceMst=ðlBgð0ÞÞ � ½�ðHex þ HdipÞ þ ðHkp �Ms=l0Þ� ð4Þ

JAP!Pc0 ¼ aceMst=ðlBgðpÞÞ � ½�ðHex þ HdipÞ � ðHkp �Ms=l0Þ� ð5Þ

On the other hand, the thermal stability factor D defined by theenergy barrier (E), Boltzmann constant (kB), and temperature (T)(E/kBT) is particularly important for discussing the non-volatileproperties of SPRAM such as retention and read disturbance. Thethermal stability factor can be expressed as

D ¼ ðMsHkiVÞ=ð2kBTÞ for IMTJs ð6ÞD ¼ ½MsðHkp �Ms=l0ÞVÞ=ð2kBTÞ for PMTJs; ð7Þ

where V is the volume of the free layer. In PMTJs, Jc0 is directly pro-portional to anisotropy Hkp �Ms/l0, which determines the thermalstability of the free layer. In IMTJs, however, Jc0 must overcome theadaptive factor Hd, which does not contribute to the stability of thefree layer. This is the reason PMTJs are vigorously being developedfor SPRAM.

Fig. 5 shows the switching current density Jc as a function ofpulse duration sp. As shown in Fig. 5, Jc steeply increases in thesp region of less than 10 ns. This region is called the precessionregion where STT switching occurs with precession motion ofmagnetization in the free layer around the effective magnetic field.On the other hand, in the sp region of less than 10 ns, Jc can bewritten as,

Jc ¼ Jc0½1� D�1 lnðsp=s0Þ�; ð8Þ

where s0 is the attempt pulse width, which normally equals 1 ns. Byfitting the experimentally obtained Jc vs. ln(sp/s0) using Eq. (8), one

SiO2/Si sub.

Ta(5)Ru(10)Ta(5)

CoFeB(1.0 )

MgO(0.85) CoFeB(1.7)

Ta(5)Ru (5)Cr/Au

40 nm-50-4

0 5 10 15 20 25

1 ns 1ms 1 s

-25

0

25

50

75

-2

0

2

4

6

J c(M

A/cm

2 ) Ta=300

ln ( p/ 0)

Ic (A)

p (sec)

(a) Structure and SEM image of CoFeB-based PMTJs

(b) Measured p vs Jc plot for a CoFeB-based PMTJ

Fig. 7. Measurement of MTJ with diameter of 40 nm.


can obtain Jc0 and D [34], as shown in Fig. 5. This region is called thethermal fluctuation region where the thermal fluctuation of magne-tization in the free layer assists STT magnetization switching.

Fig. 6 summarizes our previous experimental data on Jc0 and Dfor IMTJs [35–37]. This figure includes four types of CoFeB/MgO/CoFeB spin-valve MTJs; (1) a Co40Fe40B20-based single free layer,(2) synthetic ferri-magnetic (SyF) Co40Fe40B20-based free layer,(3) Co20Fe60B20-based single free layer and (4) Co20Fe60B20-basedSyF free layer. A SyF free layer consists of two ferromagnetic layersseparated by a very thin Ru spacer, as shown in the inset of Fig. 6.The two ferromagnetic layers are anti-ferromagnetically coupledwith each other, and the magnetization of the two ferromagneticlayers is aligned in an AP configuration. Therefore, the magneticflux is closed in a SyF free layer, resulting in more stability for mag-netic field perturbation and larger coercivity.

We define Ic0/D (Ic0 = Jc0 � S, where S is the area of an MTJ) as afigure of merit for STT magnetization switching, which is STT effi-ciency per energy. As shown in Fig. 6, Ic0/D of MTJs with a SyF freelayer is smaller than that with a single free layer. A detailedmechanism for small Ic0/D of IMTJs with a SyF free layer has not beenclarified yet. However, Ichimura et al. [38] suggests that STT exertedon the magnetizations of two ferromagnetic layers in the SyF freelayer tends to rotate in the same direction, and this tendency inducesthe cooperative reversal of magnetizations in the two ferromagneticlayers. Yen et al. [39] experimentally showed that Ic0/D of IMTJs issmallest at the optimum anti-ferromagnetic coupling constant. Inaddition, Ic0/D of MTJs with a Co20Fe60B20-based free layer is smaller

Fixed layerFree layer

Vgs Vbs (= 0V)

Fixed layerFree layer

Vgs Vbs

Vss

Vdd

Vdd

Vss

Vss

Vdd

Vdd

Vss

(a) Source-ground (P -> AP) (b) Source-follower (AP -> P)

MTJ

MT

Fig. 8. Transistor operation mode in writing.

than that with a Co40Fe40B20-based free layer. This is attributed to alarger Hkp of Co20Fe60B20. Yakata et al. [40] pointed out that Hkp ofCoFe alloy increases with its Fe composition. Since the origin of thisperpendicular anisotropy is the Fe–O coupling at the boundary be-tween MgO and CoFeB [41], an increase in Fe composition leads toan increase in Hkp.

As mentioned in Section 2.1, Ikeda et al. recently demonstratedCoFeB/MgO/CoFeB-based MTJs with a TMR ratio of more than100%. They also fabricated an MTJ with a diameter of 40 nm andmeasured Jc0 and D [24], as shown in Fig. 7. The average Jc0 forAP to P and P to AP switching is 3.9 MA/cm2 (threshold currentIc0 = 49 lA), and D is 43, indicating Ic0/D = 1.1. This value is muchsmaller than that of IMTJs (minimum Ic0/D = 3.3), which showsthe high potential of PMTJs for future downsizing of SPRAM mem-ory cells.

3. Memory cell scalability and reliability with MTJs

This section discusses the basics of memory cell technologyincluding important design issues, cell current, reliability, andthermal stability.

3.1. Memory cell scalability in terms of write current

Fig. 8 shows the transistor operation mode in writing; the volt-age relations between the cell MOS transistor (MS) and the MTJ. Anexample of connecting a fixed layer of a MTJ with the MS is shownin this figure. When the writing of a P state to an AP state is accom-plished, a high voltage of Vdd is connected to the free layer(Fig. 8a). For the MS, the source and substrate are connected to alow voltage of Vss (ground). When the MS gate voltage turns toVdd, the current flows from the free layer to the fixed layer, andthe magnetization of the free layer is reversed. At this time, theMS operation mode is called a source-ground. The gate to sourcevoltage (Vgs) is large enough for the Vdd, and the substrate tosource voltage (Vbs) is 0 V. This provides a large current. Since

MTJ size F 2 F 2 F 2 F 2

Tr gate width, W 10F 4F 2F F

Cell size 40F 2 16-12F 2 8-6F 2 4F 2

Fig. 9. Transistor and cell size.

Id= 300 µA/µmJc= 4.0 MA/cm2

2.0

1.0Tr. W= 10F

4F

2F

1F

Feature size, F (nm)

1

10

100

1000

90 65 45 32 22

TMR size: FxF

0.5

: Write current: Transistor’s current drivability

Tran

sist

or d

river

bilit

y,

Id, I

c (µ

A)

Writ

e cu

rren

t,

Fig. 10. Required current for reversing the TMR device and transistor drivability ineach generation.


MOS technology is developing in a direction where the current perunit gate width can be maintained in future generations, 800 lA–1 mA/lm is expected to be used for high-performance MOSs, and400–600 lA/lm for low-power MOSs, which is known as the ITRSroadmap. On the other hand, Fig. 8b shows the mode of writingfrom AP to P states, and the connection to the power supply(Vdd, Vss) is opposite to that in Fig. 8a. The Vss is connected tothe free layer in an MTJ, the drain of the MS is connected to theVdd, and the substrate is connected to the Vss. In this mode, thesource voltage is the same as the voltage for the fixed layer ofthe MTJ. This operational mode is called the source-follower.Although the gate voltage changed to Vdd, Vgs decreases due tothe voltage for the fixed layer of the MS device, and the thresholdvoltage increases due to the substrate effect, where the voltage ofthe substrate to the source, Vbs, becomes negative. Through theseeffects, the current that MS can flow through in the mode shown inFig. 8b reduces to about half that of the current in Fig. 8a. By takingthis into consideration, we should set the size (gate width) of theMS, pMOS, or nMOS, the connection of whichever side of the MTJto MS, and the substrate effect to be constant. The size of the MS

Fig. 11. Write voltage and

determines the size of the memory cell. The results are shown inFig. 9, ignoring the effect of the course pitch of the upper level me-tal layer and assuming the size of the TMR is constant as F2 (F: fea-ture size). The MS size, which is the gate width, should be reducedto 2F or less to create a dynamic RAM (DRAM)-level cell size of acurrent 8–6 F2. Fig. 10 shows that the relation of the current neces-sary for reversing the MTJ and the current the MS can flow in eachgeneration (feature size). The current per unit gate width is300 uA/um, where MS is in the source-follower mode and the cur-rent is reduced by half compared to that in the source-groundmode. The current when using the MS is proportional to F basedon the given gate width, such as 10F or 2F, but the current to re-verse an MTJ is proportional to F2 in the given threshold currentdensity of Jc. Therefore, the MS can supply sufficient current neces-sary for writing using a smaller gate width in a finer process. Thatis, this memory cell is highly scalable.

3.2. Reliability of MgO layer

The next issue we discuss concerns the vertical structure of anMTJ. A tunnel barrier layer of MgO is used in the MTJ, and the reli-ability of this film is important. The voltage applied to the TMRduring writing, VW, should be smaller than the dielectric break-down voltage VBD, which is considered a continuous writing oper-ation spanning 10 years. Note that this voltage is higher whenwriting to the AP state than for writing to the P state. The TMR ratioand the resistance area product (RA) are restricted by this condi-tion. The write voltage of VW is expressed as

Vw ¼ Jc0 � RA� MR100þ 1

� �; ð9Þ

where Jc0 is the threshold current density, RA is the resistance areaproduct [42], and MR is the TMR ratio given as a percentage. A largeJC0, RA, and TMR ratio, all components are determined by material tech-nology, increase VW. The dielectric breakdown voltage is expressed bythe following equation, where EBD [43,44] is the breakdown electricfield of the MgO film and tMgO is the MgO barrier thickness:

VBD ¼ EBD � tMgO ð10Þ

The value of EBD and resultant VBD were studied for enduring10 years of writing using Time Dependent Dielectric Breakdown(TDDB) characteristics. In an actual device, JC0 and EBD, also

reliability of MgO film.

Fig. 12. Required thermal stability (E/kBT) dependence of chip capacity.


resultant VBD, depend on RA and MR according to the materials andstructure. In Fig. 11, the relation between VW and RA is shown fromthe design aspect according to Eqs. (9) and (10), with these valuesas parameters. That is, JC0 from 0.5 to 4 MA/cm2, EBD from 4 to8 MV/cm, and VBD with different thicknesses of MgO. The TMR ratiowas also treated as a parameter and varied from 100%, 200%, and600%. This figure suggests that a low JC, small RA, and high VBD

are preferable. However, in actual design, we should set themwhile taking into consideration that the power-supply voltage,MOS resistance, and resistance change of the TMR (AP or P) in read-ing are sufficiently large compared to the MOS.

3.3. Required thermal stability of MTJ for NV-RAM

The required thermal stability of an MTJ is estimated to handlethe memory specifications in our work. Logic application needs tobe determined in another study. When data are written to a SPRAMcell to store information, the current passing through the MTJ in-duces a spin-transfer switching of the free layer in the device. Thereversal probability of a cell having a cell current Icell is given by

P1 ¼ 1� exp � ts0

exp � EkBT

1� Icell

Iw

� �� ; ð11Þ

Ther

mal

sta

bilit

y E/k BT

4M 16M 64M 256M 1G 4G60

65

70

75

80

85

90

Chip capacity (bit)

25%

10%

IR/IW=33%

16-kb parallel readtR/tcycle= 10%

Fig. 13. Required E/kBT dependence of chip capacity.

where IW is the write-threshold current, s0 and t are the inverse at-tempt cycle time (s0 = 1 ns) and cell current duration time [45].When considering non-volatile operations, all cells must maintaintheir states during read operation and data retention period forthe chip in order to operate correctly. Fig. 12a and b shows the as-sumed worst operation patterns. We took the DRAM-compatibleoperation mode for a giga-bit class SPRAM and data retention modelfor non-volatile operation into consideration. In the DRAM-compat-ible operations, a read command with the same address is issuedevery tcycle period for 10 years. The 16-k cells also have a read cur-rent (IR) over a period of 10% of the tcycle in each read cycle. In theretention mode, a no command is issued; therefore, no currentflows through the MTJs. By expanding Eq. (11) for each case, thechip failure rate (FChip) is estimated using the following equation:

Fchip ¼ 1� exp �mts0

exp � EkBT

1� Icell

Iw

� �� ð12Þ

where m is the number of bits accessed at the same time, and t isthe total duration (10 years � tread/tcycle). The required E/kBT canbe estimated using this equation by assuming Fchip. This equationcan also be used for the data retention mode by having m and tbe the total capacity and a 10-year period, respectively.

Fig. 13 plots the dependence of the calculated required EkBT onchip capacity with the read/write current ratio as a parameter. ADRAM-compatible operation with a 16-kb parallel read is assumed.The required EkBT increases as the chip capacity increases under alow read/write current ratio condition of 10%. This means that therequired EkBT under a low read/current ratio is limited by the dataretention characteristics. On the other hand, EkBT is not related tothe integration and becomes constant under a large read/write cur-rent ratio condition. This means the necessary EkBT is determinedby the read disturbance. Note that this constant EkBT should beachieved as an absolute value at each generation where the featuresize differs and the MTJ size is F2 � 2F2. For example, assuming16 Mb by 90 nm and 4 Gb by 32 nm with the same read/currentratio of IR/IW = 33%, we should achieve an EkBT = 85 with a TMR sizeof F2 � 2F2 with F of 90 nm for a 90-nm generation. For a 32-nmgeneration we should obtain the same EkBT of 85 at F of 32 nm witha TMR size of F2 � 2F2. The necessary EkBT value for DRAM-compat-ible operation is higher than that of SRAM-compatible operationbecause the number of bit counts accessed at the same time is lar-ger for page mode operation.

Cell size (F2)0 10 20 30 40 50

Gat

e si

ze W

(F)

0

5

10

15

20

25

1T1R cell

2T1R cell

1T1R cell (15 F2)2T1R cell (12F2)

SLcontact

TMR contact

(a) 2T1R and 1T1R cell layout with gate width of 4F

(b) Comparison of 2T1R and 1T1R cell layout

Fig. 14. Layout and comparison of 2T1R and 1T1R cell.

4Mb

256kb sub-array block

SA

32Mbchip

Localized write driver(WB, WS)

Main-word driver

32kb sub-array

WB1WS1

WGB0

WBS0-7 WB0-7WL0 WL255RS0-7RGB0

RS0

Vd

Vs

WGB15RGB15RS15

SSL0-7WGB0-15

GRBS0-15

128-kb sub-array

SA

SL1

RB1

Fig. 15. Hierarchical array configuration.


4. Spin-transfer torque RAM circuit technology

The major challenges in designing high-density SPRAM are sta-ble read operation with small resistance difference and steadywrite operation to control the magnetization of the free layer ofthe MTJ according to the write data. In addition, high-densitymemory cell structure and array configurations satisfying therequirement of read and write characteristics of the MTJ are alsorequired.

4.1. Memory cell layout and structure

A small cell area with enough current drivability for switchingthe magnetization of the free layer of an MTJ is desired to achievea high-density SPRAM, which has the necessary gate width men-tioned above. A cell with two transistors and one MTJ (2T1R) hasbeen proposed [46] to fabricate such a cell. Fig. 14a shows this2T1R cell layout and the conventional 1T1R layout. To minimizethe cell area in the 2T1R layout, the isolation area between a cell

0

0.2

0.4

0.6

0.8

1

50 100 1k200 500 2kNumber of bits on BL (bits)

Cur

rent

deg

rada

tion

ratio

0

20

40

60

80

100

Driv

er a

rea

over

head

(%)

BL

SL

n bits

Localizeddriver (WB)

Localizeddriver (WS)

WL0 WLn-1

(a) Sub-array configuration (b) Current degradation ratio and area overhead

150 nm CMOS Process

Area overhead

Current degradation

Fig. 16. Dependencies of current degradation ratio and area overhead on number of bits on local bit and source lines.


and an adjacent cell in the BL direction is replaced by the transistorof the adjacent transistor. Fig. 14b shows the relations between celllayout area and gate size of the 2T1R and 1T1R cell layouts. The2T1R cell layout can fundamentally have a larger MS gate widththan that of the 1T1R cell layout. For example, even in/with a cellarea of 8F2, the transistor gate size can be 2F, while the gate sizeof the 1T1R cell layout is 1.67F. Therefore, when the required gatewidth defined by the writing current is larger than 2F, the 2T1Rlayout results in a smaller chip size.

4.2. Write circuits (write current control with write data, hierarchicalconfiguration)

To distribute sufficient writing current for all cells in a large-scale chip, the effects of parasitic resistance of the BL and sourceline (SL) should be considered, i.e., BL voltage changes that occurdepending on the memory cell position, and also reduced writingcurrent. To prevent the reduction of writing current, a hierarchicalarray configuration has been introduced [46]. Fig. 15 shows thememory array block of a 32-Mb SPRAM chip with hierarchicalarray configuration. The number of cells (n) connected to a BLand SL impacts the write current and chip size. That is, when the

Csa

Cb

'0'

AMP

Csa

Cb

AMP

'1'

Read-outcells SW

Referencecells

ISA

ISAISA

Csa

Cb

Csa

Cb

ISA

Fig. 17. Concept of ‘1’/‘0’ dual-array equalized reference scheme.

current flows, the voltage drop due to the resistance of the SLand BL decreases the writing current. Fig. 16 shows the dependen-cies of the current degradation ratio and area overhead on thenumber of bits on the BL and SL assuming 150-nm CMOS process,which is used for fabrication of 32-Mb SPRAM chips. The decreaseis greater when there are more than 512 bits per BL. In contrast, theoverhead of the area increases with a decreasing number of mem-ory cells because the local write drivers (WB, WS in Fig. 16a) arenecessary for this unit. In the 32-Mb chip, 256 bits per BL wasimplemented for a secure write current. In the write operation,the global BL and SL are driven from the global write driver accord-ing to the write data stored in a sense amplifier (SA). The global BLsare divided into read and write ones to reduce the parasitic capac-itance for fast read operation and reduced power. The local writedrivers handle the small number of memory cells that are con-nected to the BL (BL1) and SL (SL1). The write pulse width isdefined in the local write drivers by the activation period of theBL- and SL-select signals.

In read operation, the signal voltage in an SA is defined by theresistance difference between P and AP states and the amount ofread current. At present, the resistance ratio between the P andAP states of an MTJ is about 100%. Using STT switching for writeoperation, the difference between read and write operations is justthe amount of current through the MTJ. From this point of view,read current should be suppressed to prevent data destruction dur-ing read operation. In addition, the temperature dependence of theMTJ should be considered. Therefore, a precise reference genera-tion is the key for stable read operation because the signal voltage

0 10 20 30 40 50Time (ns)

RE activation SA activation

Read cell “1”

Read cell “0”Equalized reference

MR ratio: 100%1.5

1.0

0.5

2.0

0

Inpu

t vol

tage

for S

A (V

)

Fig. 18. Simulated waveform of ‘1’/‘0’ dual-array equalized reference scheme.

0.1

1

10

100

1000

180 130 90 65 45 32 22 15Feature size (nm)

Cur

rent

(µA)

Write

Read

In-plane Perpendicular

Hard to sense, or slow speed

Free layer

Pinned layer

Fig. 19. Projection of read and write current.

-0.5

0

0.5

1.0

1.5

2.0

4.0

0 10 20 30 40 50 60 70 80 90 100-1

0

1

2

3

4

8C

urre

nt I c

ell(

a. u

.)

WL

Volta

ge (V

)

Time (ns)

Anti-parallel (AP) Parallel (P)2.5 5

3.0 6

3.5 7TMRWL

Icell

VDD

VSS

WLIcell

No switching

Free layerPinned layer

RP

RAPR

Icell

Fig. 20. Measured waveform in write operation.


generated from the memory cell is small. To solve this problem, wedevised a reference generation scheme which uses the MTJ. Fig. 17shows the proposed ‘1’/‘0’ dual-array equalized reference schemein which average current generated by two MTJs with P and APstates is used [46]. In this scheme, an switching element betweenarrays of SW shorts between the input nodes of the two

Bit line (BL)

Source line (SL)

Word Line(WL)

TMRWBL

Write enable(WE)

Sense Amp. enable(SAE)

IORef. level(Vref)

MC

Column select(YS)

WSL

SAO BLD

SLDLA

SA

(a) Block diagram

Fig. 21. Block diagram and timing chart of d

neighboring SAs and averages the read current of reference cellsstoring ‘1’ and ‘0’ data. The capacitance of the input nodes of theSAs can be balanced because the capacitance of the two read pathsis connected to two memory cells by generating one reference withboth SAs. As a result, the reference level, even in early transitions insensing, stays between the ‘1’ and ‘0’ data, as shown in Fig. 18.Therefore, the start time of the SAs can be set earlier, i.e., high-speed access is possible even with a TMR ratio of 100%.

4.3. Future technology for higher density SPRAM

The perpendicular recording method for an MTJ is promising forfuture SPRAM. The perpendicular recoding technology will beintroduced in 50-nm generation and beyond, as shown in Fig. 19.This technology achieves both higher thermal stability and lowerthreshold current than those of the in-plain recording scheme.However, the reduction in the threshold current leads to a smallread current. As a result, the access time of the chip degrades inthe advanced process nodes due to low read current. To preventthe degradation of the access time, a disruptive read and restoringscheme has been proposed [47]. This scheme is based on the mea-surement results shown in Fig. 20 [48]. The MTJ keeps its state inthe early stage of the current pulse when the current comparableto the threshold current is input to the MTJ. Fig. 21 shows the cir-cuit configuration and operation waveforms of this scheme [47]. Byusing the no switching period, the stored data can be read and sentto the SA. Then, the data is written back to the memory cell toensure the stored data in the memory cell. By outputting the SAdata to the I/O during restoring operation, the restoring operationdoes not affect the access time. In addition, this scheme can reducethe required E/kBT, because the requirement only for data retention(10 years for NVRAM and 100 s for low-power RAM) is to be con-sidered for the estimation of the required E/kBT. Note that SPRAMhas an infinite endurance.

4.4. 4F2 cell structure

When the process technology progresses and the required writ-ing current is less than the drive current supplied by the transistorwith a gate width of F, we can reduce the cell area to 4F2 by using avertical MS. The vertical transistor is promising for DRAM to reducethe memory cell size to 4F2 [49]. Fig. 22 shows the 4F2 memory celllayout and structure using a vertical MS and an on-axis MTJ[47,50]. In this structure, the MTJ is on the top of the drain region

WL

BL

SL

Read Restore

Vref

SAE

WE

SAO

WBL

WSL

YS

IO

(b) Timing chart

isruptive reading and restoring scheme.

Fig. 22. 4F2 memory cell layout and structure.

MTJ1

MTJ2

BL

SL

WL

72 nm

Fig. 23. Schematic view of MLC SPRAM with stacked TMR devices.


of the transistor to reduce the cell area. In this case, the perpendic-ular recording is suitable for the memory device because the shapeof the MTJ in the largest area is square with an area of F2.

4.5. Multi-level cell and its operation

A multi-level technique is the one of the means to improve chipdensity. However, an MTJ has only two states, which means thatonly one bit can be stored with one MTJ. To fabricate a multi-levelcell using an MTJ, a memory cell structure with stacked MTJs hasbeen proposed [51], as shown in Fig. 23. The number of bits stored

Fig. 24. Concept of two-step r

in one memory cell is equal to the number of stacked MTJs. In thismemory cell structure, multiple levels of resistance are obtained bychanging the size of the MTJs to achieve different resistance statesand threshold currents. Regarding circuits technique for the multi-level SPRAM, two-step read and write techniques have been pro-posed for two-bit cell [51]. Fig. 24 shows the concepts of thetwo-step read and write techniques with two stacked MTJs. Inreading operation, the resistance state of the TMR with small sizeis read by using mid level reference, and then the resistance stateof the TMR with large size is read by using higher or lower refer-ence level depending on the stored data of TMR with small size.By first using mid-level reference, almost the same access timecan be achieved as that of a single level cell. In writing operation,each resistance state of the two MTJs can be controlled indepen-dently by using the difference in the threshold current of two MTJs.The MTJ with large size and small threshold current is written first,and then the MTJ with small size and small threshold current iswritten. This writing order is in opposite to reading one. In addi-tion, if two MTJs are written to same state, the writing operationhas done with write current for TMR with large size.

5. Non-volatile architecture for green computing

Having a system quickly turn off when not in use and instantlyturn on when needed without sacrificing full performance isbecoming a necessity [53,54]. We call such an architecture non-volatile architecture. Any internal status should be memorizedwithout consuming power. We then can instantly turn on any typeof computation and resume the state prior to interruption. This re-quires NV-RAM discussed in detail in the previous sections. Thisapproach is adaptive to wide time and area domains (basic circuitlayer to system layer).

5.1. Basic circuitry layer

Fig. 25a shows the non-volatile architecture in a basic circuitlayer. This is also called non-volatile logic-in-memory architecture.

ead and write techniques.

Fig. 25. Logic level non-volatile architecture.

Fig. 26. Board/chip level non-volatile architecture.


Storage elements are distributed over a logic-circuit plane, whichcan greatly reduce global routings in LSI chip. In general, it is diffi-cult to implement such logic-in-memory circuits. By using MTJscombined with CMOS gates, however, the logic-in-memory circuitcan be implemented. The MTJ has several potential advantagessuch as non-volatility, unlimited endurance, fast writability, scala-bility, CMOS compatibility, and 3D stacking capability. Since thestorage element is non-volatile, static power is completely cutoff. Magnetic tunnel junctions are located on the CMOS layer to re-duce chip area. Storage and logic element functions can be mergedin this architecture to further reduce the chip area. Wire delay anddynamic power is also reduced. Fig. 25b shows an example ofbasic-cell level example [52], where a full adder with a non-volatilestorage cell was designed and demonstrated with a shown chip.Power consumption can be controlled by a unit of the commandline, and the leakage current reduced in the intermittentstand-by state. The experimental results show that the dynamic

power is reduced to less than one-fourth while maintaining thesame performance compared to nominal CMOS circuits.

5.2. Board/chip and main memory level layer

Board/chip level non-volatile architecture [53] is shown inFig. 26. Typical digital equipment uses a main board that includesthe CPU, special purpose processing units, a BUS, and memory, asshown in Fig. 26a. An HDD and/or NAND are used for the file data.In the memory block, both ROM and RAM are used (file memorymight take on the role of ROM). ROM is non-volatile with limitedendurance, and RAM is volatile with an infinite number of writecycles. In this memory structure, ROM stores the program and code,and the code is expanded into the RAM area for use. This takes a rel-atively long time and uses a large amount of power. Some of the nec-essary code will be taken from file memory, which keeps the systemwaiting a long time before use. When such a system is shut down, it

Fig. 27. Impact of main memory level non-volatile architecture on power reduction.


also requires time and power to store the status data back into thenon-volatile memory. With the non-volatile structure shown inFig. 26b, which offers both non-volatility and an infinite number ofwrite cycles, the number of devices can be reduced and the timeneeded for commutation between ROM and RAM in a conventionalsystem is eliminated. It also reduces the power needed to senseand receive the signal through the BUS. This enables instant-onand quick software changes from the normally off state, which is adirect benefit for end users. Furthermore, this architecture bringsprogrammable on-the-fly functions and finer time grain power con-trol. This technology is also expected to be widely used in NAND flashmemory in the file memory region in the future. The CPU layer can byapplied to non-volatile architecture. This scheme achieves quickoverall turn-off and turn-on. Therefore, there is no need for the con-ventional sleep mode. High energy efficiency is achieved duringoperation and no DC power is consumed in the CPU’s long standbystate, as occurs often in most business applications. Elimination ofthe need for power to communicate between the main memoryand CPU is also expected.

Furthermore, power reduction of the main memory layer is alsoremarkable especially in the application of cellular phone/smartphone. The concrete example of this effectiveness is shown as

CPU

Memory

StoFile Memory (HDD/SSD)

ALU(FF)

Register

1st Cache

2nd Cache

DRAM

File Cache

ROM

e-File Memory (DRAM)

(a) Conventional Architecture

# Commit

# Work

# Storage

Fig. 28. Non-volatile architecture

follows. A cellular phone example is shown in Fig. 27. Total memorycapacity of high-end cellular phones/smart phone will double in3–4 years. According to this, stand-by power of DRAM will alsoincrease up to 1 mA. We assume the low power version of DRAM.Such large stand-by power is expected. However, when we change1/5 of DRAM to non-volatile RAM, we can turn off the DRAM with-out degrading performance. The power is reduced to by the order.Since we can assume the memory capacity of one chip will increase,almost the same stand-by power is maintained.

5.3. System layer

Fig. 28 shows the non-volatile architecture in a total computingsystem compared with conventional architecture. In conventionalarchitecture (Fig. 28a), memory systems are constructed accordingto a deep hierarchy based on speed and capacity to enable bettercomputing performance. Volatile and non-volatile memories andstorage are often combined. High-speed operation with large-scalememory space has been achieved by combining high-speed withsmall-capacity memories and low-speed with large-capacity mem-ories. In actual operation, though, this sort of design leads to slowstart-up, long idle times, and low power efficiency. Examples of

: Non-Volatile: Volatile

rage

NV-CPU

NV-RAM

ALU(NV-FF)

NV-Register

NV-1st Cache

NV-2nd Cache

File Memory(HDD/SSD)

NV e-File Memory

NV-Main Memory

NV-File Cache

(b) Non-volatile Architecture

# Commit# Work

# Storage

in total computing system.


this kind of complex control are the mechanisms of booting andshutting down an OS, dual redundant systems for main memorybackup, and log and dump systems. Fig. 28b shows a system whereall hierarchy structures including the CPU use non-volatilememory: non-volatile architecture in a total computing system.The advantage of such architecture is that devices are free fromhierarchal constraints, which originate from mixing volatile andnon-volatile memories. Furthermore, data stored during operationcan be retained in the state it was in before power being turned off.This enables IT equipment to be turned on instantly and resumethe state prior to interruption. This is somewhat of a return tothe systems developed at the dawn of computing when the controlof memory was quite simple.

By comparing Fig. 28a and b, especially, in conventional archi-tecture, any tentative change in the computational state can befixed only by writing to the HDD. This is called commit. On theother hand, a system with all non-volatile memory, as shown inFig. 28b is expected to solve this problem. Commit can be doneat the main memory level. The speed difference between two sys-tems reaches 1000 times, and the data stored during operation canbe retained in the state it was in before power was turned off. Thisenables IT equipment to be turned on instantly and resume thestate prior to interruption.

Therefore, non-volatile architecture can dramatically savepower while maintaining its performance. Non-volatile RAM playsa vital in this. However, there are issues to address. A new OS forthe best use of non-volatile memory needs to be developed. Away of activating memory contents for users, handling the securitycontent and a compiler that schedules on/off need to be developed.And in addition, the problem to be solved is this computation mustbe the same as uninterruptible computation. These issues shouldbe addressed through cooperation on the device and system sides.

6. Conclusion

We reviewed the developments of MTJ devices with high tunnelTMR ratios. A TMR ratio of more than 600% at room temperaturewas discussed. Also the very thin CoFeB film in MTJ was shownto exhibit perpendicular magnetization and a TMR ratio of morethan 100%. Moreover, we examined the guidelines for reducingthe magnetization switching current, which corresponds to thewrite current in memory applications. Furthermore, the write cur-rent in a perpendicular MTJ system can be reduced independentlyof the thermal stability, which results in small write currents, ahigh read disturbance, and a long retention time. For the cell struc-ture and operation of memory applications, we discussed the de-sign considerations such as the voltage condition and thethermal stability. The formulation for calculating the thermal sta-bility is described by taking into account the memory-chip specifi-cations. The thermal stability should be set large enough to protectthe reading disturbance and to enable sufficient retention time, rel-ative to the array structure and usage. We described an array struc-ture, a sensing scheme, and a disruptive read operation designedfor large-scale integration at the circuit level. Finally, we discusseda multi-level cell and its operation. Using such technologies, theresulting memory using MTJ devices and the spin-transfer torquemechanism would be expected to represent a true NV-RAM thatwould enable instant-on and -off functions of IT equipments. Thiswould drastically reduce the power consumption of the IT equip-ments and of the related infrastructure while still preserving theirhigh performance.

Acknowledgements

This work was supported in part by the High-Performance Low-Power Consumption Spin Devices and Storage Systems program

(headed by Professor Hideo Ohno of Tohoku University) under Re-search and Development for Next-Generation Information Tech-nology of MEXT, and also by the Japan Society for the Promotionof Science (JSPS) through its Funding Program for World-LeadingInnovative R&D on Science and Technology (FIRST Program).

The authors would like to thank S. Ikeda, T. Meguro, R. Sasaki,M. Yamanouchi, F. Matsukura, and H. Hanyu of Tohoku University;K. Miura, H. Yamamoto, J. Hayakawa, N. Matsuzaki, Y. Mouri, T. Ish-igaki, S. Yamaguchi, S. Mitani, M. Odaka, I. Morita, T. Hirata, H.Hasegawa, H. Takahashi, Y. Goto, and H. Matsuoka of Hitachi.

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http://www.aspdac.com/aspdac2011/archive/pdf/1K-1.pdf

spin-transfer torque ram technology: review and prospect

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