spin qubit system integration with advanced semiconductor … · 2021. 3. 24. · the ‘fab ’...
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Intel ConfidentialDepartment or Event Name 1
Spin Qubit System Integration with Advanced Semiconductor Manufacturing
IEEE Quantum Workforce Development
Lester Lampert, Ph.D.
Quantum Computing Lab
IEEE Quantum Workforce Development 2
Outline
• What is advanced semiconductor manufacturing?
• Why semiconductor spin qubits?
• Spin qubit tutorial
• Porting the traditional FAB flow to spin qubits
• Scaling of semiconductor spin qubit systems
• Summary
IEEE Quantum Workforce Development 3
What is advanced semiconductor manufacturing?
• The ‘FAB’ is a vast collection of wafer scale tools
• Electronic measurement represents any electrical signal used to develop metrics
• Seeing is believing: correlate electronic measurement with manufacturing targets
The ‘FAB’
Electronic measurement
Seeing is believing
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Semiconductor processing steps
Lithography
Chemical Mechanical Polish
(CMP)
Etch
See Y Nishi and R Doering, Handbook of semiconductor manufacturing technology (2000); H Geng, Semiconductor manufacturing handbook (2018)
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Transistors are the most ubiquitous man-made objects on earth
Intel 14nm FinFet
Fin Cut
Intel ships ~800 Quadrillion transistors every year (800,000,000,000,000,000)
By 2025 expect more transistors on Earth than human cells! Forbes.com
Gate Cut
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ENIAC (ca. 1947-1955) ENIAC (1995)
In ~50 years, ENIAC went from occupying an entire room to an area smaller than a US dime using Advanced Semiconductor Manufacturing
Images from Wikipedia
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Quantum Supremacy (2019)
Advanced Semiconductor Manufacturing can transform quantum computers…
Intel Horse Ridge 2 (2021)
All* rack electronics moved onto an SoC inside fridge
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Why semiconductor spin qubits?
22
mm
Intel Transmon Test Chip 49 qubits
SameScale3
6 m
m
Intel Tukwila CPU 20082 billion+ transistors
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Spin qubits are highly coherent
https://blog.qutech.nl/index.php/2018/04/20/making-quantum-computers-with-spin-qubits/
Metric Best reported value
T1 >1s
T2* 100us
T2Hahn 1ms
T2mem 30ms
F1Q 99.96%
F2Q 98%
Fmeas 98% at 1us
6Q device
Stephan Philips et al. APS March Meeting 2021
Takeda et al. Arxiv 2010.10316 2020
3Q GHZ state
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What is a spin qubit?
A qubit is a two-level system, so we need to generate these
two levels
B0
Apply an external magnetic field
𝐸 = 𝑔𝜇𝐵𝐵0
We now have well defined levels to utilize as a qubit!
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At low temperature, we can accumulate a 2DEG (two-dimensional electron gas) at a Si/SiOx interface
Silicon
Oxide
++ + ++ + +
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Silicon
Oxide
++ + + -- -
Dot 1 Dot 2
Using voltages to push electrons away, we can isolate electrons by forming quantum dots
Gate 1 Gate 2
2DEG reservoir2DEG reservoir
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Silicon
Oxide
++ + + -- -
Dot 1 Dot 2
We then apply the external magnetic field we introduced so we can have addressable two-level systems
Gate 1 Gate 2
B0
𝐸 = 𝑔𝜇𝐵𝐵0
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Silicon
Oxide
++ + + -- -
Dot 1
Gate 1 Gate 2
Adding or subtracting a single electron from the quantum dot costs a specific energy, the charging energy > kBT
Clean single quantum dot in charge sensing (Intel Si/SiGe device)
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Increase barrier gate voltage
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Vreservoir
VGate1 VGate1
Spin down Spin up
Vreservoir
EF EF
We have a mechanism for both initialization, and measurement,
ȁ ۧ0
TimeCh
arge
sen
sor
curr
ent
TimeCh
arge
sen
sor
curr
ent
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Spin up
Spin down
By applying a threshold to our ‘blip’ data, we can detect a spin up event
threshold
Before
After
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Phase = 0 Phase = 0 Phase = 90 Phase = 90
X90 Y90
Single qubit operations/gates are rotations around the Bloch sphere
X Y
Changing the phase by 90° we can rotate around the y-axis
Bit flip (x) Bit flip (y)
Z
Rotation about the z-axis is done in
software by applying a global phase to all
X and Y gates
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𝐸 = 𝑔𝜇𝐵𝐵0 = ℎ𝑓𝐿
First, we need to find the qubit by sweeping the frequency of a magnetic field applied perpendicular to the external magnetic field, B0
VreservoirVdot
EF
microwaves
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Each point corresponds to 2000 ‘blip’ measurementsInit Measure
Init Measure
fL
fL
Sitting at the Larmor frequency, we can rotate the qubit!
A lot of blips at our spin up state
Very few blips at our spin down state
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BAC
BDC
IACIAC
Strip line
CPW
CPW
ESR stripline
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28SiMOS electron spin qubit coherence times with ESR at ~100mK
T2*
THahn
TCPMG
Intel ESR stripline device performance (SiMOS)
Coherence times in-line with other academic devices.(T2* = 20us, T2Hahn = 290us, T2CPMG = 4ms)
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BDC
Spatial oscillation
MicromagnetMicromagnet
Plunger gate
Electrical control with micromagnets
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Intel micromagnet device performance (Si/SiGe)
MM magnet fab
Rabi
CPMG 40: T2 = 1.1ms
Coherence times in 5 different devices
Clifford fidelity of 98.8% - limited by nuclear spins: next steps to improve valley splitting and implement multi-qubit gates
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Porting the traditional flow to spin qubits
The ‘FAB’
Seeing is believing
NEW!
To implement the FAB cycle with spin qubits, one must introduce cryogenic
measurements
Electronic measurement
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The FAB: Intel spin qubit devices
Full 300mm Wafer Full Reticle
Individually diced 55/23/15/ 7 gate arrays
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Seeing is believing: process control can eliminate qubit personality
Academic Device Intel Fabrication
TU Delft
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Electrical measurements
Room T2 hours / wafer
1000s of devices
1.7 K 12 hours / device
T = 10 mK Weeks / device
Increasing measurement time
Cryogenic measurement represents a major bottleneck and impedes the FAB flow!
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Electrical measurements: divide and conquer
300 mm FAB
300mm wafer probing at room temperature
Measurements at <2 Kelvin
Dilution Fridge
1L. Petit et al., PRL 121, 076801 (2018)2L. Petit et al., Nature 580, 355-359 (2020)
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Introducing the cryoprober (T<2K)
• Combination of expertise in wafer scale probing and cryogenics
• Full 300mm wafer comes out of the FAB and into the prober
• Able to recover wafer for further processing or move to packaging
• No handling and wire bonding
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Exponentially speed up characterization <2KCross-Wafer Device CharacterizationCross-channel capacitance measurements
V1
V2
Gate V1 (mV)
Gate
V2 (
mV
)
Ch 1
Ch 2
Ch 1
Ch 2
From several weeks to 24 hours!
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The ‘FAB’
Seeing is believing
RT etest
LT etest
ULT etest
The spin qubit flow
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The ‘FAB’
Seeing is believing
RT etest
LT etest
ULT etest
Packaged computing unit
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Interconnects and packaging
Processor• 109 transistors• 103 pins
3D NAND Memory• 1012 bytes• 102 pins
55 Gate Linear Dot Array• 26 Qubits• 122 pins
Qubit chips currently have more connections than qubits
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Enabling quantum computing with advanced manufacturing
Intel 14nm Interconnect Stack• Fully integrated and
packaged processors utilize many metal layers
• Interconnects, process uniformity, and performance enables scaling
Spin qubits are made on the same processing line that produces these interconnect layers
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Scaling qubit control systems
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Horse Ridge 1
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Horse Ridge 1: microwave drive
• Controller capability• Drive
• Main features• 128 qubits control with frequency
multiplexing(4 channel, each with 32 qubits)
• Arbitrary pulse envelope(SRAM based)
• Wideband frequency output(2-20GHz)
[J. P. G. Van Dijk et al., IEEE JSSC, Nov. 2020]
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Horse Ridge 1: microwave drive
Randomized benchmarking
Two qubit gates and the Deutsch-Jozsa Algorithm
Fidelity = 99.71±0.03%
Fidelity = 99.69±0.02%
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Horse Ridge 2
• Controller capability• Drive
• Readout
• Gate pulsing
• Additional features• Programmable digital filter for drive
• Integrated micro-controller
• 22 DACs for flexible gate control
• SoC integration: >100M transistorsTechnical details were presented at 2021 IEEE
International Solid-State Circuit Conference (ISSCC)
4mm
Readout
RX
Re
ad
ou
t
RX
Dig
ita
l
Gate Pulsing
Readout
TX
Dri
ve
Dig
ita
l
Readout TX
Digital
Gate Pulsing Digital
Memory
µ-controller
Dig
ita
l I/O
s
Drive
4mm
4mm
Tested and verified at ~4K and currently integrating with spin qubit hardware
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Quantum @ Intel
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Summary
• The path towards useful quantum computers involves myriad skillsets
• Full breadth of advanced semiconductor manufacturing + quantum computing skills (both experimental and theoretical)
• Getting involved in quantum computing with spin qubits can come from any level in the development flow
• Learning quantum and qubit specialist information is possible on-the-job
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