spice example
DESCRIPTION
spice examplesTRANSCRIPT
Assignment 2
Submitted byGaurav Saini124070012
2.a). Program
DC analysis
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.include tsmc_spice_180nm.txt
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Mn 1 2 0 4 cmosn L=0.18u W=20u
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Vds 3 0 dc 50mVbs 4 0 dc 0Vgs 2 0 dc 1.8Vdummy 3 1 dc 0
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.dc Vgs 0 1.8 0.1*.control*run*plot i(Vdummy)*.endc.end
Threshold Voltage is around 0.4 Volt.
2.b). Program
DC analysis
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.include tsmc_spice_180nm.txt
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Mn 1 2 0 4 cmosn L=0.18u W=20u
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Vds 3 0 dc 1.8Vbs 4 0 dc 0Vgs 2 0 dc 1.8Vdummy 3 1 dc 0
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.dc Vgs 0 1.8 0.1*.control*run*plot i(Vdummy)*.endc.end
There is no change in the value of threshold voltage.
2.c.1). Program (comparison with 2.a)
DC analysis
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.include tsmc_spice_180nm.txt
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Mn 1 2 0 4 cmosn L=0.18u W=20u
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Vds 3 0 dc 50mVbs 4 0 dc -0.9Vgs 2 0 dc 1.8Vdummy 3 1 dc 0
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.dc Vgs 0 1.8 0.1*.control*run*plot i(Vdummy)*.endc.end
Because of negative Vbs (body to source voltage), threshold voltage of the transistor increases. Hence according to the drain current formula, drain current decreases.
2.c.2). Program (Comparison with 2.b)
DC analysis
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.include tsmc_spice_180nm.txt
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Mn 1 2 0 4 cmosn L=0.18u W=20u
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Vds 3 0 dc 1.8Vbs 4 0 dc -0.9Vgs 2 0 dc 1.8Vdummy 3 1 dc 0
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.dc Vgs 0 1.8 0.1*.control*run*plot i(Vdummy)*.endc.end
Same reason for decrease in current as was for 2.c.1.
2.d) Program
DC analysis
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.include tsmc_spice_180nm.txt
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Mn 1 2 0 4 cmosn L=0.18u W=20u
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Vds 3 0 dc 1.8Vbs 4 0 dc 0Vgs 2 0 dc 1.8Vdummy 3 1 dc 0
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.dc Vds 0 1.8 0.1*.control*run*plot i(Vdummy)*.endc.end
The positive slope when the device is in saturation is because of the finite resistance between the drain to source terminal. This is also called channel length modulation effect. Because of small channel length current in saturation region depends on the drain to source voltage.
3.a). Program
DC analysis
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.include tsmc_spice_180nm.txt
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Mn1 1 2 3 0 cmosn L=0.18u W=1.8uMn2 3 2 0 0 cmosn L=0.18u W=1.8u
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Vds 4 0 dc 1.8Vgs 2 0 dc 1.8Vdummy 4 1 dc 0
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.dc Vds 0 1.8 0.1*.control*run*plot i(Vdummy)*.endc.end
3.b). Program
DC analysis
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.include tsmc_spice_180nm.txt
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Mn 1 2 0 0 cmosn L=0.36u W=1.8u
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Vds 3 0 dc 1.8Vgs 2 0 dc 1.8Vdummy 3 1 dc 0
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.dc Vds 0 1.8 0.1*.control*run*plot i(Vdummy)*.endc.end
Channel length modulation effect is less when we use channel length of larger size. In 3.b, length of channel is twice as compared to the transistor channel length in 3.a. So, channel length modulation effect is more in 3.a. Because of this effect, current in saturation region depends on the drain to source voltage. Hence, Id v/s Vds curve will have some finite slope which is also clearly visible in the output waveform. In case of 3.b, Id v/s Vds slope in saturation region is less.