spectral pll built-in self-test for integrated cellular transmitters

7/31/2019 Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters

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Spectral PLL Built-In Self-Test forIntegrated Cellular Transmitters

Spektraler PLL-Selbsttest fr integrierteMobilfunktransmitter

Der technischen Fakulttder Universitt Erlangen-Nrnberg

zur Erlangung des akademischen Grades

DOKTOR-INGENIEUR

vorgelegt von

Christian Mnker

Erlangen - 2010


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ii

Als Dissertation genehmigt vonder Technischen Fakultt der

Universitt Erlangen-Nrnberg

Tag der Einreichung: 30. Oktober 2009

Tag der Promotion: 10. Mrz 2010

Dekan: Prof. Dr.-Ing. Reinhard GermanBerichterstatter: Prof. Dr.-Ing. Dr.-Ing. habil. Robert Weigel

Prof. Dr.-Ing. Heinrich Klar

Christian Mnker March 10, 2010


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Die Geburt unseres Sohns Robin, unsere Heirat, zwei Jobwechsel,zwei Umzge, ein Hauskauf ... ohne die Hilfe meiner geliebten FrauSylvia Englert und unserer Eltern htte ich es nie geschafft, meineArbeit in dieser turbulenten Zeit abzuschlieen.

Dafr danke ich Euch von Herzen.

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters


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Acknowledgments

First of all, Id like to thank my two supervisors Prof. Dr. Dr. Robert Weigel andProf. Dr. Heinrich Klar for their kind support and motivation over all the yearsin spite of geographical distance.

My interest in PLL topics was triggered by "old PLL rabbit" Edmund Gtz. Healso played a vital role in our weekly discussions with Markus Scholz, BurkhardNeurauter and Gnter Mrzinger at Inneon Technologies revolving aroundPLLs and self-calibration strategies. These discussions sparked-off greatchips, several patents and, in the end, this thesis. Markus Scholz also designedthe excellent multi-modulus divider block that found its way from the PLLinto the FD and shared countless mugs of coffee with me. Manufacturing andevaluation of the test-chips was made possible by the kind support of InneonTechnologies.

Frank Demmerle was especially helpful for long discussions on test and self-testissues, motivation and reading the rst horrible versions. Guido Retz, LudgerSchneider-Strmann and Stefanie Marek ( www.schreibkonzepte.de ) gaveme valuable ideas for the nal structure of this work.

Julien Layoles contributions on PLL modeling using SystemC gave me impor-tant insights into modeling issues and spectral estimation.

Parts of this work were funded by the MEDEA+ project A107 "4G-Radio" andthe BMBF project 01M3071 "DETAILS".

This work was typeset using the MiKTEX - implementation of L ATEX with theTeXnicCenter user interface and the fantastic GhostView / Ghostscript package.Figures were created with XFig / WinFig and references were administrated withthe combination of B IB TEX and JabRef . Data was kept secure and up-to-datebetween many different computers and harddisks by Unison .

A big "THANK YOU" to all of you!!

http://www.schreibkonzepte.de/http://miktex.org/http://miktex.org/http://miktex.org/http://www.texniccenter.org/http://jabref.sourceforge.net/http://jabref.sourceforge.net/http://www.cis.upenn.edu/~bcpierce/unison/index.htmlhttp://www.cis.upenn.edu/~bcpierce/unison/index.htmlhttp://jabref.sourceforge.net/http://www.texniccenter.org/http://miktex.org/http://www.schreibkonzepte.de/


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KURZFASSUNG v

Kurzfassung

Bis vor wenigen Jahren war die Komplexitt von HF-ICs so gering, dass test-untersttzende Designmanahmen (Design-for-Test, DfT) oder gar ein Selbst-

test (Built-In Self-Test, BIST) unwirtschaftlich gewesen wren. Da man HF-Parameter zudem nur schwer mit ausreichender Genauigkeit auf dem Chipmessen konnte, wurde der Produktionstest auf speziellen automatischen HF-Testsystemen (Automated Test Equipment, ATE) durchgefhrt. Der allgemeineTrend der letzten Jahre hin zu drahtlosen Anwendungen schaffte einen Mas-senmarkt fr komplexe HF-Systems-On-Chip (SOC) mit rapide sinkenden Pro-duktmargen. Wie zuvor bei digitalen ICs wurde der Produktionstest auch frHF-SOCs zum Flaschenhals; DfT und BIST wurden zur konomischen Notwen-digkeit.

Sigma-Delta-modulierte Fractional- N Phase-Locked Loops ( PLLs) gehrenzu den Schlsselkomponenten in heutigen HF-SOCs; sie erzeugen und modu-lieren rauscharme HF-Trgersignale mit kurzer Einschwingzeit. Die enge Ver-zahnung von analogen und digitalen Blcken in PLLs und deren vollstndigeKapselung im SOC erschwert jedoch deren Produktionstest und damit den Testdes gesamten HF-SOCs.

Da erprobte digitale DfT-Methoden ungeeignet sind, um die vielfltigen HF-Spezikationen abzudecken, wird ein neuer Ansatz fr den autonomen, spezi-kationsgetriebenen Test von PLLs in SOCs bentigt. HF-Gerte mssen stren-ge Standards erfllen, die ganz berwiegend in der Frequenzebene speziziertsind, wie z.B. die Sendebandbreite. In dieser Arbeit wurde daher ein spektralerPLL BIST (SP-BIST) entwickelt, um spektrale Eigenschaften von integriertenPLLs auf dem Chip ohne externe Messgerte zu ermitteln und digital auszu-geben. Der SP-BIST beinhaltet einen Stimulusgenerator zur Modulation der PLLund einen Block, der die HF-Antwort der PLL spektral bewertet.

Es musste zunchst eine Simulationsmethodik entwickelt werden, um das Zu-sammenspiel der RF- und Digitalblcke von PLL und SP-BIST im Frequenz-und Zeitbereich vorherzusagen. Unter Verwendung eines Standard-VHDL-Simulators konnten damit u.a. die PLL-Schleifenbandbreite und das Phasen-rauschen bei 4 GHz mit einem Noise Floor von -200 dBc/Hz simuliert werden.

Der digitale Stimulusgenerator erzeugt Zweitonsignale mit einer Frequenz von16 . . . 180 kHz und einem Spurious-Free Dynamic Range (SFDR) von 60 dB.Die PLL wird digital ber das Fractional-Frequenzwort moduliert. Das Zwei-tonsignal steht sowohl als Sigma-Delta-modulierter Bitstrom zur Verfgung als

auch in paralleler Form und ist damit ein vielseitiges Testsignal auch fr andere



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vi KURZFASSUNG

analoge und mixed-signal-Blcke auf dem Chip.

Das HF-Signal der PLL wird mit einem digitalen Sigma-Delta-Frequenz-Dis-kriminator ( FD) gleichzeitig demoduliert und digitalisiert. Der demodulier-te Bitstrom wird in einem Multiraten-Bandpasslter vierter Ordnung mit einer

Bandbreite von 0,8 kHz und einem digitalen Hllkurvendetektor spektral bewer-tet. Dabei wird ein SFDR von 45 dB erzielt, der Rauschboden liegt bei L =

80 dBc/Hz. Die Mittenfrequenz des Bandpasses wird mit einem einzigen Para-meter in Schritten von 300 Hz im Bereich von 10 . . . 200 kHz abgestimmt. Derniedrige Ausschnittsverlust des Filters verursacht einen reproduzierbaren Ampli-tudenfehler von weniger als 0.5 dB fr Einzeltne. Dieser und andere systema-tische Fehler knnen leicht mit einer Kalibrationsmessung entfernt werden. Dieresultierende Standardabweichung des PLL-Frequenzgangs, gemessen mit demOn-Chip Stimulusgenerator, ist 0.05 dB.

Die Messdauer betrgt 3 ms pro Frequenzpunkt, Messwerte werden ber einminimales Testinterface als statisches Wort ausgegeben und ermglichen damitauch einen RF-Test der PLL auf Wafer Level.

Mit der Einschrnkung des relativ geringen SFDR knnen auch das In-Band Pha-senrauschen und die Modulationsmaske bewertet werden. Diese On-Chip Extrak-tion der spektralen Parameter stellt eine efziente Kompression der analogen Da-ten dar und kann direkt mit den Spezikationen im Frequenzbereich verglichenwerden. Durch Messung der PLL-Bandbreite und des Spektrums knnen funk-

tionale und parametrische Ausflle ermittelt werden.

Stimulusgenerator und Bandpasslter basieren auf verlustlosen Resonatoren, dieguten Rauschabstand und Stabilitt auch bei kurzen Wortbreiten garantieren. Re-sonanzfrequenz bzw. Bandbreite werden mit einem Parameter mit annhernd li-nearer Abhngigkeit eingestellt. Durch diese einfache Beziehung eignet sich dasVerfahren auch fr einen Selbstabgleich.

Der SP-BIST wurde auf einem hochintegrierten GSM / UMTS-Transceiver-Chipmit zwei 4 GHz PLLs in einer 130 nm CMOS-Technologie integriert, ohnedie Signalqualitt zu beeintrchtigen. Die volldigitale Implementierung ist ro-bust gegen Technologieschwankungen und bentigt eine zustzliche Flche vonweniger als 0,06 mm 2 , die durch die Reduktion der Testzeit um 150 ms und dieverbesserte Testabdeckung mehr als ausgeglichen wird. Der Transceiver-Chipwurde getestet und zeigt die erwartete SP-BIST Funktionalitt.



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ABSTRACT vii

Abstract

Until a few years ago, RF ICs were low complexity devices that required noDesign-for-Test (DfT) or Built-In Self-Test (BIST) features. Additional testblocks would have been uneconomical for these small devices and RF parame-ters could not be measured with sufcient precision on-chip. Instead, productiontest was performed on automated test equipment. Since then, a general trendtowards wireless applications has turned RF ICs into high volume System-On-Chip (SOC) commodity products with dwindling gross margins. As before withdigital ICs, production test has become a bottle-neck for cost sensitive consumermarkets, turning DfT and BIST into an economic necessity for RF SOCs as well.

Sigma-delta modulated fractional- N Phase-Locked Loops ( PLLs) are keycomponents of todays wireless transceivers for the generation and modulationof low-noise RF carrier signals with fast settling times. The tight interaction of analog and digital blocks makes PLLs - and as a consequence the whole RFSOC - hard to test, especially as the analog ports of PLLs embedded in SOCs areinaccessible from the outside.

As digital DfT methods cannot address the rich analog and RF parameter space,a new approach for the autonomous, specication oriented test of PLLs in RFSOCs is needed. RF applications have to fulll tight spectral requirements, spec-ied by parameters like frequency response or the level of spurious sidebands. In

this work, a Spectral PLL BIST (SP-BIST) for on-chip analysis of the spectralproperties of PLLs is developed that requires no external RF test equipmentand does not disturb critical RF paths. The SP-BIST contains a stimulus genera-tor for PLL modulation and a block for spectral response analysis of the PLL RFsignal.

A simulation methodology had to be developed to predict transient and spectralbehavior and the interaction between RF and digital blocks of PLL and SP-BIST.Utilizing a standard VHDL simulator, the PLL bandwidth and phase noise could

be simulated down to a noise oor of -200 dBc/Hz at 4 GHz.A digital stimulus generator provides a two-tone sine signal in the range 16. . . 180 kHz with a spurious-free dynamic range (SFDR) of 60 dB for efcienttesting of PLL spectral properties. The PLL is modulated digitally via the frac-tional frequency word. The two-tone signal is available as an oversampled Sigma-Delta bitstream as well as in parallel form, making it a versatile test signal forother analog and mixed-signal blocks on-chip as well.

The PLL RF signal is demodulated and digitized using a rst order Sigma-Delta

frequency discriminator ( FD). Spectral estimation of the demodulated bit-



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viii ABSTRACT

stream is performed using a 4th order multi-rate band-pass lter with a resolu-tion bandwidth of 0.8 kHz, achieving an SFDR of 45 dB and a noise oor of L = 80 dBc/Hz. The band-pass center frequency is tuned with a single param-eter in steps of 300 Hz in the range 10 . . . 200 kHz. The low scalloping loss of thelter gives a reproducible amplitude error below 0.5 dB for single tones. This and

other systematic errors can be eliminated easily with a calibration run, resultingin a standard deviation of 0.05 dB for the PLL frequency response measured inconjunction with the on-chip multi-tone generator.

Using a digital envelope detector, the amplitude of the band-pass output is readout as a static word via the DUT serial data bus. This minimal test interfacealso enables an RF PLL test on wafer level. Total measurement time is 3 ms perfrequency point.

Limited by the relatively low SFDR, in-band phase noise and the modulationmask can be measured as well. This on-chip calculation of spectral informationis an efcient way for test data compaction and allows direct comparison to spec-ications in the frequency domain. Functional and many parametric faults canbe detected by measuring the PLL bandwidth and spectrum.

Both stimulus generator and band-pass lter utilize compact lossless resonatorswhich give good performance in spite of short coefcient and word lengths. Os-cillation and band-pass center frequencies are tuned with a single parameter withnearly linear dependency. This simple relationship enables self-calibration as

well. Slow and computation intensive tasks like linearization, smoothing andlogarithmic scaling are performed off-chip to save chip area.

The SP-BIST has been implemented on an integrated GSM / UMTS transceiverchip with two 4 GHz PLLs in a 130 nm CMOS technology. The fully digitalimplementation is robust against technology deviations, does not degrade the de-vice performance and requires an additional area of less than 0.06 mm 2 whichis more than compensated by the improved test coverage and a reduction of testtime of 150 ms. The transceiver chip has been tested, proving the SP-BIST capa-

bilities and functionalities.



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Contents

Kurzfassung v

Abstract vii

Table of Contents xii

List of Acronyms and Symbols xiii

1. Introduction 11.1. Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2. State-of-the-Art of DfT and BIST . . . . . . . . . . . . . . . . 4

1.2.1. Automated Test Equipment Based Test . . . . . . . . . 61.2.2. Structural Test . . . . . . . . . . . . . . . . . . . . . . 61.2.3. Functional Test . . . . . . . . . . . . . . . . . . . . . . 101.2.4. Alternate or Translation Test . . . . . . . . . . . . . . . 11

1.2.5. Loop-Back Test . . . . . . . . . . . . . . . . . . . . . . 111.2.6. Built-In Self-Test . . . . . . . . . . . . . . . . . . . . . 131.2.7. PLL BIST . . . . . . . . . . . . . . . . . . . . . . . . . 16

1.3. Goals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2. Fundamentals 212.1. Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.1.1. Symbols . . . . . . . . . . . . . . . . . . . . . . . . . 212.1.2. Denitions . . . . . . . . . . . . . . . . . . . . . . . . 22

2.2. Angle Modulation . . . . . . . . . . . . . . . . . . . . . . . . . 232.2.1. Angle Modulation in the Time Domain . . . . . . . . . 232.2.2. Sinusoidal Angle Modulation . . . . . . . . . . . . . . 252.2.3. Small-Angle Approximation . . . . . . . . . . . . . . . 272.2.4. Bandwidth of Angle Modulation . . . . . . . . . . . . . 27

2.3. Phase Noise Metrology . . . . . . . . . . . . . . . . . . . . . . 282.3.1. Double-Sideband Representation . . . . . . . . . . . . . 312.3.2. Single-Sideband Representation . . . . . . . . . . . . . 322.3.3. Frequency Modulation and Division . . . . . . . . . . . 34

2.4. Spectral Estimation of Simulation Data . . . . . . . . . . . . . 36

ix


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2.5. Sampling and Quantization . . . . . . . . . . . . . . . . . . . . 392.5.1. Sampling . . . . . . . . . . . . . . . . . . . . . . . . . 402.5.2. Quantization . . . . . . . . . . . . . . . . . . . . . . . 402.5.3. Oversampling . . . . . . . . . . . . . . . . . . . . . . . 412.5.4. Subsampling and Downsampling . . . . . . . . . . . . 42

2.6. Sigma-Delta Modulation . . . . . . . . . . . . . . . . . . . . . 432.6.1. Single Bit Quantizer . . . . . . . . . . . . . . . . . . . 462.6.2. Quantization Noise in M . . . . . . . . . . . . . . . 462.6.3. Spurious Tones of First Order M . . . . . . . . . . . 492.6.4. Higher Order M . . . . . . . . . . . . . . . . . . . . 492.6.5. Terminology . . . . . . . . . . . . . . . . . . . . . . . 52

2.7. Digital Resonators . . . . . . . . . . . . . . . . . . . . . . . . 522.7.1. Basic Properties . . . . . . . . . . . . . . . . . . . . . 522.7.2. Undamped Resonators . . . . . . . . . . . . . . . . . . 552.7.3. Resonance Gain and Peak Gain . . . . . . . . . . . . . 552.7.4. Constant Peak-Gain Digital Resonator . . . . . . . . . . 562.7.5. Bandwidth and Settling Time of High-Q Resonators . . 582.7.6. Resonator Implementations . . . . . . . . . . . . . . . 61

2.8. Fixed-Point Number Format . . . . . . . . . . . . . . . . . . . 632.9. Digital Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

2.9.1. Direct Form and Related Filters . . . . . . . . . . . . . 642.9.2. Passivity and Reference Network Filters . . . . . . . . . 67

2.9.3. Resonator Based Filters . . . . . . . . . . . . . . . . . 692.9.4. Comparison of Filter Structures . . . . . . . . . . . . . 72

3. Introduction to the Circuit-Under-Test 733.1. Basic PLL Theory . . . . . . . . . . . . . . . . . . . . . . . . . 753.2. Circuit-Under-Test . . . . . . . . . . . . . . . . . . . . . . . . 783.3. PLL Specications and Test Methods . . . . . . . . . . . . . . 82

4. Concept and Simulation Methodology for Spectral BIST 87

4.1. RF PLL Test Concept . . . . . . . . . . . . . . . . . . . . . . . 874.2. Measurement Principle . . . . . . . . . . . . . . . . . . . . . . 884.2.1. PLL Bandwidth . . . . . . . . . . . . . . . . . . . . . . 884.2.2. Spectral Analysis with FM Discriminator . . . . . . . . 89

4.3. From MADBIST to SP-BIST . . . . . . . . . . . . . . . . . . . 904.4. Partitioning of Test Hardware . . . . . . . . . . . . . . . . . . . 924.5. Simulation Methodology . . . . . . . . . . . . . . . . . . . . . 93

4.5.1. Special Requirements for PLLs . . . . . . . . . . . . . 944.5.2. Discrete Time Modeling of Analog Blocks . . . . . . . 95

4.5.3. Limitations of Event-Driven Analog Simulation . . . . . 98



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List of Acronyms and SymbolsAcronymsM Sigma-Delta Modulation

PLL Sigma-Delta PLL

CP Charge Pump

ABIST Analog Built-In Self-Test

ACF Auto-Correlation Function

ADC Analog-to-Digital Converter

ATE Automated Test Equipment

ATPG Automatic Test Pattern Generation

AWGN Added White Gaussian Noise

BE Backward Euler

BER Bit-Error Rate

BiCMOS Bipolar CMOS

BILBO Built-In Logic Block Observer

BISC Built-In Self-Calibration

BIST Built-In Self-Test

BOST Built-Off or Built-Out Self-Test

CDF Cumulative Distribution Function

CDR Clock-and-Data Recovery

CIC Cascaded Integrator-Comb (Filter)

CT Continuous-Time

CUT Circuit Under Test

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xiv LIST OF ACRONYMS AND SYMBOLS

DAC Digital-to-Analog Converter

DDS Direct Digital Synthesis

DF Direct Form

DFT Discrete Fourier TransformDfT Design-for-Test

DOT Defect Oriented Test

DSB Double Sideband

DSM Deep Submicron

DT Discrete-Time

DUT Device Under TestEVM Error Vector Magnitude

FE Forward Euler

FFT Fast Fourier Transform

FM Frequency Modulation

FPGA Field-Programmable Gate Array

FSR Full Signal Range

GSM Global System for Mobile Communications, originally Groupe Sp-cial Mobile

HBIST Hybrid Built-In Self-Test

HDL Hardware Description Language

IC Integrated Circuit

IF Intermediate FrequencyLBIST Logic Built-In Self-Test

LDI Lossless Digital Integrator

LFSR Linear-Feedback Shift-Register

LNA Low-Noise Amplier

LO Local Oscillator

LTI Linear Time-Invariant



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List of Acronyms and Symbols xv

MADBIST Mixed Analog-Digital Built-In Self-Test

MASH MultistAge noise SHaping

MBIST Memory Built-In Self-Test

MISR Multiple-Input Signature RegisterNTF Noise Transfer Function

OBIST Oscillation Built-In Self-Test

ORA Output Response Analysis

OSR Oversampling Ratio

OTA Operational Transconductance Amplier

PA Power Amplier

PCB Printed Circuit Board

PD Phase Detector

PDF Probability Density Function

PLL Phase-Locked Loop

PM Phase Modulation

PRBS Pseudo-Random Binary Sequence

PSD Power Spectral Density

RBW Resolution Bandwidth

RF Radio Frequency

RMS Root Mean Square

ROM Read-Only Memory

RWV Real World Value of binary number representation

RX Receiver

SC Switched-Capacitor

SDM Sigma-Delta Modulation

SFDR Spurious-Free Dynamic Range

SNR Signal-to-Noise Ratio



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xvi LIST OF ACRONYMS AND SYMBOLS

SOC System-On-Chip

SOS Second-Order Section

SP-BIST Spectral PLL BIST

SPICE Simulation Program with Integrated Circuit EmphasisSPOT Specication Oriented Test

SQNR Signal-to-Quantization-Noise Ratio

SSB Single Sideband

STF Signal Transfer Function

TLA Three-Letter Acronym

TPG Test Pattern Generation

TX Transmitter

UMTS Universal Mobile Telecommunications System

VCO Voltage Controlled Oscillator

VDSM Very Deep Submicron

VHDL VHSIC (Very High Speed Integrated Circuit) Hardware Description

LanguageWDF Wave Digital Filter

WL Word Length

WLAN Wireless Local Area Network

Symbols f Frequency modulation index

Q Quantization step size

Angular frequency

Normalized angular frequency

+ Upper -3 dB frequency of band-pass

Lower -3 dB frequency of band-pass



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List of Acronyms and Symbols xvii

0 Nominal or carrier angular frequency

c Center frequency

r Resonance frequency

sT Loop gain transit frequency Phase deviation from nominal phase

i(t ) Instantaneous phase

2e Variance of quantization error

p Pole angle

A Amplitude

Am Modulation amplitude

B Bandwidth

B3 -3 dB bandwidth B60 -60 dB bandwidth Bm Modulation bandwidth

Bn Noise bandwidth

Brel Relative bandwidth

D Frequencies in the discrete time domain

en Quantization noise voltage

f Frequency

F Normalized frequency

f 0 Nominal or carrier frequency

f Frequency error or deviation

f Peak frequency deviation f c Corner or center frequency f i(t ) Instantaneous frequency

f l Lower -3 dB frequency of band-pass

f m Modulation frequency or offset frequency from the carrier



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List of Acronyms and Symbols xix

r p Pole radius

RBW Resolution Bandwidth

s Complex frequency

S Normalized complex frequency; signal powerSF Shape factor or selectivity of a band-pass lter

s(t ) Signal

sFM (t ) Angle modulated signal

S ( f m) Phase instability

S y( f m) Frequency instability

t TimeT Period

T (s) Closed-loop transfer function

T Period error or deviation

T q Quantization time step

T sym Symbol period, reciprocal of symbol rate

W L Word length in bits

y(t ) Relative frequency deviation

y Peak normalized frequency deviation



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xx LIST OF ACRONYMS AND SYMBOLS



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1.2. State-of-the-Art of DfT and BIST 7

A fault is an abstract representation of a defect that can lead to the failure of the device.

Every defect should be mapped to a fault, but not every defect or fault results inthe failure of the DUT. This is especially true for analog or RF circuits.

Defect: imperfection of a component or structure that violates the technologyspecications, e.g. a bridge between a pad and ground or an excessivedeviation of a sheet resistance value.

Failure: behavior of a DUT that does not conform to customer specications, beit functional or parametric, e.g. a microprocessor calculating 2 + 2 = 5 ora lter with a corner frequency outside the specication band.

Fault: a defect mapped to an abstract, computer-readable representation of thechip which could be a gate level or SPICE netlist of lumped components.

Examples for faults are a node stuck at zero level or a resistor with twicethe target resistance.

Box 1.1: Important Denitions

For defect-oriented testing, a set of input patterns, also called test vectors , is de-termined that stimulates a high number of the basic devices, the correspondingideal responses are simulated and recorded. During production test the prede-termined stimuli are applied to the DUT and the responses are compared to the

predetermined, ideal ones. This only works well when a high percentage of inter-nal nodes is controllable and observable . Finding suitable stimuli is a task wellsuited for computers as structural test is a brute force approach without know-ledge about the function of the circuit. Besides topological information (a netlistor layout), fault models are needed for fault diagnosis techniques. A computercannot understand the concept of "defects", instead, hypotheses about how thecircuit will fail - fault models - have to be formulated. Together with an initialset of test vectors, a fault simulation is started where various faults are insertedinto the circuit. The simulator then checks whether the current set of test vectors

can detect the difference between faulty and correct circuit behavior and tries tond new test vectors if the fault coverage is unsatisfactory.

Digital Structural Test

Due to their complexity, digital ICs were the rst to suffer from the loss of ob-servability and controllability of internal nodes. Scan techniques were introducedto improve fault detection during structural test: The basic idea is to implement

a scan mode where all the ip-ops in a design are hooked up as a long shift



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Test MUX

DDFF D out D in

1

0

S in

S out S en

CLK

Logic Overhead

Figure 1.3.: Scan ip-op with test-logic overhead (dashed box)

can be detected by static tests. Fault modeling is complex for this class of de-fects as failures are parametric and so is testing, touching problems of analog

test. Additional test methods like at-speed or quiescent current (IDDQ) testinghave to be used to nd these defects [ SCP + 99, SH04 ].

However, the high leakage currents in VDSM technologies reduce the sensitivityof IDDQ tests. At-speed tests are difcult to implement due to lacking automatedtool support. For these reasons, functional tests are used increasingly to improvetest coverage or for speed binning.

Analog Structural Test

DOT has worked very well for digital circuits for more than 25 years now, andthe idea of using a similar approach for analog ICs was and is very appealing.However, the rich parameter space of analog circuit design does not allow a re-duction of complexity similar to digital circuits. While simple Boolean logic andregister-transfer level abstractions are working ne for digital systems, a state-of-the-art BSIM4 analog transistor model has more than 100 principal parameters(and approx. 300 in total). Hierarchical partitioning of analog circuits is difcultand error prone as the selection of which parameters and constraints have to bepassed between abstraction layers is a manual task.

Even the concept of "fault coverage" which is a well accepted test quality metricfor digital test is difcult to dene for analog test. Only simple open/short de-fects lead to signicant performance degradations of the analog DUT that can bedetected easily; these faults are classied as catastrophic or hard faults. Analogand especially RF circuits usually try to push the limits of the process technology.Consequently, parametric failures , i.e. a DUT performance slightly outside the

specications, are far more important. Tracking these failures back to individ-



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10 1. Introduction

ual defects is daunting, dening limits for the corresponding parametric or soft faults even more so. DOT approaches are based upon detecting catastrophic andparametric faults due to defects of individual components, however, not everyparametric fault or combination of parametric faults causes a parametric failureof the device. A strict application of DOT principles may therefore lead to a loss

of yield for analog devices.

[Mil98 ] gives an overview over the challenges involved with dening and ndingfaults for analog blocks. The effort of simulating catastrophic and parametricfaults is high, requiring a large number of analog Monte-Carlo simulations todetect these faults. Hence, analog fault simulation so far is restricted to smallcircuit blocks like OTAs and low-order lters [GPG01 ], it has yet to nd its wayinto industry. An automatic RF structural test seems even more unlikely for thenear future, given the difculties of accurate "normal" RF simulations, except for

low-complexity devices like LNAs [KDCM04 ]. A similar procedure for complexmixed-signal building blocks like PLLs or ADCs has not been published yet anddoes not seem feasible in the near future. A structural PLL test presented in[MCAS05 ] e.g. only covers some charge-pump related catastrophic defects.

In contrast to digital ICs, there is also no solution in sight for monitoring and con-trolling internal analog nodes without signal deterioration. Analog scan chainswere an attempt to adapt the hugely successful digital scan design techniques:[Wey90 , SW98 ] suggest a chain of sample and hold ampliers as an analog shift

register for this purpose. Limited scan chain length due to accumulation of er-rors, the large area overhead (one opamp and a sampling capacitor per stage) andthe restriction to near-static signals have so far limited the practical use of thistechnique.

Analog test buses and multiplexers for controlling and monitoring analog nodes[Wur93 ] are used to some extent in products, though mainly for quasi-static sig-nals like bias currents. As there is no tool for scan insertion like in the digitaldomain, a manual selection of the analog nodes of interest is required as well ascareful analog design to avoid performance deterioration due to the loading of internal nodes.

1.2.3. Functional Test

On a rst glance, functional testing seems to be more economical than structuraltesting because only modes that are important for the customer need to be tested.However, given the multitude of operation modes and input values of SOCs, the

duration for an exhaustive functional test would be forbiddingly long. Addition-



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12 1. Introduction

ever, several inherent limitations render a loop-back test impractical for manyapplications:

Checking two unveried block against each other may mask errors. Priortesting of the higher performance block using ATE or additional BIST com-ponents [ Li04 ] may be a workaround to this problem but reduces the ef-ciency of the loop-back approach.

"Performance" is a multi-faceted parameter, comprising dynamic range,sampling speed, differential and integral nonlinearity (DNL / INL), inter-modulation distortions etc. One of the converters has to be superior to theother in all aspects which is unlikely for high-performance components.

Inserting analog multiplexers into the signal path to close the loop bringsthe risk of performance deterioration.

Loop-back is an integral system test that provides no information aboutthe cause of the failure which is needed for yield improvement in volumeproduction.

The technique of re-using the on-chip receiver (RX) path to mix down and de-modulate the transmitter (TX) signal in RF transceivers is dubbed RF loop back test . Some additional problems make a loop back test at RF even harder to im-plement:

On- and off-chip crosstalk due to RX and TX running at the same fre-quency degrades accuracy.

In time-division multiple access (TDMA) systems like GSM or Bluetooth,RX and TX often cannot operate simultaneously because there is e.g. onlyone local oscillator shared between RX and TX path or because powerconsumption would be too high.

RX and TX frequency range in frequency division duplex (FDD) systems(all major cellular and short-range communication standards) do not over-lap. Hence, one of the two blocks has to run outside the standard operationrange during test, requiring the design of an extended frequency range. Ad-ditionally, the test results do not reect the real operation case.

Due to these reasons, loop-back test cannot be applied for most RF systems.



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1.2.6. Built-In Self-Test

In order to improve test efciency, built-off self-test 1 (BOST) and built-in self-test (BIST) have been developed as DfT techniques for both structural and func-tional test. The target of BIST / BOST is to minimize ATE requirements byreducing volume and bandwidth of stimulus and circuit response signals. BISTachieves this task by using on-chip test-pattern generation (TPG) and output re-sponse analysis (ORA). The ORA usually generates a compact representation of the input data, the so-called signature . Pass / fail information is determined bycomparing the signature to the value for the fault-free case.

BOST performs the same tasks not within the chip but on the load board. Thisis achieved e.g. with an RF mixer to reduce the signal frequency or with a eld-programmable gate array (FPGA) to compress digital data. In many cases, BISTcircuitry can be replaced by BOST and vice versa, trading chip area against inter-face pins and board area. For this reason, BOST is not treated separately in thiswork.

Another application of BIST is not regarded here: Fail-safe systems employ BISTfor a continuous on-chip test during operation, switching over to a redundant unitor powering down the system in case of an error.

The main drawback of BIST is that it requires more chip area and more effort

during the design phase than ATE based test. Circuit partitioning and test patterngeneration are mainly performed using ad hoc methods without mathematical un-derpinning and therefore little potential for automation. Design effort and chiparea for the additional BIST blocks have to pay-off in terms of reduced test-timeand tester resources and / or quality improvement. This is best achieved usingdigital, synthesizable test blocks which are compact and reusable, minimizingboth area and design effort. Like other DfT measures, BIST is usually imple-mented on a block level to speed-up both test development and the test itself,with highest priority on those blocks that are hard to test otherwise. Observabil-

ity and controllability for the individual building blocks is provided via a digitaltest bus to avoid the routing of sensitive analog signals across the chip.

Logic BIST

In 1979, the rst logic BIST (LBIST) was presented [KMZ79 ] using a linear-feedback shift-register (LFSR) to generate pseudo-random binary sequences

1Also called built-out self-test



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16 1. Introduction

DAC and a low-pass lter from an oversampled digital bit-stream. This leavesthe auxiliary DAC and the lter as the only unveried analog circuit block andallows operation in an uncalibrated environment. In the second step, the DAC ischaracterized using the now veried ADC.

1.2.7. PLL BIST

Due to the complexity of conventional PLL verication, the potential reward of implementing DfT measures is high and many attempts have been made to targetfunctional and performance verication. Some basic self-test features are im-plemented in most PLLs to detect catastrophic failures [ BLBR04 , AS07 ]. Pulsecounting with an on-chip frequency counter is such a simple but effective digitalBIST method for verifying basic PLL functionality and parameters like center fre-quency, frequency range and VCO loop gain [ KSR00 , MSMG02 , MS02b , MS03 ,YL07 ].

The complex interactions within a PLL make it difcult to establish correlationsbetween complex specication parameters (e.g. RMS jitter, closed-loop band-width) and simple PLL quantities (e.g. phase detector pulse width, loop ltervoltage) [ YL07 ]. In practice, it is also very difcult to measure e.g. the loop ltervoltage with sufcient accuracy without deteriorating PLL performance. Hence,most successful approaches for detecting parametric failures measure the speci-ed parameters directly.

PLL Jitter BIST

In the last years, several BIST approaches have been presented for PLLs usedin clock synthesis for microprocessors or in clock-and-data recovery (CDR) forhigh-speed wire-bound data transmission. These applications are specied in thetime-domain; signal analysis focuses on time-related parameters like timing jitter.The interest in on-chip measurement of PLL timing jitter has increased tremen-dously with the advent of SOC solutions for high-speed serial transceivers inchip-to-chip [CMJ + 03] or Gigabit Ethernet [ CKTM02 ] communication. Com-petitive pressure for communication products and the high costs for fast ATEhelped to create the nancial momentum for developing DfT / BIST solutions.

Several methods have been published that determine the cycle-to-cycle jitter froman estimation of the autocorrelation function (ACF) around t = T 0 . Collectingmultiple cycle-to-cycle jitter measurements yields the probability density func-

tion (PDF) and the cumulative distribution function (CDF) of the jitter. Subse-



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18 1. Introduction

vernier circuits are large and complex, requiring precision analog components.However, for digital PLLs utilizing vernier based time interval measurements(time-to digital converter, TDC) [ MS07 ], jitter information can be gathered withlittle overhead [ EBSB07 ].

For testing the bit-error rate (BER), receiver and transmitter are connected inloop-back mode, sent and received bits of a pseudo-random binary sequence(PRBS) are compared for errors. Loop-back test is feasible, because receiverand transmitter of wire-bound systems operate at the same frequency and withsimilar signal levels. However, verication of very low BERs requires exces-sive measurement times; [ SR07 ] proposed measurement of the PLL RMS jitterinstead, using subsampling with a slightly offset frequency.

Frequency Domain PLL BIST

In contrast to time-domain specied PLL Jitter BIST, there are bare to none ap-proaches for a PLL BIST in the frequency domain: PLLs in wireless systemsare specied in the frequency domain (frequency response, phase noise, spurioussidebands) and should be tested accordingly. Calculating frequency domain spec-ications from time-domain measurements is possible but very inefcient withlong measurement times due to the required large number of jitter measurements.

Several publications try to assess the PLL performance at the output of the phase-frequency detector (PFD) because this is a digital, comparatively low-frequencysignal. For high-performance PLLs in wireless systems, this is a dangerous ap-proach: The relative phase error of the VCO signal appears divided by N , makingit more difcult to quantify the signal error at this node in practical implementa-tions. The output of the PFD is also a very sensitive node in the PLL; disturbancesintroduced at this node appear multiplied by N at the VCO output. Due to thesereasons, most publications, e.g. [ ABM + 09] only present simulation results.

Figure 1.6.: Self-calibrated on-chip phase noise measurement circuit [KBK07 ]



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1.3. Goals 19

In contrast, [VGKB + 07] presents a phase noise BIST based on a tunable delay-line and mixer achieving a measured sensitivity of -75 dBc at 100 kHz offset atthe cost of an additional 0.5 mm 2 of analog building blocks in a 0 .25 m tech-nology. Using the same area in the same technology node, [ KBK07 ] achieves asingle-tone sensitivity of -75 db using a self-calibrated delay-line (Fig. 1.6 ).

1.3. Goals

Todays RF SOCs require multiple test insertions, i.e. production test on spe-cialized digital, RF and sometimes also mixed-signal automated test equipment.Power and speed of digital testers have to increase with the growing digital com-plexity of RF SOCs providing ever more features and media support. This means,in the long run, test costs can only be minimized by performing all productiontests on a single digital tester, eliminating RF and mixed-signal ATE.

However, efcient DfT concepts for RF Systems-On-Chip (SOC) are amiss, asshown in the last section. RF PLLs are among the most troublesome buildingblocks on RF SOCs as important signals like RF output or tuning voltage areusually unaccessible from outside. The reduced testability slows down produc-tion test of the whole device under test (DUT). Consequently, this work starts theimprovement of RF SOC testability at the RF PLL. The focus is on -modulated

RF PLLs ( PLLs) as they have become the industry standard for RF synthesisand offer convenient digital modulation capabilities.

PLLs are not only hard to test, the tight interaction between digital blocks (e.g.-modulator) and analog blocks (e.g. VCO and loop lter) is also very hardto simulate, especially when the noise performance is important. Usual mixed-signal, RF or digital simulators do not provide the required simulation perfor-mance out-of-the-box, therefore, a new modeling and simulation methodologyis needed to complement standard simulators.

As the complexity of PLLs will not allow structural test in the near future, thiswork will focus on functional DfT enhancements on block level . In contrastto system level tests, block level tests help to improve yield and the portabil-ity of building blocks like the PLL. The reuse of e.g. central on-chip DSPresources for computationally intensive test routines would require the routingof high-speed signals across the chip and hinder concurrent testing of functionblocks. It also complicates test program development as otherwise unrelatedbuilding blocks have to be synchronized.

Ideally, the block level tests should be autonomous , require no external mea-



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22 2. Fundamentals

Symbols referring to DT terms are denoted by the prescript D as in D f = f T S

Normalized frequencies are written in capital letters, i.e. F , , S

In the DT domain, (angular) frequency is normalized w.r.t. the samplingfrequency f S, in the CT domain w.r.t. a center or corner frequency f c

Quantized terms have a subscript Q , e.g. a 1,QThe DT systems regarded in this work operate at uniform sampling intervals andare shift-invarian t1 , permitting the use of frequency domain signal-ow diagramswhere the unit delay is represented by the symbol z1 .

2.1.2. Denitions

The following denitions have been taken from [Joi08 ], terms in round bracketsare additions by the author:

Accuracy: Closeness of agreement between a measured quantity value and atrue quantity value of a measurand

Precision: Closeness of agreement between measured quantity values obtainedby replicate measurements on the same or similar objects under specied

conditionsUncertainty: Non-negative parameter characterizing the dispersion of the quan-

tity values being attributed to a measurand (usually measured as standarddeviation)

(Measurement) Error: Measured quantity value minus a reference quantityvalue

Bias: Estimate of a systematic measurement error, i.e. component of measure-

ment error that in replicate measurements remains constant or varies in apredictable manner

Resolution: Smallest change in a quantity being measured that causes a percep-tible change in the corresponding indication

Reproducibility: Measurement precision under reproducibility conditions of measurement (e.g. repeated measurements on different testers)

See also Fig. 4.4 for a visualization of accuracy and precision.

1Similar to LTI systems in the CT domain



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2.2. Angle Modulation 23

2.2. Angle Modulation

The topic of angle modulation is especially important for this work for two rea-sons:

Signal: The measurement principle described in this work is built upon fre-quency modulation and demodulation of the device under test. Addition-ally, the DUT utilizes angle modulation for signal transmission.

Noise: In a VCO, voltage and current noise in resistive and active elements areconverted into phase uctuations by a combination of additive and non-linear processes [ LH00 , RA00 ]. Amplitude deviations are usually sup-pressed resp. converted to phase or frequency noise by some form of am-plitude gain control or limiting in the oscillator. For this reason, the quality

of the carrier signal for signal transmission in wireless system is usuallyspecied in terms of phase ("phase noise", "phase instability"), frequency("frequency instability") or time ("time interval error jitter"), all relating toangle modulation.

In the following, phase and frequency modulation are rst described in the timedomain for general and for sinusoidal signals. Next, a linear approximation forsmall-angle modulation is derived to allow analysis in the frequency domain anddifferent measures of angle modulation in the frequency domain are given. Fi-nally, the effect of frequency division on angle modulation is explained.

2.2.1. Angle Modulation in the Time Domain

In systems with a xed frequency and nearly constant amplitude A(t ) A likeoscillators or digital blocks, nearly all noise power Pn near the carrier can becontributed to random phase uctuations n(t ). For this work, it is assumedthat amplitude noise contributions Pn, A are suppressed by amplitude control or

limiting, i.e. Pn = Pn, A + Pn, Pn, in the frequency range of interest. The outputsignal of such a system can be approximated by a purely angle modulated signals(t ) with carrier frequency f 0 and a constant amplitude A (2.2.1 ):

s(t ) = A(t ) cos (2 f 0t + (t )) A cos (2 f 0t + (t )) = Acos i(t ) (2.2.1)where (t ) is the phase deviation from the nominal phase 2 f 0t . As an anglemodulated signal ( 2.2.1 ) has a constant envelope, its power is always P = A2 / 2.The sum of nominal (linear) phase and phase deviation is the instantaneous phase

i(t ) = 2 f 0t + (t ) . (2.2.2)



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2.2. Angle Modulation 25

condition

mPM (t ) = 2 k FM k PM t = mFM ( )d . (2.2.7)

This relationship is utilized in the device-under-test (Sec. 3.2 ) as indirect PM where the carrier is frequency modulated by the differentiated modulation signal.

2.2.2. Sinusoidal Angle Modulation

In the following, the special case of sinusoidal frequency modulation is describedthat can be solved in closed form in contrast to most other modulation cases:A carrier, frequency modulated by a sinusoidal modulation signal mFM (t ) = Am,FM cos mt has the phase and frequency deviation shown in ( 2.2.10 ) - ( 2.2.9 ).

f i,FM (t ) = f 0 + f FM (t ) with f FM (t ) = k FM Am,FM cos mt (2.2.8)

yFM (t ) = f (t )

f 0=

f FM f 0

cos mt = y cos mt (2.2.9) FM (t ) = 2 t = f FM ( )d = k FM Am,FM f m

:=

sin mt (2.2.10)

The ratio of peak frequency deviation f and modulation bandwidth Bm (= f min this case) for analog modulation signals 2 is called frequency modulation in-dex3 f (2.2.11 ) [VDP30 ]. Another common measure is the peak normalizedfrequency deviation y (2.2.11 ):

y :=

f f 0

and f :=

f

Bm=

f f m

=k FM Am,FM

f m= (2.2.11)

with f = 1 and = 1 rad ,(2.2.11 ) also shows that the FM modulation index has the same value as the peak phase deviation measured in rad. As derived in ( 2.2.7 ), a PM signal mPM (t ) cre-ates the same modulated signal sFM (t ) = sPM (t ) = s(t ) as an FM signal mFM (t )

2The modulation index of digital modulation signals is usually dened as the maximum phasedeviation over one symbol period.

3Phase modulation index p is dened in a similar way by the ratio of peak phase deviation andmodulation signal bandwidth.



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30 2. Fundamentals

(2.3.3 ) and (2.3.5 ) show that a sinusoid with frequency f m and a narrowbandnoise signal centered at the same frequency have the same ACF and PSD when

Ps =A2m2

= 2 N 0 BH ( f m) = Pn .

On average, the narrowband noise signal can be represented by a sinusoid withthe same power. Due to the linearity of small-angle modulation, the spectrumcreated by general modulation signal with spectrum H ( f ) can be calculated usingsuperposition.

The FM spectrum of a signal with phase deviation (t ) can be calculated from itsFourier transform ( f ): The spectrum due to each individual frequency compo-nent can be approximated by ( 2.2.15 ) as long as the (linear) small angle approxi-mation is valid, yielding the complete spectrum by superposition ( 2.3.7 ).

FM (t ) = 2 k FM t = mFM ( )d FM ( f ) =

M FM ( f ) j f

for M FM (0) = 0 (2.3.6)

|SFM ( f 0 + f m)|

P 2( f m)

4=

M FM ( f m)2 f m

2

(2.3.7)

A

A

f

A

0

S(f)

f +f 0 m f f f 0 m

A

(a) (b) / 2A = A

/ 2A

22 / 8

/ 22

00

+ m+ m

m

t ( )

/ 2

t ( )

Figure 2.3.: Phasors for small-angle PM/FM, DSB (a) and SSB (b) representation

Phase uctuations can be measured by two fundamentally different procedures,

either by direct spectral analysis of the signal or by prior demodulation , also



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2.3. Phase Noise Metrology 31

called discrimination . These procedures are related to SSB and DSB representa-tion of the modulation [ Pla00 , p. 189ff]:

2.3.1. Double-Sideband Representation

Spectra of angle-modulated signals can be obtained from measurements of thephase resp. frequency deviation, requiring demodulation of the signal. Practicalmeasurements use detectors with an output voltage that is proportional to thephase or frequency deviation. The deviation is measured against an externalreference or a copy of the signal itself (self-referenced). The amplitude of thecarrier is either suppressed (clipping detectors) or needs to be eliminated fromthe results by calibration [ Pla00 ].

Phase Instability

Phase instability S ( f m) is dened as the one-sided PSD of the phase deviation (t ) ( f m).

S ( f m) =2( f m)

2(2.3.8)

S ( f m) has the unit rad 2 / Hz. The pseudo-unit dBrad / Hz is dened in this work

to express S dB ( f m) in a convenient logarithmic scale:

S dB ( f m) (dBrad / Hz ) := 10logS ( f m)

rad 2 / Hz(2.3.9)

Strictly speaking, "per Hz" relates to the argument of the logarithm instead of the logarithm itself - doubling the bandwidth does not give twice the dBrad / Hz value. However, this sloppy use is widely adopted in literature, especially inconjunction with phase noise (see below) and is adopted here as well.

The phase instability S ,FM ( f m) of a signal sFM (t ) frequency modulated bymFM (t ) is derived from ( 2.2.6 ):

FM (t ) = 2 k FM t = mFM ( )d |( f m)|= k FM

M FM ( f m) f m

for M (0) = 0

S ,FM ( f m) = k 2FM M 2FM ( f m)

f 2m

for M (0) = 0 (2.3.10)



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32 2. Fundamentals

The phase instability of sinusoidal FM ( 2.2.12 ) is derived in (2.3.11 ).

FM (t ) =k FM Am,FM

f msin mt = sin mt

S ,FM ( f m) =

2( f m)2 =

2 f 2 ( f m) =

2

2 ( f m) (2.3.11)

Normalizing the PSD of a small-angle modulated signal (2.3.4 ) with respect toits power P = A2 / 2 shows the equivalence to its phase instability (2.3.12 ):

|SFM ( f 0 + f m)|P

= ( f 0) + 22

( f 0 f m) = ( f 0) +S ,FM ( f m)

2(2.3.12)

Frequency Instability

Frequency instability S y( f m) is the single-sided PSD of the relative frequencydeviation y(t ) with the unit rad 2 / Hz resp. the pseudo-unit dBrad / Hz.

The relationship (2.3.13 ) between phase and frequency instability is derived us-ing ( 2.2.4 ) and illustrated in Fig. 2.4 for a typical PLL spectrum: Near the carrier,phase deviation S ( f m) drops with -30 dB/dec, followed by a region of constantin-band noise. Outside the loop bandwidth, phase noise is dominated by the

VCO, decreasing with 20 dB/dec. The slope of the S y( f m) segments in Fig. 2.4 is20 dB/dec larger than the segments of S ( f m) due to the f 2m term in ( 2.3.13 ).

S y( f m) =f 2m

f 20S ( f m) (2.3.13)

2.3.2. Single-Sideband Representation

A single sideband of an purely angle-modulated signal with carrier frequency f 0can be downconverted to an intermediate frequency with a mixer in one or morestages (Fig. 6.1 ). Fig. 2.3 shows that this restriction to a single sideband convertshalf of the phase uctuations to amplitude uctuations with A = A / 2. This phase-to-amplitude conversion enables measurements in the amplitude domain.The SSB amplitude noise power after conversion is A2

2 / 4.

The ratio of this SSB noise power (due to phase uctuations only) to the total

signal power (carrier and sidebands) in a 1 Hz bandwidth is called phase noise



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1 Hz

y

f 1

f f

S (f)

f 0

S(f)

f

f +f 0 m c)a) 1f b)

1 Hz

f 1 m

1 Hz

S (f)/2

m

f

L (f)

f f

m

Figure 2.4.: PSD of signal S( f ) (a), phase noise L ( f ) and phase deviation S ( f ) (b) andfrequency deviation S y( f ) (c)

L ( f m). It is usually specied in the pseudo-unit dBc / Hz, i.e. dB relative tothe carrier. The same caveats apply for the use of this pseudo-unit as explainedabove for phase instability.

L ( f m) =Pn, ( f 0 + f m)

Ptot =

f 0+ f m+ 1Hz

f 0+ f mS( f )d f

Ptot

S( f 0 + f m)/ 2 1Hz

A2/ 2 S ( f m)

2(2.3.14)

Note: Recent standards [ IEE08 ] redene phase noise via the phase instability as

L new ( f m) S ( f m)/ 2 . (2.3.15)This denition avoids the small angle limitation of the conventional phase noisedenition (2.3.14 ) that is no longer valid near the carrier. Both denitions yieldidentical values (but not units!) for small phase deviations when the small-angleapproximation ( 2.2.15 ) is valid, L new ( f m) L ( f m).Note: This work does not address the important issue of how the impact of theinevitable amplitude noise in active and passive components upon the oscillatorphase uctuations can be minimized. To some extent, the amplitude noise is in-dependent of the oscillator amplitude (most obvious for additive noise). Hence,one well-known design strategy is to maximize the VCO amplitude in order tominimize the noise-to-carrier ratio. At rst glance, there seems to be a contra-diction to (2.3.14 ) and ( 2.3.15 ) which claim that the phase instability does notdepend on the carrier amplitude. However, the denition of phase noise containsthe single-sideband noise power that is related to the phase instability via the

small signal approximation.



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These effects can be demonstrated for the case of a carrier with frequency 0 ,frequency modulated by a sine wave of frequency m5 , creating a peak frequencydeviation and a peak phase deviation = / m .

sFM (t ) = Acos 0t +

msin mt

The signal has an instantaneous phase i(t ):

i(t ) = 0t + m

sin mt (2.3.17)

After division by N , instantaneous phase i, N (t ) and frequency i, N (t ) are:

i, N (t ) = i(t ) N =

0t N +

N m sin mt (2.3.18)

i, N (t ) = i(t ) N

=d i, N (t )

dt =

0 + cos mt N

(2.3.19)

For = / m1, small-angle approximation ( 2.2.15 ) can be used to analyzethe effect of division upon the sidebands:

sFM , N (t ) = Acos 0t

N +

N msin mt

A cos 0t N

2 N m

cos 0 N m t (2.3.20)

(2.3.20 ) shows:

Carrier frequency f 0 , peak phase and frequency deviation, and f , arereduced by N

Relative frequency deviation y(t ) = f (t )/ f 0 remains unchanged

Sidebands still are a distance of f m from the carrier The level of the sidebands are reduced by N and hence the power of mod-ulation sidebands and phase noise L ( f ) are reduced by N 2 (when the

carrier amplitude A remains unchanged)

Note: This simple analysis works only for narrowband modulation. In general,the division should be regarded as a subsampling process [ Ter05 ] that folds back wide-band noise into the baseband.

5This could also be a narrowband noise signal.



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36 2. Fundamentals

2.4. Spectral Estimation of Simulation Data

The goal of spectral estimation is to describe the spectral power distribution of asignal, based on a nite set of data. This section reviews the theory of spectral

analysis using periodograms.

Power Spectral Density Estimation

The power spectral density (PSD) of a stochastic process X is dened by theFourier transform of its auto-correlation function (ACF). A random discrete sig-nal x N with nite length N can be seen as a realization of X from which its trueACF and PSD can only be estimated . It can be shown that the magnitude squaredFourier transform of x N , a so called periodogram , is an estimation for the truePSD of X [KK06 ].

Calculating the periodogram of a long sequence x N is very computationally in-tensive which is avoided by averaging the periodograms of K shorter slices x i L of length L < N (Fig. 2.5 ). An averaged periodogram [PM92 ] reduces the varianceand spectral resolution of the estimate by the factor K at the same time.

0 L-1 2L-1L N-1-L N-1 x [k]

x [k]0L x [k]1L x [k]

K-1L

N

Figure 2.5.: Basic slices of the signal x N

The relationship between spectral resolution and variance is improved by Welchsmethod [ Wel67 ] of averaging modied periodograms , calculated from overlap-

ping windowed slices x i L (Fig. 2.6 )

W ( ) =1

L1k = 0 w2[k ]

window power1

K K 1i= 0

L1k = 0

xi L[k ]w[k ]e2 jk 2

periodogram of windowed slice i(2.4.1)

where K is the total number of slices. The averaged periodogram is normalizedby the power of the window function w[k ] for unbiased results [KK06 ]. Thisalgorithm is used in the Matlab scripts for spectral estimation of the VHDL -

simulations.



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2.4. Spectral Estimation of Simulation Data 37

0

x [k]

N-1

N

x * w[k]0L

x * w[k]1L

Figure 2.6.: Overlapping windowed slices of the signal x N

Narrowband and Wideband Signals

The power PS of a narrowband signal is concentrated in one spectral line and canbe read directly from the display. In contrast, the power P N of a broadband signallike noise is distributed over M frequency bins. The displayed power per bin is

therefore given by (2.4.2 ).

Pbin = P N / M or Pbin [dB] = P N [dB] 10log M (2.4.2)The relationship between noise power density P N (specied for a bandwidth of 1 Hz) and displayed power per bin depends on the resolution bandwidth RBW of the spectral estimation:

Pbin = P N RBW or Pbin [dB] = P N [dB] + 10log RBW / 1 Hz (2.4.3)with RBW = B N B/ M

where B N is the equivalent noise bandwidth expressed in bins (see next section)and B is the total bandwidth. For an N FFT -point FFT with a rectangular window,

B N = 1, B = f S/ 2 and M = N FFT / 2, resulting in RBW = f S/ N FFT .

Extracting Noise and Phase Noise from DT Period Data

Spectral estimation of a DT sequence of amplitude values can be performed di-

rectly with the periodogram methods described above. When phase noise has tobe estimated from a DT sequence of period values, produced e.g. by the simpli-ed DT VCO model described in Sec. 4.5.2 , some pre-processing is needed:

The DT period values ck uctuate around the average period T 0 . The cumula-tive sum of the periods, scaled with 2 / T 0 gives the DT approximation to theinstantaneous phase i[ N ] = 2 / T 0 N k ck .

Phase uctuations [k ] = ck are estimated from the instantaneous phase i[ N ] byremoving the linear phase 2 f 0t (Fig. 2.8 ). This is achieved in Matlab by spec-

ifying the option "detrending" for the PSD which is performed using Welchs



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40 2. Fundamentals

2.5.1. Sampling

Sampling creates images of the original signal around multiples of f S that overlapwhen B > f S/ 2 (Nyquist frequency), folding back frequency components above f S/ 2 into the base-band. These components cannot be separated from the originalsignal. This process is called aliasing and can only be avoided by band-limitingthe original signal with an anti-aliasing lter to B f S/ 2.Hence, a sampled signal may be recovered without losses as long as the Nyquist criterion is fullled:

A signal must be sampled at a rate f S equal to or greater than twiceits bandwidth B in order to preserve all the signal information.

2.5.2. Quantization

Quantization reduces the innite amplitude resolution of the analog signal to adiscrete number of levels which inevitably adds distortions that cannot be fullyremoved. In general, it is very difcult to predict the level of distortion as itdepends not only on the quantization step size Q but also on the signal amplitudeand statistics.

Note: A physical interpretation of the numeric quantizer output is obtained by

scaling the output with the quantization step size Q , resulting in a nominal quan-tizer gain of 1.

The quantization error qe(n) is in the range 6 Q / 2 for the case of rounding . Formulti-bit quantizers and sufciently large signal amplitudes, qe can be approxi-mated by a stochastic process with uniform amplitude probability density 1 / Qand a constant power spectral density (PSD) N q( f ) in the interval ( f S/ 2, f S/ 2).Outside this interval the noise spectrum repeats due to sampling. The variance 2e of such a process is given by ( 2.5.1 ).

2e = 2Q / 12 = N q( B = f S/ 2) (2.5.1)

The variance equals the quantization noise power N q( f S/ 2) within the Nyquistbandwidth, obtained by integrating the quantization noise PSD N q( f ) over( f S/ 2, f S/ 2). This allows the calculation of N q (2.5.2 ).

N q( B = f S/ 2) = f S/ 2 f S/ 2 N q( f )d f = N q( f ) f S N q( f ) = 2Q

12 f S(2.5.2)

6For truncation, Q < qe 0



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42 2. Fundamentals

the total quantization noise power in the baseband ( B < f < B) depends on theoversampling ratio OSR = f S/ 2 B. For the optimum case of a brickwall lter with f c = B (Fig. 2.9 ), the SQNR is improved by the oversampling ratio OSR = f S/ 2 B(2.5.8 ).

N q( B) = B

B N q( f )d f = 2Q12

2 B f S

= N q( f S/ 2) 2 B f S= N q( f S/ 2)

OSR(2.5.8)

On a logarithmic scale, this means doubling the OSR improves the SQNR by10log OSR = 3 db, equivalent to increasing the resolution by half a bit.

Another advantage of oversampling is the relaxed requirements for anti-aliasingand reconstruction lters which remove frequency components above f S/ 2: InNyquist rate converters, the signal bandwidth B is just below f S/ 2, requiringsteep analog lters. This is not needed in an oversampling architecture where

B

f S/ 2. Signal and quantization noise between B and f S/ 2 can be removedlater on in the digital domain.

2.5.4. Subsampling and Downsampling

As the Nyquist criterion only requires that the signal bandwidth is lower than the

Nyquist frequency f S/ 2 the signal frequency may be far higher than the samplingfrequency. The signal frequency range f sig has to fall into a single Nyquist zone( N 1) f S/ 2 < f sig < N f S (see Fig. 2.10 ). If this condition is met, the sampledimage of the signal contains all the information of the original signal. When theoriginal signal lies in an even Nyquist zone, the order of frequency components isreversed which can be reversed easily in digital processing. Using a sampling fre-quency below the highest signal frequency (i.e. sampling signals above the rstnyquist zone) is called undersampling or subsampling , independent of whetherthe Nyquist criterion is fullled or not. In contrast, the term downsampling is

used in this work to denominate the whole process of sampling a signal around f sig with a sampling frequency f S after limiting the signal bandwidth to f S/ 2[CT92 , pp. 125].

Decimation 7 by a factor of N operates on a DT signal by keeping 1 out of N samples and discarding the others, yielding an output sampling rate of f S/ N . Thishas the same effect as undersampling a CT signal, consequently, the bandwidth of an DT signal also has to be limited to f S/ 2 N before decimation to avoid aliasing.

7The term has its origins in the Roman method of punishment where a group of men were selected

at random and every tenth one was killed.



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2.6. Sigma-Delta Modulation 45

The major advantage of M over delta modulation is that only a low-pass lterwith relaxed specications instead of an integrator is required for signal recon-struction. Further simplication is obtained by moving both integrators behindthe subtractor (Fig. 2.14 ).

Q

Q

Q

Q

f

+

+sd[n]

LPFilter

s(t)

DAC

Quantizer

DAC

Integrator Sampler

s(t)

Demodulator Modulator

Figure 2.14.: Sigma-Delta modulation and demodulation (efcient implementation)

The advantage of exchanging amplitude resolution against oversampling ratio isalso frequently applied digital signal processing. In this work, M is used inthree different forms:

PLL: The circuit-under-test (Sec. 3.2 ) uses an PLL to achieve a ne fre-quency granularity with a high ("coarse") reference frequency.

-attenuator: In the digital sine generator (Sec. 5.1 ), a large N -by- N bit multi-plier is replaced by a compact M attenuator.

-FM discriminator: In the output response analyzer (Sec. 6.2.2 ), the RF sig-nal is demodulated and quantized with an Sigma-Delta Frequency Discrim-inator ( FD), yielding an M bitstream approximation to the frequencydeviation.

Q

1zsd[n]

Accumulator

s[n]

Quantizer

Figure 2.15.: Digital sigma-delta modulator

In digital M, the integrator is replaced by an accumulator, the DAC in thefeedback path is implemented by a MUX selecting Q / 2 or 0 , Q .As the signal is already DT, the sampler becomes a unit delay that is drawn into



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46 2. Fundamentals

the accumulator (Fig. 2.15 ) with a transfer function H A( z) of

H A( z) =z1

1 z1and | H A()|=

12 2cos

. (2.6.1)

2.6.1. Single Bit Quantizer

For multibit quantizers, the quantizer gain is usually approximated as gQ 1.The output of a single-bit quantizer only depends on the sign of the input value,hence, its "gain" gQ strongly depends on the input signal. Useful approximationsfor gQ can only be made by regarding the closed loop.

The same is true for the full scale amplitude, which is usually dened as thevalue where the input signal becomes equal to the DAC output Q as higherinput signals overload the converter.

For frequencies well below f S/ 2, the loop gain is H A( f )gQ1 and overall gainis determined by feedback. Correspondingly, the quantization error is Q e[n] < Q with a noise power of e2n = ( 2Q )2 / 12 = 2Q / 3.

For the purpose of analysis, the DAC gain factor is absorbed into the quantizer

-output, yielding a Q instead of a 1 stream. This has the advantage that thelow-pass ltered output can directly be interpreted as an approximation to theoriginal signal.

2.6.2. Quantization Noise in M

z 1

1 z 1

n e [n]

s[n]

Quantizer

sd[n]

Accumulator

Figure 2.16.: Model for quantization noise in M bit stream

The model in Fig. 2.16 is used for the analysis of quantization noise in the Mstream sd [n] where the quantizer action has been replaced by adding the quanti-



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zation noise voltage en[n] to the original signal. The digital output stream is

SD( z) = ( S( z) SD( z))z1

1 z1+ en( z)

=S

( z

)

z11 z1 +

en(

z)

1+

z11 z1

1

= S( z) z1

H s( z)+ en( z) 1 z1

H n ( z). (2.6.2)

e [n]

1

(1z )

z

n 1

sd[n] s[n]

Figure 2.17.: Signal and noise transfer functions in rst order M

The resulting bit stream contains the input signal plus the quantization noise.While the signal is merely delayed by one sample, i.e. the signal transfer function(STF) is H s( z) = z1 , the quantization noise en = Q / 12 f S is shaped with thenoise transfer function (NTF) H n( z) = 1 z1 (Fig. 2.17 ). H n attenuates lowfrequencies of en by taking the difference between two consecutive samples. Thefrequency response is calculated using sin 2 x = 12 (1

cos2 x):

H n e j = 1 e j = 2je j/ 2e j/ 2 e j/ 2

2j

= 2e j( )/ 2 sin 2

(2.6.3)

H n e j = 2sin2

= 2sin f f S

(2.6.4)

(2.6.4 ) shows that the quantization noise at the M output is high-pass shaped in

the frequency range 0 . . . f S/ 2, returning to zero at f S. The noise power containedin the bandwidth of interest B is given by ( 2.6.5 ):

N q( B) = + B B H 2n ( f ) N q( f ) d f = + B

B4sin 2

f f S

e2n f S

d f

= + B B 2 1 cos 2 f f S e2n

f Sd f =

2e2n f S

f f S

2 sin

2 f f S

+ B

B

=e2n

2 f

f S sin

2 f

f S

+ B

B=

2e2n

2 B

f S sin

2 B

f S(2.6.5)



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2.6.3. Spurious Tones of First Order M

When a constant signal is applied to a rst order M, the internal quantizedsignal changes between two levels, keeping the mean equal to the input signal.Depending on the level of the input signal x = Q i + b/ aQ with respect to thetwo nearest quantization levels Q i and Q i+ 1 , the output pattern can have a shortpattern length, concentrating the quantization noise in a few strong spectral lineswhich are also called "idle tones". The worst kind of input signals are DC signalswith a low-valued denominator, i.e. a = 2, 3, . . . . This DC pattern noise is a well-known issue of rst order SDMs; expressions for the frequency and power of these lines have been derived by [CB81 , Gal93 ] amongst others.

Figure 2.19.: SDM noise for DC inputs [ CT92 , p. 5]

Fig. 2.19 shows that the peak noise regions are indeed around low-values for a ,i.e. around 1/2, 1/3 etc. When a low-frequency ( f

f S) signal is present, the

SNR is dened by integrating the noise over time while moving along the x-axisin Fig. 2.19 . Choosing a bias point around one of the peak noise regions of Fig. 2.19 will therefore lead to a bad SNR.

2.6.4. Higher Order M

In rst order M, the correlation between input signal and quantization erroris rather strong, leading to patterns in the output bit stream which show up asspurious lines in the spectrum. Additionally, the noise shaping only has a weak,rst order characteristic.

One way to improving rst-order M is to apply the integrated error between



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behavior, resulting in a stronger noise shaping. It is calculated exactly as theNTF of the rst order M (2.6.4 ). The structure in Fig. 2.21 can be rearrangedto obtain the second order single-loop M in Fig. 2.22 with identical STF andNTF. The quantization model for both version is given in Fig. 2.23

n e [n]

sd[n] 11z1

11z1

z112z

Quantizers[n]

Figure 2.23.: Quantization noise model for M in Fig. 2.21 and 2.22

A different architecture for higher-order noise shaping is known under the nameof cascaded SDM or MultistAge noise SHaping (MASH). In this topology, single-and second-order loops are cascaded (Fig. 2.24 ), their single-bit outputs are com-bined in a noise-cancellation block.

The difference between the quantizer output and the output itself of the rst ac-cumulator is quantization noise which is integrated in the second accumulator.The output of the rst stage is summed with the differentiated output of the sec-ond stage. This way, the quantization noise is high-pass shaped while the signalpasses without disturbance.

2 bit

xd(n)

x(n)

CO CO 1z

1z1z

Figure 2.24.: Second order digital M with multistage noise shaping

The main advantage of the MASH architecture is that it is unconditionally sta-ble as it is made of rst order sections without overall feedback. The multi-bitoutput stream necessitates a multi-bit DAC ( -ADCs) which may suffer of non-linearities (in contrast to a one-bit converter). In the circuit-under-test, a third-

order MASH is used within the -PLL to achieve ne frequency granularity



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2.7. Digital Resonators 53

The zeros of the characteristic equation dene the poles z p,i of the system(2.7.2 ):

= 1 + a 1 z1 + a2 z2

z p ,i =

a1

2 a 21

4 a2 (2.7.2)

For the case a2 > a21 / 4, the system has two conjugate complex poles z p ,1 = z p,2 =r p e j p that are written in polar form for this analysis, i.e. as pole radius r p (2.7.3 )and pole angle p (2.7.4 ).

r 2 p = r 2 p,1 = r

2 p ,2 = z p,i

2 =a214

+ a 2 a214

= a 2 (2.7.3)

p,i = arctan{ z p,i}{ z p ,i}

= arctan a 2 a21 / 4a 1 / 2 = p (2.7.4)

a 1 = { z p ,i}= 2r p cos p and a2 = r 2 p (2.7.5)The system is stable when all poles are inside the unit circle i.e. the pole radiusr p is less than one.

1

a

complex poles

2

a

1

1

1

12 2real poles

Figure 2.25.: Stability region of a second order system with real coefcients a 1 , a 2

The stability condition (2.7.6 ) for complex poles is derived directly from (2.7.3 )and visualized as the stability triangle in Fig. 2.25 .

a 2 < 1 for a 2 >a 214 (2.7.6)



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2.7. Digital Resonators 57

0

10

20

30

40

50

60

70

80

0 0.2 0.4 0.6 0.8 1

| H ( ) | ( d B )

Normalized frequency /

Resonator with b = 1, r = 0.99 and = 0 ...

Figure 2.29.: Frequency response of the two-pole resonator with r = 0.99 for differentvalues of

ing a biquadratic or biquad transfer function ( 2.7.18 ).

H ( z) =b0 + b1 z1 + b2 z21 + a1 z1 + a2 z2

= g0( z z z,1) ( z z z,2)( z

z p ,1) ( z

z p,2)

(2.7.18)

Placing zeros at z = 1 ( = 0 and = ) results in a biquad with constantpeak-gain over the whole frequency range that is also very simple to implement[Ste94 ]. The values for the coefcients a1 = 2r p cos p and a2 = r 2 p have beenselected as before.

| H ()|= g0e j z z,1 e j z z,2

(e j z p ,1) (e j z p ,2)= g0

LZ 1 LZ 2 LP1 LP2

(2.7.19)

Similar to ( 2.7.17 ), the frequency of peak gain can be derived as ( 2.7.20 ). Obvi-ously, the zeros at z = 1 prevent setting the peak gain at and near = 0 and = . As the factor for cos p in (2.7.20 ) is always less than 1, a value for cexists for every setting of p . This means, in contrast to ( 2.7.17 ), the resonatorshows peaking for every value of p but peak gain frequencies near = 0 and = cannot be set.

cos c = cos p2r p

1 + r 2 p(2.7.20)



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2.8. Fixed-Point Number Format 63

However, it is obvious that the condition 2 + 2 = 1 for undamped resonancegenerally cannot be achieved for quantized coefcients Q , Q . It is also unprac-tical that both coefcients have to be tuned to modify the resonance frequency.

2.8. Fixed-Point Number Format

When minimum hardware complexity is important, digital signal processing isperformed with xed point arithmetics. In contrast to software and digital sig-nal processor solutions, FPGA and ASIC implementations allow a free choiceof number representation (scaling, bias, twos complement, ...), the number of integer bits QI and fractional bits QF (the position of the binary point) and thetotal word length WL = QI + QF (Fig. 2.37 ). In this work, the "Q-notation" isused:

QU[ QI ].[QF ] for unsigned andQS[ QI ].[QF ] for signed numbers.

MSB

QI

WL

QF

LSB

b0b1b2bQF bQF

1bW L

1 bW L

2 bW L

3

Figure 2.37.: Fixed-point number representation

The same binary word BinWord represents different real-world values ( RWV ),depending on the number format (Tab. 2.1 ). For unsigned numbers, this relationis simply:

RWV = 2QF

W L1

i= 0 bi2i

=

W L1

i= 0 b i2i

QF

For signed numbers, the MSB bW L1 represents the sign bit. The correspondingrelation is

RWV =

W L2i= 0

bi2iQF for bW L1 = 0

W L2

i= 0bi2iQF

2QI for bW L

1 = 1



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2.9.

spectral pll built-in self-test for integrated cellular transmitters

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