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    IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 10, OCTOBER 2013 4159

    Space-Vector PWM With Reduced Common-ModeVoltage for Five-Phase Induction Motor Drives

    Mario J. Durn, Joel Prieto, Student Member, IEEE, Federico Barrero, Senior Member, IEEE,Jos A. Riveros, and Hugo Guzman

    AbstractThe growing interest in multiphase electrical driveshas required the extension of control schemes and modulationtechniques already well known for three-phase drives. Specifically,different and more complex space-vector pulse width modulation(SVPWM) methods have been developed for multiphase machinestaking into account the increased number of switching possibili-ties and the new components resulting from generalized Clarkestransformation. In spite of the intensive work undertaken in thelast decade, no SVPWM techniques with common-mode voltage(CMV) reduction have been developed for five-phase drives. This

    work proposes two SVPWM methods that are capable of reducingthe peak-to-peak CMV by 40% and 80% compared to standardfive-phase modulation strategies. Reduction of the CMV is doneat the expense of higher phase voltage and current distortion.Simulation and experimental results confirm the CMV reductionand quantify the performance penalties of the proposed methods.

    Index TermsCommon-mode voltage (CMV), five-phase in-duction machines, multiphase systems, space-vector pulse widthmodulation (SVPWM).

    I. INTRODUCTION

    T

    HE WORLDWIDE agreement to develop three-phase ACelectrical grids has limited the use of multiphase machines

    in favor of three-phase machines with capability to be directlyconnected to the mains. Nevertheless, the advent of moderndigital signal processors (DSPs) and power electronics hasawaken the interest on multiphase machines since the beginningof the 21st century. Multiphase machines have found a nicheof applications in autonomous systems such as traction orship propulsion where the mandatory use of a power inverterdoes not restrict the number of phases anymore [1][3]. Morerecently, multiphase machines have also been proposed in full-power wind energy conversion systems where the existence

    Manuscript received March 12, 2012; revised June 19, 2012; acceptedJuly 28, 2012. Date of publication September 7, 2012; date of current versionMay 16, 2013. This work was supported in part by the Spanish Govern-ment (National Research, Development, and Innovation Plan, under referencesDPI2011-25396 and DPI2009-07955, and Junta de Andaluca 2010 researchprogram, under reference TEP-5791) and in part by Itaipu Binacional/ParqueTecnolgico ItaipuParaguay.

    M. J. Durn is with the Department of Electrical Engineering, University ofMlaga, 29071 Malaga, Spain (e-mail: [email protected]).

    J. Prieto, F. Barrero, J. A. Riveros, and H. Guzman are with the Depart-ment of Electronic Engineering, University of Seville, 41092 Seville, Spain(e-mail: [email protected]; [email protected]; [email protected]; [email protected]).

    Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

    Digital Object Identifier 10.1109/TIE.2012.2217719

    of an intermediate dc link allows the use of multiphase windgenerators [4].

    The intensive research on multiphase machines has led tothe development of drive topologies and modes of operationnonexistent in standard three-phase drives, including the useof multimotor drives with single inverter supply [5], operationwith enhanced torque in concentrated-winding motors [6], [7],or fault-tolerant modes of operation [8], [9]. In addition tothese novel developments, well-established concepts of three-phase drives have also been reviewed for multiphase driveimplementation. Control schemes including vector control [1],direct torque control [10], or predictive control [11][15] havebeen successfully extended for multiphase systems. Similarly,modulation schemes have been modified to consider the newdegrees of freedom existing in multiphase converters. Theextension of carrier-based pulse width modulation (PWM)techniques for distributed-winding machines in single-motorconfiguration has been straightforward [4], but the space-vectorPWM (SVPWM) techniques [16] or the consideration of non-sinusoidal voltage supply for multimotor, fault-tolerant, andtorque-enhanced drives has required an increased complexity

    [17], [18]. In any case, a wide range of modulation techniqueshas been developed including continuous and discontinuousmultiphase PWM methods for two-level voltage source invert-ers (VSIs) [19], multilevel multiphase PWM techniques [20],[21], or modulation for open-end drive topologies [22]. In spiteof the vast work undertaken to develop multiphase modulationsand control schemes, there is a lack of analysis of the common-mode voltage (CMV) reduction in five-phase drives.

    Reduction of CMV has been an issue of interest in thedesign of PWM techniques because CMV is known to causeelectromagnetic interference, breakdown of winding insulation,and fault activation of current detector circuits and leakage

    currents that may damage the motor bearings [23][28]. Apercentage of the CMV (typically 10% [28]) appears betweenthe motor shaft and the grounded motor frame, allowing par-asitic currents to flow via the motor bearings. These leakagecurrents, associated to the shaft-to-frame voltage, depend onvariables like the motor speed, bearing temperature, type ofbearings, or power level to name a few [24]. They can severelydamage the bearings and reduce the drive robustness. While thedisplacement bearing currents are generated by the dv/dt ofthe inverter, the electric discharge machining (EDM) bearingcurrents are generated when the peak value of the CMV exceedsa certain threshold, causing the dielectric breakdown of thebearing lubricant [23][27]. Aiming to avoid bearing currents,

    0278-0046/$31.00 2012 IEEE

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    different modulation techniques for three-phase machines havebeen proposed both for two-level [28][30] and three-level[31], [32] VSIs. Sine-triangle PWM with interleaved carriers[30] inherently reduces the appearance of the zero vectors{000} and {111}, thus reducing the rms value of the CMVbut still allowing CMV peaks of Vdc/2. Zero vectors can,

    however, be fully eliminated by substituting the zero vectorsby active vectors in phase opposition with equal duty cycles.This approach is adopted in [29] proving that the peak values ofthe CMV can be reduced to Vdc/6. Carrier-based versionof this strategy can be found in [28] with some modificationsof the basic idea of [29]. All these works are, however, devotedto three-phase drives and have not been extended to five-phasedrives so far.

    This work extends the fundamental idea of [29] to the caseof one of the most interesting multiphase drives from theapplication point of view, the five-phase induction motor drive.As in three-phase drives [28][30], the modulation techniqueswith reduced CMV can be used in any multiphase applica-tion where the bearings can be damaged due to the peak-to-peak CMV. Five-phase VSIs, in comparison to theirthree-phase counterparts, present an increased complexity be-cause the number of voltage vectors is increased (from 23 = 8to 25 = 32), the size of the voltage vectors is not unique (zero,small, medium, and large vectors are present), and an additionalsubspace appears (so-called xy plane) [1]. Compared to thethree-phase case, the dv/dt of the CMV in five-phase drivesis inherently reduced because it is, in general, equal to Vdc/n,being n the number of phases of the system. Nevertheless, thepeak-to-peak CMV remains as in the three-phase case equalto Vdc. Similar to the approach adopted for three-phase drives

    [28][30], the modification of the switching pattern cannotreduce the dv/dt but can effectively reduce the peak-to-peakCMV. In the five-phase system, the CMV presents now sixdifferent levels, and elimination of zero vectors does not ensureminimum CMV peak values as it occurs in three-phase VSIs.All these issues are discussed and analyzed, and two SVPWMalgorithms for the reduction of CMV in five-phase VSIs areproposed and compared to standard five-phase SVPWM.

    This paper is structured as follows. Next section analyzesthe CMV in five-phase induction motor drives. Section IIIdescribes the modeling of the five-phase VSI and presents thebasic outlines to mitigate CMV in a five-phase drive. Two

    proposed SVPWM techniques with CMV reduction capabilityare described in Section IV. These techniques are analyzedin Section V, where simulation and experimental results arepresented and discussed. The conclusions are summarized inthe last section.

    II. CMV IN FIVE-P HASE DRIVES

    Five-phase induction motor drives have attracted much atten-tion among multiphase induction motor drives as an alternativeto standard three-phase drives [1]. This work considers a drivewith a distributed-winding five-phase induction motor with 72

    of spatial displacement between stator windings and a two-levelfive-phase inverter (Fig. 1).

    Fig. 1. Two-level five-phase induction motor drive scheme showing theleakage currents flowing via the grounded motor frame.

    The CMV, from now on VCM, relates the motor neutralvoltage to the midpoint of the dc link, and its expression in two-level three-phase drives is [32]

    VCM =Vdc

    3 (Sa + Sb + Sc)

    Vdc2

    = VnN Vdc

    2(1)

    where Vdc is the dc link voltage, VnN relates the motor neutralvoltage to the negative rail of the VSI (Fig. 1), and Si {0, 1} denotes the switching functions of each VSI leg. From(1), it follows that the maximum peak value of the CMV is|VCM| = Vdc/2, the minimum voltage variation is Vdc/3, andthe number of CMV levels is four.

    Most of the techniques for CMV reduction avoid the zerostates {SaSbSc} = {000} or {111}, maintaining the voltagevariation of Vdc/3 but reducing the peak value of the CMV

    to Vdc/6 (66% of reduction). Consequently, the dv/dt (causeof displacement bearing currents) remains constant, but thereduction of the maximum |VCM| helps to mitigate the mainsource of leakage current, namely, the EDM bearing currents.

    The expression of the CMV in five-phase drives can bedirectly extrapolated from (1) as

    VCM =Vdc

    5 (Sa + Sb + Sc + Sd + Se)

    Vdc2

    . (2)

    In this case, the maximum peak value of the CMV is still|VCM| = Vdc/2, but the number of CMV levels is increased tosix and the minimum voltage variation is reduced to Vdc/5.

    Therefore, in spite of dealing with a two-level VSI, the CMVpresents more levels because additional switching combina-tions are possible due to the multiphase nature of the converter.The dv/dt is thus reduced in five-phase drives independent ofwhich SVPWM technique is selected.

    From (2), it can be deduced that the switching combina-tions generate six different values of the CMV: 0.1 Vdc,0.3 Vdc,and 0.5 Vdc. The switching states can be grouped(Table I) into those that generate the following:

    1) large CMV (0.5 Vdc): switching states with allswitches on or vice versa, referred to as 05;

    2) medium CMV (0.3 Vdc): switching states with one

    switch on and four switches off or vice versa, referredto as 14;

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    TABLE IMAGNITUDE OF CMV ACCORDING TO THE SWITCHING STATES

    3) small CMV (0.1 Vdc): switching states with twoswitches on and three switches off or vice versa, referredto as 23.

    As in the three-phase case, zero vectors (05) generate thehigher CMV and must therefore be avoided if the bearingvoltage needs to be diminished. However, avoiding the selectionof zero vectors only reduces the CMV by 40%, so the use ofmedium CMV voltage vectors should be also restrained in orderto further reduce the bearing voltage.

    III. FIVE-P HASE VSIS AND CMV MITIGATION

    Two-level five-phase VSIs (Fig. 1) have 25 = 32 differentswitching states. A switching function Sk {0, 1} can bedefined in a way that Sk is one when phase k is connected tothe positive rail of the VSI (top switch on and bottom switchoff) and Sk is zero when phase k is connected to the negativerail of the VSI (top switch off and bottom switch on). The stateof the converter is then determined by the switching state of itsfive legs, which can be defined as

    S= [Sa Sb Sc Sd Se] (3)

    where vector notation is indicated using underlined variables.Each switching state is numbered from now on according to itsbinary number

    Sa 24 + Sb 2

    3 + Sc 22 + Sd 2

    1 + Se 20. (4)

    In addition, leg voltages can then be expressed as

    VkN = Sk Vdc (5)

    being Vdc the voltage of the dc link. Assuming that the five-phase induction machine (Fig. 1) has an isolated neutral, thephase voltages can be calculated as

    vkn =4

    5VkN

    1

    5

    5i=1,i=k

    Vi. (6)

    Phase voltages can then be mapped into the and xysubspaces using the current invariant transformation provided

    Fig. 2. Zero, small, medium, and large vectors in the and xy planes

    using the five-phase power converter and its correspondence with the small(23), medium (14), and large (05) CMV switching states.

    by the general Clarkes transformation [1]

    vvvxvyv0

    =

    2

    5

    1 cos() cos(2) cos(3) cos(4)0 sin() sin(2) sin(3) sin(4)1 cos(2) cos(4) cos(6) cos(8)0 sin(2) sin(4) sin(6) sin(8)1

    2

    1

    2

    1

    2

    1

    2

    1

    2

    vanvbnvcn

    vdnven

    (7)

    where = 2/5. The last row of the transformation corre-sponds to the zero sequence component discussed in the pre-vious section. The voltage vectors can be represented intwo different planes providing zero, small, medium, and largevoltage vectors [1]. Note that the size of the voltage vectorsin or xy subspaces is different from the size of theCMV referred to in the previous section (see Table I and Fig. 2for clarification). From the relations shown in Table I andFig. 2, it follows that the elimination of medium voltage vectorsseems not critical because the control remains for low and

    high modulation indices using small and large voltage vectors,respectively.

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    Elimination of zero (05) and medium (14) vectors is alsoacceptable in the overmodulation region because large (23)vectors can still be chosen. As a general rule, the followingrelationships apply.

    1) Switching states 05 generate zero voltage vectors bothin and xy subspaces and provide large CMV

    (0.5 Vdc).2) Switching states 14 generate medium voltage vectorsboth in and xy subspaces and provide mediumCMV (0.3 Vdc).

    3) Switching states 23 generate small voltage vectors inplane and large voltage vectors in xy plane or viceversa and provide small CMV (0.1 Vdc).

    For the sake of example, switching state 25 corresponds tothe switching state [1 1 0 0 1] according to (4) and generatesa large voltage vector in the first sector of the subspace,a small voltage vector in the fifth sector of the xy subspace,and a small CMV of0.1 Vdc.

    IV. SVPWM WIT H REDUCED CMVIN FIVE-P HASE DRIVES

    Standard SVPWM for three-phase VSIs has been recentlyextended to multiphase drives [16][21]. Although the principleof operation of the SVPWM is similar, the algorithm hasadditional complexity because the number of voltage vectorsis increased from 23 = 8 to 25 = 32, the number of sectors isincreased from six to ten, and the number of subspaces is alsoincreased with the appearance of the nonelectromechanicallyrelated xy voltage components [1]. Four different SVPWMtechniques are described in this section: SVPWM1 is the stan-

    dard technique for five-phase VSIs in the linear region, andSVPWM2 and SVPWM4 are different proposals that aim toreduce CMV. Notice that SVPWM3 will be also presented tointroduce SVPWM4 technique.

    A. SVPWM1: Large, Medium, and Zero Voltage Vectors

    In the initial attempts to develop multiphase SVPWM al-gorithms, only two active vectors per sector (the largest onesin the plane in Fig. 2) were selected to generate thereference voltage in the subspace v. However, this pro-cedure leads to low-order voltage harmonics due to high xy

    voltage components. Consequently, this modulation techniquehas become acceptable only in the overmodulation zone. Toovercome this shortcoming, standard SVPWM for five-phasedrives in the linear range applies four active vectors per sector(large and medium ones in Fig. 2) to simultaneously achievethe voltage reference in the subspace (v) and cancel thexy voltage components (vxy = 0) [16]. Zero vectors 031 arethen applied during the rest of the sampling period.

    For the sake of example, let us consider a reference voltagevector v that is located in sector I (upper plot, Fig. 2). Large(24, 25) and medium (16, 29) voltage vectors are selected tobe applied during the sampling period Ts [Fig. 3(a)]. Selectedvectors are preordered to ensure that only one switching cycle

    per phase occurs, thus maintaining the switching frequencyequal to 1/Ts. According to the definition of (4), this task

    Fig. 3. Voltage vectors selected for the SVPWM in the first sector. (a) Case 1:Large, medium, and zero vectors. (b) Case 2: Large, medium, and phase-opposed vectors. (c) Case 3: Large, adjacent large, and zero vectors. (d) Case 4:Large, adjacent large, and phase-opposed vectors.

    implies applying the vectors in ascending order. For example,in sector I, the order becomes 0, 16, 24, 25, 29, and 31.Once the switching states are properly ordered, voltage vectorsare applied twice to obtain a symmetrical switching pattern[Fig. 4(a)]. The times of application of the active vectors 16,24, 25, and 29 can be calculated as

    t1t2t3t4

    =v1 v2 v3 v4v1 v2 v3 v4v1x v2x v3x v4xv1y v2y v3y v4y

    1 vv

    00

    Ts (8)

    where subscripts 14 refer to the four preordered active vectors(1 16, 2 24, 3 25, and 4 29), subscripts ,,x, and yrefer to the voltage components after Clarkes transformation(7), and superscript indicates reference values (provided by anouter control loop). Zero vectors 031 are then applied duringthe rest of the sampling period

    t0 = Ts 4

    k=1

    tk (9)

    being t0 always positive in the linear region.The SVPWM using zero, medium, and large voltage vectors

    in the subspace, referred to from now on as Case 1 orSVPWM1, provides six CMV levels ranging from 0.5 Vdc to0.5 Vdc, as shown in the lower part of Fig. 4(a). Conse-quently, in spite of the good performance in terms of phasevoltage generation, the peak-to-peak value of the CMV is high(equal to Vdc). The linear modulation range extends up to M=1.0514 = 1/ cos(/10), being M the modulation index [19]

    M=2 |V|

    Vdc

    (10)

    where |V| is the peak value of the ac phase voltage.

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    Fig. 4. Switching patterns and CMV for different SVPWM techniques. (a) Large, medium, and zero vectors. (b) Large, medium, and phase-opposed vectors.(c) Large, adjacent large, and zero vectors. (d) Large, adjacent large, and phase-opposed vectors.

    B. SVPWM2: Large, Medium, and Phase-Opposed

    Voltage Vectors

    Aiming to reduce the CMV, the zero vectors 031 can be

    replaced by two active vectors in phase opposition both in and xy subspaces. A similar proposal is stated in [29] butfor a three-phase power converters. The SVPWM2 proposalextends those ideas to the multiphase case. As far as the timeof application of these phase-opposed vectors is the same andequal to t0/2, any two active vectors in phase opposition willgenerate a zero vector on average and will therefore obtainsimilar average output voltage as in Case 1 where true zerovectors 031 are used. However, some of these vectors gen-erate a switching pattern with more than one switching cycle(on off on or vice versa) per sampling period (Ts), thusincreasing the switching frequency. For example, looking atthe switching pattern of Fig. 4(a), it follows that vector 0

    cannot be replaced by a vector with Sb = 1, Sc = 1, or Se = 1if only one switching cycle per sampling period is required.

    Only three pairs of vectors in phase opposition preserve theconstant switching frequency 1/Ts, ensuring that only oneswitching cycle per sampling period occurs: 1318 (smallvectors), 1516 (medium vectors), and 229 (medium vectors).Any of these three options generate zero average voltage andpreserve constant switching frequency, but vectors 1318 areselected because of the small generated CMV (0.1 Vdc).This SVPWM, further on referred to as Case 2 or SVPWM2,is shown in Fig. 3(b) (selected voltage vectors) and Fig. 4(b)(switching pattern and generated CMV). It is noticeable thatthe elimination of the zero vectors 031 reduces the peak CMVby 40%, being the peak CMV equal to 0.3 Vdc [Fig. 4(b)].It must be highlighted that the maximum linear modulationrange of SVPWM2 is the same as in SVPWM1 (i.e., M =1.0514) because the times of application t0 of the voltagevectors in phase opposition (1318) are the same as those of

    the zero vectors and the active vectors remain the same for bothcases.

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    C. SVPWM3: Large, Adjacent Large, and

    Zero Voltage Vectors

    Cases 1 and 2 make use of the large and medium vectorsto generate the voltage reference v . However, mediumvectors generate higher CMV (0.3 Vdc) than small andlarge vectors (0.1 Vdc). Consequently, it seems convenient

    to replace medium voltage vectors by small or large vectors inorder to further reduce the CMV. A modification of SVPWM1can be obtained by substituting the medium vectors (1629 insector I) by the small vectors (926 in sector I). Unfortunately,vectors 25 and 9 do not have y component, while vectors 24 and26 have negative y component, thus being impossible to satisfythe vxy = 0 condition.

    Considering that medium voltage vectors generate highCMV and small vectors cannot provide null xy voltages, largevectors in adjacent sectors are considered next. Focusing on thecase of sector I, adjacent large vectors are switching states 28and 17. It can be observed in Fig. 2 that the location of large

    (2425) and adjacent large (2817) active vectors in the xyplane is adequate for cancelation.Let us first consider the case with zero, large, and adjacent

    large vectors, further on referred to as Case 3 or SVPWM3.This SVPWM3 implies the use of vectors 0, 17, 24, 25, 28, and31 in sector I [Fig. 3(c)]. Times of application can be calculatedaccording to (8) and (9), and the symmetrical switching patternof Fig. 4(c) is then obtained. In spite of preordering the selectedvectors to obtain minimum average switching frequency, it isnoticeable that leg e completes three switching cycles in asampling period. The average switching frequency is thus in-creased to 1.4/Ts because of these additional switching cycles.Furthermore, application of zero vectors 031 maintains thepeak-to-peak CMV equal to Vdc, as shown in the lower part ofFig. 4(c). Both disadvantages make SVPWM3 (also termed 4LSVPWM in [19]) impractical. However, it is possible to replacezero vectors 031 in such a way that the switching frequencyremains constant and the peak-to-peak CMV is reduced.

    D. SVPWM4: Large, Adjacent Large, and Phase-Opposed

    Voltage Vectors

    Focusing on the switching pattern of SVPWM3 [Fig. 4(c)],it can be deduced that it is not possible to obtain just oneswitching cycle in phase e. For this reason, the active vectors

    are preordered following the sequence 28, 24, 25, and 17. Withthis new sequence of application, it is now possible to achieve aconstant switching frequency if the following are considered.

    1) The switching state of phase e for vectors 0 and 31 cannotbe changed.

    2) The switching state of phases a and d for vectors 0 or 31can be changed or not.

    3) The switching state of phases b and c for both vectors 0and 31 needs to be mandatorily changed.

    The pairs of voltage vectors that comply with the aforemen-tioned conditions are 1219 (large), 1417 (large), 283 (large),and 30-1 (medium). Any of the first three pairs of switch-

    ing states can adequately replace vectors 031 with constantswitching frequency and minimum CMV (0.1 Vdc), reduc-

    TABLE IICOMPARISON OF SVPWM1SVPWM4

    TABLE IIIELECTRICAL PARAMETERS OF THE FIV E-PHASE MACHINE

    Fig. 5. Experimental system, including the power and control modules at theleft side and the five-phase induction machine at the right side.

    ing the peak-to-peak CMV to 80% compared to SVPWM1.The dv/dt still remains as in the standard SVPWM1 and pro-posed SVPWM2, being equal to Vdc/5. Using the pair 1219[Fig. 3(d)], referred to from now on as Case 4 or SVPWM4, theswitching pattern and generated CMV of Fig. 4(d) are obtained.

    The set of selected vectors includes the six large vectors adja-cent to the reference (three clockwise, three counterclockwise),and the application order is clockwise.

    Note that the linear modulation range of Cases 34 is thesame as in Cases 12 (Table II). Using (8) and (9) and imposingthe condition t0 > 0 for the four different SVPWM techniques,it follows that the linear range lays within the range [01.0514].Similarly, the maximum modulation index in overmodulationzone is M = 1.2311 in all four cases because only large vectorsare used in the pulse dropping region. A comparison of thefeatures of the four SVPWM techniques is summarized inTable II. As far as the CMV is concerned, Case 4 provides thebest performance although a more distorted waveform is ex-

    pected. Compared to three-phase drives, it must be highlightedthat both the dv/dt (due to the multiphase nature of the system)

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    Fig. 6. Experimental CMV in tests supplying a five-phase passive resistive load with different modulation indices (M = 0.2, M = 0.5, and M = 1.05) anddifferent SVPWM techniques. Case 1: Large, medium, and zero vectors; Case 2: Large, medium, and phase-opposed vectors; Case 4: Large, adjacent large, andphase-opposed vectors.

    and the peak-to-peak CMV (due to specific switching patterndesign) are reduced from Vdc/3 to Vdc/5.

    V. SIMULATION AND EXPERIMENTAL RESULTS

    The reduction of the CMV using modulation strategies

    SVPWM1, SVPWM2, and SVPWM4 is experimentally veri-fied in a test rig based on a 30-slot two-pairs-of-poles three-phase induction machine, whose stator has been rewound toprovide a five-phase induction machine with three pairs ofpoles. Parameters of the machine have been determined usingconventional and standstill tests with inverter supply [33],[34], and the obtained values are those shown in Table III. Aschematic of the rig and photographs of the complete systemare shown in Fig. 5. Five phases of two conventional three-phase VSIs from Semikron (SKS21F) have been used to drivethe machine. The control system is based on the MSK28335board and the TMS320F28335 DSP, and the induction machineis operated in open-loop mode of operation.

    Measurements are obtained using a digital scope, a currentprobe, and a differential voltage probe (Tektronix TDS3014B,

    TCP202, and P5205). All simulation and experimental resultshave been obtained using a switching frequency of 2 kHz.Tests have also been performed using a five-phase passiveresistive load. These tests were conducted with a fundamentalfrequency of 10 Hz and a dc link of 100 V and modulationindices of 0.2, 0.5, and 1.05, while the tests with the five-phaseinduction machine were obtained with a dc link of 300 V anda fundamental frequency of 25 and 50 Hz, using modulationindices of 0.5 and 1.

    Although the time of application of zero vectors is reducedas the modulation index is increased, the qualitative CMVwaveforms of Fig. 6 closely resemble those of Fig. 4. Six,four, and two levels of the CMV are obtained implementingSVPWM1, SVPWM2, and SVPWM4, respectively. Peak-to-peak CMV is reduced from 100 V in SVPWM1 test to 60 V inSVPWM2 test and 20 V in SVPWM4 test. These experimentalresults confirm the 40% and 80% of CMV reduction alreadypredicted in Section IV.

    Nevertheless, the elimination of certain switching possi-

    bilities is expected to generate more distortion in the phasevoltage and currents [30]. This is also confirmed in the phase

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    Fig. 7. Simulated phase voltage waveform for modulation index M = 0.5and different SVPWM techniques. Case 1: Large, medium, and zero vectors;Case 2: Large, medium, and phase-opposed vectors; Case 4: Large, adjacent

    large, and phase-opposed vectors.

    Fig. 8. Simulated and experimental THDs of the phase voltage versus modu-lation index for different SVPWM techniques. Case 1: Large, medium, and zerovectors; Case 2: Large, medium, and phase-opposed vectors; Case 4: Large,adjacent large, and phase-opposed vectors.

    voltage waveform shown in Fig. 7, where it can be noted thatthe substitution of zero and medium vectors by small/largevectors increases the waveform distortion. In order to quantifythe distortion, Fig. 8 shows the simulated and experimentalphase voltage total harmonic distortions (THDs) for differentmodulation indices.

    The THD has been calculated considering harmonics up to15 kHz according to the expression

    THD =

    V22

    + V23

    + + V2nV1

    (11)

    where Vk is the rms value of the kth voltage harmonic.

    As expected, the THD is reduced in all cases as the modula-tion index is increased because the duty cycles of the active

    vectors become higher. Results from simulations and exper-iments show good agreement. Fig. 8 also shows the higherdistortion for those methods with reduced CMV (SVPWM2 andSVPWM4) compared to standard SVPWM1. The deteriorationof the waveforms is more noticeable at low modulation indiceswhere phase-opposed vectors in Cases 24 need to be applied

    during a longer period of time. On the contrary, all methodsconverge as the limit of the linear modulation region is ap-proached. The narrow difference in terms of THD performanceof methods SVPWM2 and SVPWM4 is noticeable. Consider-ing that the peak-to-peak CMV obtained using SVPWM2 isthree times higher than using SVPWM4, it can be deduced thatSVPWM4 presents better overall performance in terms of phasevoltage THD.

    Obtained results using the multiphase electrical drive aresummarized in Fig. 9. SVPWM1, SVPWM2, and SVPWM4techniques have been implemented with modulation indicesequal to 0.5 and 1. It is shown that phase voltage and currentwaveforms using SVPWM2 are more distorted than thoseobtained using SVPWM1, which agrees with results shown inFigs. 7 and 8. This is so because zero vectors have been replacedby active vectors in phase opposition.

    Performances of SVPWM1 and SVPWM2 are proved to besimilar in terms of phase current distortion and converge athigh modulation indices (M= 1.05). Notice that phase voltagewaveform shows an excellent agreement with simulation results(Fig. 7). CMV for the three methods is also shown in Fig. 9,confirming simulation results shown in Fig. 7: the peak-to-peakCMVs of SVPWM2 and SVPWM4 are 40% and 80% lower,respectively, than that of SVPWM1.

    Even though all three methods (SVPWM1, SVPWM2, and

    SVPWM4) can synthesize both and xy references, theswitching harmonics can generate additional torque ripple andlosses, respectively. Fig. 10 shows the and xy currentswith the three methods for modulation indices M = 0.4 and1.05. It can be noted that the xy currents are higher usingSVPWM2 compared to SVPWM4, while the opposite occurswith the currents. It can be concluded that the reductionof the CMV is obtained at the expense of additional losses(SVPWM2) or torque ripple (SVPWM4).

    VI. CONCLUSION

    Standard SVPWM techniques for five-phase VSIs generatehigh peak-to-peak CMV that can be a source of undesired leak-age currents. Since each VSI voltage vector is associated to aninstantaneous level of the CMV, eliminating certain switchingstates can reduce the peak-to-peak CMV in five-phase drives.Eliminating zero vectors can reduce the CMV by 40%, andavoiding zero and medium vectors can further reduce the CMVby 80% compared to standard modulations. Both strategies,termed SVPWM2 and SVPWM4 in this work, show similarperformance to standard SVPWM1 at high modulation indices,but the performance is diminished at low modulation indices.Even though the peak-to-peak CMV is three times lower using

    SVPWM4 instead of SVPWM2, higher torque ripples can beobtained due to the absence of medium voltage vectors. Both

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    DURN et al.: SVPWM WIT H RE DUC ED CO MM ON-MO DE VO LTAG E FO R FIV E-PH ASE IN DU CT IO N MOTO R DR IVE S 4167

    Fig. 9. Experimental phase voltage (upper trace), phase current (middle trace), and CMV (lower trace) in tests supplying the five-phase induction motor withdifferent modulation indices (M = 0.5 and M = 1) and different modulation techniques (SVPWM1, SVPWM2, and SVPWM4).

    Fig. 10. (Outer circle) Experimental currents and (inner trace) xycurrents with modulation indices M = 0.41.05 and different modulationtechniques: (Upper trace) SVPWM1; (middle trace) SVPWM2; and (lowertrace) SVPWM4.

    SVPWM2 and SVPWM4 show an interesting prospect for

    industrial applications where the leakage currents produced byhigh peak-to-peak CMV are a main concern.

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    Mario J. Durn received the M.Sc. and Ph.D.degrees in electrical engineering from the Univer-sity of Malaga, Malaga, Spain, in 1999 and 2003,respectively.

    He is currently an Associate Professor with theDepartment of Electrical Engineering, University ofMalaga.

    Prof. Duran was the recipient of the Best Paper

    Award from the IEEE TRANSACTIONS ON INDUS-TRIAL ELECTRONICS in 2009.

    Joel Prieto (S10) was born in Asuncion, Paraguay.He received the B.Eng. degree in electronicengineer-ing from the Universidad Catolica Nuestra Seorade la Asuncion, Asuncion, in 2005, and the M.Sc.degree from the University of Seville, Seville, Spain,in 2009, where he is currently working toward thePh.D. degree.

    In 2008, he joined the Department of ElectronicEngineering, University of Seville. His researchinterests include modern modulation and control

    strategies of multiphase drives.Mr. Prieto is a recipient of a scholarship from Itaipu Binacional/ParqueTecnologico ItaipuParaguay for his Ph.D. studies.

    Federico Barrero (M04SM05) was born inSeville, Spain, in 1967. He received the M.Sc. andPh.D. degrees in electrical and electronic engineer-ing from the University of Seville, Seville, in 1992and 1998, respectively.

    Since 1992, he has been with the Department ofElectronic Engineering, University of Seville, wherehe is currently an Associate Professor. His recentinterests include microprocessor and digital signal

    processor device systems, sensor networks, and con-trol of multiphase ac drives.

    Jos A. Riveros received the B.Eng. degree in elec-tronic engineering from the Universidad Nacional deAsuncin, San Lorenzo, Paraguay, in 2007 and theM.Sc. degree from the University of Seville, Seville,Spain, in 2010, where he is working toward the Ph.D.degree.

    Since 2009, he has been with the Department ofElectronic Engineering, University of Seville.

    Mr. Riveros is a recipient of a scholarshipfrom Itaipu Binacional/Parque Tecnolgico ItaipuParaguay for his Ph.D. studies.

    Hugo Guzman received the B.Eng. degree in elec-tronic engineering from the Pontificia UniversidadJaveriana, Bogota, Colombia, in 2009 and the M.Sc.degree from the University of Seville, Seville, Spain,in 2011, where hehas been working toward the Ph.D.degree in the Department of Electronic Engineeringsince 2010.

    Since 2007, he he has been with the Departmentof Electronic Engineering, University of Seville, as aResearch Assistant.