space vector pwm method for ultra sparse matrix converter using fpga xc3s500e

Download Space Vector PWM Method for Ultra Sparse Matrix Converter Using FPGA XC3S500E

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Gii thut iu ch Vector khng gian PWM cho Ultra Sparse Matrix Converter thc hin vi card FPGA XC3S500E

Abstract: The Ultra S parse Matri x converter (US MC) circuit, which simpl y consists of nine single switches, shows a great advantage to a much more burdensome conventi onal Matrix converter, which invol ves double number of s witches. Being due to this least number of switches, US MC is the most compact design. Des pite its restricted requirement of uni directional power fl ow applications, US MC has the same high quality output waveform of conventi onal Matrix converter. In this paper, a whole control algorithm of US MC was entirely designed on Xilinx XC3S500E Spartan-3 E FPGA. The algorithm's efficiency is verified through simul ation for switching strategy of US MC. Experimental results of switching gate signals are shown and compared to theoretical swi tching sequence. Experi mental input and output waveforms are also analyzed. I. GII THIU Kh i cng ngy cng c nhiu s quan tm v cc b bin i xoay chiu AC-AC ng dng cho cc my pht nng lng gi i hi t nh linh hot cao. B bin i ma trn thu ht c rt nhiu s nghin cu trong hin ti v tng lai. Vi cu trc tt c u l kha bn dn v khng c bt c thnh phn d tr nng lng no, b bin i ma trn c th to ra dng sng u vo, u ra c dng sin vi h s cng sut u vo c th iu khin c. Tuy nhin, tr ngi chnh ca b bin i ma trn l rt d gy ra qu p trong qu trnh ng ngt; v vy mt vi cu hnh c a ra cho gii thut ng ngt v cu trc n gin hn nh mt gii php thay th. Mt s dng mi ca b bin i ma t rn c bit n nh: B bin i ma t rn hai tng hoc l B bin i ma trn tng kp c ngh [1]. c bit l Sparse matrix converter vi vic gim s kha chnh lu u vo [2],[3]. Ultra sparse matrix converter l dng gn nht ca Sparse matrix converter vi 9 kha ng ngt n v 18 diodes cng vi mch kp bao gm 1 d iode Dc v 1 t Cc nh trn Hnh 1. u im ca Sparse matrix converter so vi b bin i ma trn truyn thng l gii thut ng ngt n gin v an ton hn do ng ngt bn pha chnh lu khi dng bng 0, v mch kp bo v cng n gin hn. Ngy nay cng ngh FPGA cho php thc hin c nhiu gii thut iu khin phc tp. Kh nng thc thi nhiu php tnh song song lm FPGA l mt cng ngh cho nhng h thng iu khin i hi p ng nhanh v chnh xc cao. Trong bi bo, g ii thut iu ch vector khng gian cho

Ultra Sparse Matrix converter c thc hin trn card Xilin x XC3S500E Spartan-3E FPGA. M hnh m phng cho Ultra Sparse Matrix converter c xy dng s dng MATLAB/Simu link. M hnh phn cng ca Ultra Sparse Matrix converter c xy dng kim chng tnh kh thi thc t ca gii thut. Nhng kt qu thc nghim v xung kch c to ra bi card FPGA ca tng chnh lu v nghch lu c a ra v so snh vi chui xung kch ng ngt ca gii thut. Cc kt qu thc nghim v dng sng u vo u ra ca gii thut iu ch vector khng gian cng c phn tch.idc SAp Dc Sa Sb Sc Cc Udc SAn SBn SCn SBp SCp

isa

isb

isc iA iB iC

Vsa

Vsb

Vsc

Hnh 1.

Ultra Sparse Matrix converter

II. IU CH VECTOR KHNG GIA N A. Phng php PWM cho tng chnh lu: in p ba pha u vo:

(1)

Chu k ca in p ba pha u vo c chia thnh 6 khong nh Hnh 2.

B. Phng php iu ch vector khng gian cho tng nghch lu Tng t nh phng php iu ch vector khng gian cho nghch lu 2 bc, thi g ian ng ngt T1 , T2 and T0 s c tnh ton khi vector khng gian p quay vi in p DC trung bnh ca tng chnh lu l .V3(010) V2(110)

- 6 6 2

0

5 7 3 11 6 6 2 6

uoV4(011)

0

V1(100)

Hnh 2.

Su khong chia ca in p ba pha u vo

Gi s ti thi im ly mu in p ba pha ang nm trong khong 1 thuc on [-/6, /6]. Trong khong ny ln in p Vsa ln hn in p Vsb v Vsc. Do vy trong sut chu k ng ngt thuc on [-/6, / 6]. Kha Sa s ng duy tr trong mt chu k v 2 kha cn li Sb v Sc s ng vi t s ng ct d b v dc nh sau:

V5(001)

V6(101)

Hnh 3. Gin vector khng gian p u ra . S thay i gi tr trung bnh ca p DC theo chu k ng ngt lm thay i ng knh lc gic, phm vi thay i xc nh bi vng t m.

Tuy nhin gi tr trung bnh in p DC thc s l Khi kha Sb c ng, in p Vdc s bng in p Vab vi t s db . Khi kha Sc ng, in p Vdc s bng in p Vac vi t s d c. Gi t r trung bnh p Vdc trong mt chu k s l: (3) Th (1) v (2) vo phng trnh (3), g i tr trung bnh in p Vdc trong mt chu k thu c nh sau: Vi mv : t s iu ch p u ra 0 : gc quay ca vector khng gian p Tng qut gi tr trung bnh p Vdc trong mt chu k s l: tng chnh lu, gi tr in p Vdc c 2 khong gi tr, in p Vdc s bng Vab trong khong Ts db vi t s ng ct db v Vdc s bng Vac trong khong Ts dc vi t s ng ct d c nh c din t trong Hnh 4. tng nghch lu gi t r thi g ian ng ngt T1 , T2 , T0 tng ng vi cc vector V1 , V2 , V0 cng s c phn phi trong 2 khong ny. Gi tr thi g ian c phn phi trong khong Tsd b : , do vy gi tr thi g ian T1 , T2 s c nhn thm vi h s s ca in p. b cho s chnh lch so vi gi tr thc

Vi Bng 1: Tr ng thi ng ngt tng chnh luSa Sb Sc Vdc_p Vdc_n Vdc ia ib 1 0 1 Vsa>Vsc Vsa Vsc Vac idc 0 VsaVsc Vsb Vsc Vbc 0 idc VsbVsa Vsb Vsa Vba -idc idc Vsb