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Measurement Methods and Applications to High-Performance

Timing Test

Mani SomaUniv of Washington, Seattle

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PurposeTo emphasize the measurement issuescritical in high-frequency testTo develop in-depth understanding of noisein measurements

timing noise, phase noise in RF systemsnoise in converters

To provide a foundation for research in RF measurement and test

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OutlineTop-down view of measurement issuesBasic noise mechanisms and modelsNoise in measurement circuits

converters (sampled data)PLL & VCO (clocks and data control)

Case studies in measurementexisting methods and their noise considerations

Research in measurement methodsSoma 4

System-level ViewFocus on measurements in RF systems

RFRFBasebandBaseband

Link ManagerLink ManagerL2CAPL2CAP

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DataData Cont

rol

Cont

rol

HardwareHardwaremodulesmodules

SoftwareSoftwareTCP/IPTCP/IP HIDHID RFCOMMRFCOMMApplicationsApplications

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RF Test Requirements High-frequency test for specific blocks

RF digital blocks: PLL, I/O buffersRF analog / mixed-signal blocks: transceiver, modulator, VCO, LNA, etc.

Functional parametric test to verify performance

Phase, frequency, jitter, SNR, spectrumAutomatic test

Role of low-frequency ATESoma 6

High-frequency Test ApproachesWhich measurement can be done most efficiently at high-frequency?

VoltageCurrentTime

Which high-frequency measurement tool is available?

GHz clocksVery fast sampler, converters

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Focus on MeasurementMeasure = acquire raw data from a signal

usually taken for granted but …..the critical first step of any test procedurestrong impact on final test accuracy and decisionstrong impact in evaluating tradeoffs between on-chip and off-chip test

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What Do We Measure?Voltage

capture signal points (tn,Vn), n=1,NS/H, ADC, and sampling clocks

most popular measurement methodsin oscilloscopes, spectrum analyzers, etc.in ATE

post-processingpeak detection, voltage gain, amplitude, etc.timing estimation (e.g. zero-crossing)FFT: amplitude, phase, noise, etc.

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What Do We Measure? (2)Current

capture current values (at one or a few points)resistor,current sensor, clocks

implementationbuilt-in compliance in benchtop instrumentin ATE for IDDQ test

limited usesimple short/open detectionIDDQ, IDDt, IDDx testing for various faults

post-processingusually for IDDQ applications

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What Do We Measure? (3)Time and frequency

direct measurement by capturing signal edgesclocks for capturing edges

indirect measurement via FFT of voltage samplesrecent strong interest in direct timing measurement

on-chip BISTbenchtop instrument (e.g. Wavecrest)

post-processingFFT and / or statistical analysis

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Measurement IssuesNo perfect measurement existsLimitations to accuracy

noise: fundamental limitinteractions between measuring instrument and circuit under test (CUT)post-processing methods and interpretation of results

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Research in measurement methods

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Noise Characteristics & Models

Component noise and impact on measurement

intrinsic noiseboth in CUT and in measurement circuits

Timing noise of high-frequency circuitshigher-level modelsmeasurement methods

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thermal noiseinherent (T=0K, k=1.38E-23 J/ 0K)1 KΩ @ 250C or 298 0K @ 1 MHz has 4 µV noise

Resistor Noise

e n2 4k T R f∆=

in2 = 4kT∆f / R

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Resistor Noise & Sampling JitterResistor noise creates timing uncertainty in input sampling

need to design for at high frequencies

Example50 Ω system, 10 MHz clock with 250 ps rise time noise-induced 2.7 ps jitter with 0.5V input

∆ tC L K0.7 k T R n

f C L K A π t r C L K,-------------------------------------------=

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Wiring Impact16-bit ADC on loadboard, Zin = 5K Ω, 5 cm of PCB copper track (0.25 mm wide, 0.038 mm thick) between input and signal sourceR (wire) = 0.09 Ωgain error = R / Zin = 0.0018% (> 0.0015% = LSB for 16 bits)data accuracy is no longer 16-bit!!

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Other Resistor’s ParasiticsSkin effects (f > 10 MHz for high resolution converters and high-frequency clocks)Copper (on PCB or on chip)

Skin − depth(cm) = 6.6 / f (Hz)

Rsquare(Ω) = 2.6*10−7 f (Hz)

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Resistive Noise Reduction MethodsReduce noise in design

use differential designsmatch layoutmodel and simulate with noise sources, series inductance and parallel capacitance

Reduce noise in measurementuse shielding or guarduse differential measurement circuitsuse low-valued resistorsreduce measurement bandwidth if possibleuse averaging methods in voltage measurement

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Noise in CapacitorsCapacitance between parallel wires -> crosstalkCapacitance between bond wires (~ 0.2pF)Capacitor intrinsic noise

1 pF @250C has 64 µV noise

en (C) =kTC

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Capacitor Models in Measurement

Use different models depending on measurement applicationsAdd noise models for each component

Leakage-current model High-frequency model

High-current modelDielectric-absorption model

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Shot noiseDiscrete nature of current flowShot noise current

q=1.602E-19 Canother type of white noise

In2 = 4qIDC ∆f

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1/f noiseFlicker noise (terminology from vacuum tube)

generally 1/fα, α = 0.8 - 1.3very common

Many namesexcess noise, pink noise, contact noise, etc.burst noise (popcorn noise): 1/fα, α = 1 - 2, usually 2red noise: 1/f2

Spectral density

Sn( f ) =En2

f

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Noise bandwidthNoise bandwidth ≠ 3-dB bandwidth

usually larger than 3-dB bandwidthDefinition

system with voltage gain Av(f) or power gain A2v(f),

maximum gain = Av0

∆f =1

A 2v 0

Av ( f )2

0

∞

∫ df

First-order lowpass filter example3-dB bandwidth = fLnoise bandwidth = πfL/2

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Noise bandwidth (2)

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Note on measurementWhite (thermal) noise

longer measurement time reduces noise impactaccuracy increases as (Tmeasure)1/2

1/f noisemeasurement accuracy does not increase with measurement time

Burst noiseamplitude and frequency (# bursts/sec)need bandwidth large enough to capture sudden short burst, small enough to avoid thermal noise dominance

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“Ground” in measurementrealistic ground (ground loop)

Signal ADC

Ground loop impedance

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Other ground loopsCurrent from one source flows through ground impedance of the other sourceCurrent around ground loop creates magnetic coupling

Signal source A

Next stage

Current IA

Signal source B Current IB

Ground loop CUTTest

Instruments

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Dealing with ground loopsGuidelines for both design and testSeparate digital and analog power and groundJoin grounds at one point of the device

Digital logic on chip Converter OUT

AGNDDGND

System Analog GND

VDD VDD AVDD

IN

Blocks on one chip

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Signal routing guidelinesSeparate analog and digital signalsAvoid crossovers between analog and digital signalsLayout sampling clock and analog input wires carefullyLayout high-impedance signals carefullyUse differential designs

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Noise in test set-upInstruments, ATE, on-chip test circuits all have noise

fundamental limit to measurement accuracysystem noise floor

highly dependent on test set-upno industry standard for interpretationneed to understand basic mechanisms to interpret measurement and test results

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System noise componentsRandom noise

random timing jitter of test clocksthermal noise

Digital crosstalk and clock / signal harmonicsdistinct spikes in spectrumcorrelated to analog input or clocksynchronized noise

Other noise sourcesbroad “needles” in spectrumswitching power supplies, linear power supplies, switching signalsnon-synchronized Soma 32

Case study: System noiseUse ADC to characterize system noiseIdeal 16-bit ADC

SNR (dB) = 6.02*16 + 1.76 = 98.08 dBSNR = SQDR: noise includes quantization distortion, dynamic non-linearities, internal jitter, and internal thermal noise

Measure via coherent samplinglarger sample size -> noise spread over more samples -> noise per FFT bin decreasesnoise improving figure NIF with N=2K samples

NIF(dB) = 10 logN2

= 3.01(K − 1)

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Noise floor calculations16-bit ADC, 217 samples

SQDR = 98.08 dB, NIF = 48.16 dBnoise floor (dBc) = SQDR+NIF= 146.24 dB

dBc: reference to fundamental signal amplitudenoise floor (mean and absolute values)

signal swing: -5V to +5Vsignal amplitude: 5V or 20 log 5 = 13.98 dBVmean noise floor (dBV) = 146.24 - 13.98 = 132.26 dBabsolute noise floor (dBV) = 132.26 - 11 = 121.26 dB

11 dB: worst-case bin 11 dB greater than mean bin, due to Gaussian distribution of quantization noise

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Sample size vs. noise floorSmall number of samples: noise floor not visible

SQDR+NIF

Noise floor due to quan-tization distortion

50-60 Hz power noise switch powersupply noise

fsample/2

0 dB

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Sample size vs. noise floor (2)Larger number of samples: noise floor components and spurious component

SFDR = spurious-free dynamic range

SQDR+NIF

SFDR0 dB Harmonics

Fundamental

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Case study: experimentAnalogic ADC 4355Input signal frequency fi = 997.162 Hz (approx. 1 KHz)Sampling frequency fs = 100000.0135 Hz (approx. 100 KHz)

Nyquist bandwidth = 50 KHzNumber of signal periods = 1307Record size = 131072 samples = 217

FFT frequency resolution = 100 KHz/217 = 0.763 Hz

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What type of sampling?From the spectrum, is the sampling coherent? accurate? Why?Is the sampling clock jitter-free? Why?

Fundamental

0 1 KHz 5 KHz

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Harmonics and spurious noiseIs the spike at 11.965 KHz a signal harmonic or spurious noise?

Fundamentalf=997.162 Hz

f=11.965 KHz

0 12.5 KHz

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Harmonics and spurious noise (2)Is the spike at 27.491 KHz a signal harmonic or spurious noise?

25 KHz 37.5 KHz

27.491 KHz

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Answersfi (signal) = 997.162 Hzfs (sampling) = 100000.0135 Hzf=11.9659 KHz = 12 * 997.162 Hz = 12th harmonicf=27.491 KHz = 2*fs - 173*fi = 173th harmonic folded back into the Nyquist band

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Harmonics identificationHigher harmonics folded back into theNyquist bandn = frequency zone

zone 0: 0 - 0.5 fs (Nyquist band)zone 1: 0.5 fs - fszone 2: 1.5 fs - 2 fs

M = Mth harmonic of signal (M=1,2,3…)f (Mth harmonic in zone n folded to Nyquistzone) = (n * fs + M * fi) or (n * fs -M * fi)

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Harmonics and signalGiven input frequency fi and sampling frequencyfs, identify harmonic bin fb

i = largest integer <= 2 fi/ fs

Given a peak frequency fb and sampling frequency fs, identify signal frequency fi

i = 0,1,2,3.. (ambiguity in identification)need 2 sampling rates to identify better

fb = (−1)i fi − i +1− (−1)i

2

fs

2

fi = (−1)i fb + i +1− (−1) i

2

fs

2

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Noise calculation in convertersDAC

ground all digital inputsplace noise sources (thermal, shot, 1/f, etc.) in appropriate circuit elementscontributions from each noise source type

resistor, opamp, input voltage noise, input current noise

calculate total noise using circuit analysissum independent noise power

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DAC R-2R network noiseTotal noise spectral density

independend of NE2

n=4kTR

R R R R

2R 2R 2R 2R 2R 2R

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DAC binary-weighted networkTotal spectral density

approximately E2n=2kTR

En2 =

4kTR

1 +2N −1 − 12N −1

2R

R

4R

2nR

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DAC topologies vs. noise4 topologies

R-2R with voltage followerR-2R with inverting amplifierR-2R with non-inverting amplifierBinary-weighted with inverting summer

Which has lower total noise at output?Why?

R-2R with follower

R-2R with inverting amplifierR-2R with inverting amplifier

R-2R with non-inverting amplifier

Binary-weighted with inverting amplifier

R-2Rnetwork

R-2Rnetwork

R-2Rnetwork

binarynetwork

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DAC noise analysisNormalizing assumptions

to make noise transfer function = 1 in all topologiesR-2R networks: RF=RI=RA=Rbinary-weighted network: RF=Req=R/2

Lowest noiseR-2R with follower (fewest components, no multiplication of opamp noise due to gain=1)binary-weighted could be better if amplifier noise dominates

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DAC noise lessonsUse amplifier with lowest noise

En of amplifier dominates DAC noiseUse low-noise reference voltage

second dominant noise factorBinary-weighted DAC

below 1 KHz: resistor 1/f noise dominatesabove 1 KHz: voltage reference noise dominates

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ADC noise modelFlash ADC exampleNoise components

resistor noisereference noisecomparator noise (voltage and current)

Noise models: white and 1/fIgnore digital encoder noise

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ADC noise analysis

largest contribution of Vrefnoise

all other sources contribute most noise at the mid-range comparators

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ADC noise vs. bit errorNoise distribution with respect to LSBquantization window

Gaussiancenter of each quantized step

6σ spread of the noise distributionwithin quantization step: no bit erroroutside quantization step

calculate probability of one-bit error

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Phase noise and timing jitterTwo domains to characterize clocks in measurement

timing systems: jitterRF systems: phase noisehow to relate them?

Case study: VCO and other oscillatorsSφ(ω) = phase noise in dBc (reference to carrier at ω0) at the offset frequency (ω- ω0) from the carrierJcc,RMS = RMS value of cycle-to-cycle jitterwhite noise sources (thermal and shot noise)

Sφ (ω) ≈(ω0

3 / 4π )Jcc ,RMS2

(ω − ω0 )2

Jcc, RMS2 ≈

4πω03 Sφ (ω)(ω − ω0 )

2

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Phase noise and timing jitter (2)VCO case study

2.2 GHz, -94 dBc/Hz @ 1 MHz offset is equivalent to 0.3 ps RMS value of cycle-to-cycle jitterabsolute thermal jitter given a measurement time ∆t

jitter increases with measurement time

Jabs =f02

Jcc,RMS ∆t

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Noise and timing jitter (1)VCO with supply and substrate noise

non-white noise: model by noise modulationVmcos(ωm(t))RMS value of period jitter JP,RMS

increases with noise amplitudeRMS value of cycle-to-cycle jitter Jcc,RMS

increases with noise frequency

JP,RMS =VmKVCO

2 f02

Jcc, RMS =VmKVCO

f02 1 − cos(ωm / f0) ≈

VmKVCOωm

2 f03

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Noise and timing jitter (2)Single-ended VCO

supply and substrate noiseVm=∆VDD=100 mVanalytical vs. simulated results

period jitter

cycle-to-cycle jitter

noise frequency,MHz

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Noise and timing jitter (3)Differential-ring VCO

supply and substrate noiseVm=∆VDD=100 mVanalytical vs. simulated results

period jitter

cycle-to-cycle jitter

noise frequency,MHz

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Measurement guidelinesSpectrum analyzer

more noise measured with higher bandwidthcannot be compared directlydivide each noise measurement by (∆f)1/2 for comparison

analyzer calibrated resolution bandwidth ≠ noise bandwidthneed to know how to interpret measured data correctly

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Measurement timeInstrument response time: τ

smallest time window possibleMeasurement bandwidth: ∆fRelative error:

Use widest possible bandwidth (see next slide)narrowband measurements require more averaging for same accuracy

Use long time window (with averaging when appropriate)

ε =12τ∆f

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Noise reduction in measurementUse measurement methods with differential circuits and signalsUse smaller bandwidth

just “enough” bandwidth to reduce noise and still get good accuracy (previous slide)

Employ signal separation and shieldingReduce transition switching in the measurement circuits

use current-steering methods in analog measurement circuits to avoid di/dt transient

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Noise reduction in measurement (2)“Instrument” = ATE, external instrument, or on-chip measurement circuitConsiderations for sub-ps timing measurements

DUT - instrument interfaceinstrument one-shot resolution / accuracyinstrument DC input accuracyinstrument physical location relative to DUTinstrument jitter noise floorinstrument throughput over data interfaceinstrument trigger modeinstrument bandwidth required to measure DUT timing parameters (rise, fall, delay, etc.)

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Measuring Voltage: Sampling

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Sampling Architecture

Consider noise floor of entire test set-up, including on-chip measurement circuits

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Sampling Clock IssuesFrequency

On-chip: limited by technology (CMOS, SiGe CMOS, BiCMOS)

2 - 5 GHzsame speed as fastest on-chip signals

unable to sample at Nyquist rate

ATE: 1 GHzlimited by pin electronics and test set-up

Benchtop instrumentup to 40 GHz samplers

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Faster Sampling MethodsDelay-line interpolation

on-chip or ATE1 GHz clock + 7-stage delay line (125 ps each) = 8 GHz sampling clock

clock jittercorrelated jitter

clock jitter

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Faster Sampling Methods (2)Parallel samplers

ATE and benchtop instrumentsup to 40 GHz sampling rate

clock jittercorrelated jitter?

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Sampling LimitationsClock jitter

signal with 100-ps rise timesampled with 5-ps jitterclock 5% error in sampled values

averaging to reduce error in periodic signalsno correction for one-shot signal

jitter

signal

CLK

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Sampling Limitations (2)Clock synchronization

synchronized with signal to be sampledsynchronized between sampling clocks

CLK1

CLK2

trigger

signalsynch

clocksynch

signal

clock jitter

correlated jitter?

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Realistic clock jitter valuesOn-chip (CMOS / BiCMOS) as of 2002:

2.2 GHz - 6 GHz clocks30 - 40 ps peak-to-peak jitter3 - 5 ps RMS jitter

Off-chipATE, oscilloscope, spectrum analyzer, TIA

1 - 10 ps RMS jitter200 fs resolution with 2 ps noise floor (best case)need calibration before measurements

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Sampling Limitations (3)Undersampling is better?

Lower-frequency more stable clocksFundamental problems in time coherency

ReferenceCLK

sample @ t=1.01 unit sample @ t=1.02 unit

t=1.015 unit

jitter=0.005 unit

ideal edge (no jitter)

t=1.01 unit

clock jitter

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Measuring Voltage: Sampling

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Sampling Limitations (4)Sample-and-Hold (capacitor noise, opamp noise, switching noise)

limited bandwidthaperture errortransient response, overshoot, etc.

ADC (noise estimation from previous slides)sample rates at 8-bit < 400 MHzparallel (4-channel) ADC: synchronization error

ATE or benchtop instrument only

Memory storagelimited on-chip memory or temporary buffer

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Sampling noise sourcesUncorrelated noise

thermal noise1/f noise

Correlated noise (difficult to estimate correlation)power supply noisesubstrate noiseclock synchronization noise

delay-line generation of clocks, parallel clocks

Noise floor of the on-chip measurement circuitin dB for amplitude samplingin ps for timing accuracy

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Direct Digital ConversionSigma-delta modulator

pulse-density conversion methodlow frequency and low conversion rates

clock jitter

edge jitter

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Method limitationsClock jitterJitter in output signal edges

need to characterize for each modulator designPost-processing issues

what parameters to extract from pulse stream?on-chip or off-chip extractioncorruption / modulation of signal edges during processing due to jitter and noise sources

correlation to accepted measurementsphase noise, frequency, timing parameters

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Measuring Current on ATEVS2

Tester Channel #2

VS1

CircuitUnderTest

Tester Channel #1

Loadboard

supply noise supply noise

supply noise

resistive noise

current shot noise

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Measuring Current on Chip

GND

BIC Sensor

Vdd

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Current Measurement IssuesSlow measurement

ATE: 100 µs - 3 ms; BICS: 50 µs - 500 µsLower accuracy than voltage measurementEffects on on-chip VDD and GND

power supply values reduced due to sensorspower supply noise and ground noise increase

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Current measurement noise sources

Uncorrelated noisethermal noise1/f noiseshot noise

Correlated noisepower supply noisesubstrate noise

On-chip comparator noisereference noisecomparator offset and input noise

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Methods to Measure TimeSampling

indirect method, already coveredCounter-based methodTime-to-voltage converterTime-to-digital converterDifferential oscillator methodDelay search methodStart-and-stop counter method

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Counter-based MethodTime interval much larger than TCLK

Resolution = 1 clock period TCLKimproved by delay-line interpolation

clock jitter

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Counter-method ObservationsAll-digital circuits

more robust and scalable with processesaccuracy can be improvedeasier on-chip circuit designs

Key noise is clock jitterNeed modifications if the time interval to be measured is < Tmin of fastest signalsThe core of many subsequent techniques

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Preset

MeasureT

C

V

Io

GND

Io

Time-to-Voltage Converter

Need a DC voltage measurement or Pass / Fail comparisonRequires analog components

sources of errorsMeasurement time

T+ pre-charge time

V = VDD – IoTC

clock jitter

switch noise

capacitor noise

shot noise

supply noise

supply noise

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DQ

DQ

DQ

DQ

DQ

DQ

CLK

IN

DELAY ELEMENTS

Time-to-Digital ConverterDelay-line method to search for a signal edgeResolution = 1 unit delayRobust and very popular

clock jittercorrelated jitter

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Differential-Oscillator MethodMeasure a time interval T

Credence, Vector12

T to be measured

m1 cycles

m2 cycles

CLK1

CLK2

T = m1T1 − m2T2

clock jitter

correlated?

accuracy of coincidence detector

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Differential-Oscillator Method (2)

Measurement time depends on edge coincidence

coarse / fine tuning optionsmiss many edges in a periodic signal

no cycle-to-cycle measurement

Clock-triggering mechanisms and errorsJitter on measuring clocks CLK1, CLK2

may be correlatedNoise and error in coincidence detector

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Delay Search MethodAdjust Capture CLK to measure delay

absolute value or Pass / Failmay be used to search for a signal edge

Resolution in the ps range for on-chip testLaunch Launch

CLKCLK

Launch Launch inputsinputs

Capture Capture CLKCLK

clock jitter

clock jitter

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Start-Stop Counter Method

Taverage = mCLKTCLK /Nsignal −edges

edge jitter

clock jitter

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Start-Stop Method ObservationsVariations of basic counter methodsStart clock to count at one signal edge and stop count at another predetermined signal edgeMostly digital designsSame issues with other counter-based methodsAdditional problem due to re-triggering after stop

dead-time intervalCore of Wavecrest timing analyzer

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Sampling ResearchSampling in the presence of both voltage noise and timing jitter

theory and noise analysisnew sampling and post-processing methods

Undersampling research with low timing coherency

critical for on-chip RF testFast clocks for Nyquist sampling

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Current-measurement Research

Faster methods to measure currentsHigher measurement resolution

at lower VDDBetter designs of BICS to reduce noise effects on power supply and GND

critical for on-chip testMore post-processing theory and methods

comparable to voltage sampling

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Timing-measurement Research

Theory and methods to reduce impact of jitter and timing noise in measurementFundamental understanding of physical effects in turning ON / OFF transistors

critical to controlling clock edgescritical also to sampling and current-based methods

Better circuits to capture timing edgesprocess variations

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Leaping toward the UnknownContinuous-time measurements possible?

all current methods capture discrete values or edges, not waveform segmentsno Sample-and-Hold

Get rid of switches in measurement circuits?

no timing uncertaintyProcessing analog values directly?

no ADC, no clocks, no switchesSoma 98

ConclusionNoise models of basic components in on-chip design-for-test circuitsNoise of measurement circuits and their impact on accuracy

noise source identification from measured datanoise components in each measurement method

Guidelines for low-noise measurementsSuggested research problems

soma 1 soma 2 - university of washingtonfaculty.washington.edu/manisoma/ee540/timing-methods.pdf ·...

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