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Solutions Manual to Accompany

FUNDAMETALS OF

SEMICONDUCTOR

FABRICATION

G. S. May Motorola Foundation Professor

School of Electrical & Computer Engineering Georgia Institute of Technology

Atlanta, GA, USA

S. M. SZE UMC Chair Professor

National Chiao Tung University National Nano Device Laboratories

Hsinchu, Taiwan

1

John Wiley and Sons, Inc

New York. Chicester / Weinheim / Brisband / Singapore / Toronto

2

Contents

Ch.1 Introduction ----------------------------------------------------------------------------- N/A

Ch.2 Crystal Growth ------------------------------------------------------------------------ 1

Ch.3 Silicon Oxidation ---------------------------------------------------------------------- 8

Ch.4 Photolithography------------------------------------------------------------------------12

Ch.5 Etching -----------------------------------------------------------------------------------15

Ch.6 Diffusion ---------------------------------------------------------------------------------18

Ch.7 Ion Implantation ------------------------------------------------------------------------26

Ch.8 Film Deposition -------------------------------------------------------------------------32

Ch.9 Process Integration ---------------------------------------------------------------------40

Ch.10 IC Manufacturing----------------------------------------------------------------------65

Ch.11 Future Trends and Challenges--------------------------------------------------------78

0

CHAPTER 2

1. C0 = 1017 cm-3

k0(As in Si) = 0.3

CS= k0C0(1 - M/M0)k0-1

= 0.3×1017(1- x)-0.7 = 3×1016/(1 - l/50)0.7

x 0 0.2 0.4 0.6 0.8 0.9

l (cm) 0 10 20 30 40 45

CS (cm-3) 3×1016 3.5×1016 4.28×1016 5.68×1016 1.07×1017 1.5×1017

02468

10121416

0 10 20 30 40 50

l ( cm)

N D (1

016

cm

-3)

2. (a) The radius of a silicon atom can be expressed as

Å175.143.583 so

83

=×=

=

r

ar

(b) The numbers of Si atom in its diamond structure are 8.

So the density of silicon atoms is

32233 atoms/cm 100.5

)Å43.5(88

×===a

n

(c) The density of Si is

3

23

2223

cm / g 1002.6

10509.28/1

1002.6/

×

××=

×=

nM

ρ = 2.33 g / cm3.

1

3. k0 = 0.8 for boron in silicon

M / M0 = 0.5

The density of Si is 2.33 g / cm3.

The acceptor concentration for ρ = 0.01 Ω–cm is 9×1018 cm-3.

The doping concentration CS is given by

1

000

0)1( −−= ks M

MCkC

Therefore

318

2.0

18

1

00

0

cm108.9

)5.01(8.0109

)1( 0

−

−−

×=

−×

=−

=k

s

MMk

CC

The amount of boron required for a 10 kg charge is

2218 102.4108.9338.2000,

×=××10 boron atoms

So that

boron g75.0atoms/mole1002.6

atoms102.4g/mole8. 23

22

=×

××10 .

4. (a) The molecular weight of boron is 10.81.

The boron concentration can be given as

318

2

233

atoms/cm1078.9 1.014.30.10

1002.6g81.10/g1041.5

fersilicon wa of volumeatomsboron ofnumber

×=××

×××=

=

−

bn

(b) The average occupied volume of everyone boron atoms in the wafer is

2

318 cm

1078.911×

==bn

V

We assume the volume is a sphere, so the radius of the sphere ( r ) is the

average distance between two boron atoms. Then

cm109.243 7−×==πVr .

5. The cross-sectional area of the seed is

22

cm 24.0255.0

=

π

The maximum weight that can be supported by the seed equals the product of the

critical yield strength and the seed’s cross-sectional area:

k 480g108.424.0)102( 56 =×=×× g

The corresponding weight of a 200-mm-diameter ingot with length l is

m.56.6cm656

g 4800002

0.20)g/cm33.2(2

3

==∴

=

l

lπ

6. We have

1

000

0

1/−

−=

k

s MMkCC

Fractional 0 0.2 0.4 0.6 0.8 1.0 solidified

C 0.05 0.06 0.08 0.12 0.23 ∞ 0/Cs

3

0.01

0.11

0.21

0 0.2 0.4 0.6 0.8 1

Fraction Solidified

Cs/

Co

7. The segregation coefficient of boron in silicon is 0.72. It is smaller than unity, so the solubility of B in

Si under solid phase is smaller than that of the melt. Therefore, the excess B atoms will be thrown-off

into the melt, then the concentration of B in the melt will be increased. The tail-end of the crystal is the

last to solidify. Therefore, the concentration of B in the tail-end of grown crystal will be higher than

that of seed-end.

8. The reason is that the solubility in the melt is proportional to the temperature, and the temperature is

higher in the center part than at the perimeter. Therefore, the solubility is higher in the center part,

causing a higher impurity concentration there.

9. The segregation coefficient of Ga in Si is 8 ×10-3

From Eq. 18

C Lkxs ekC /

0 )1(1/ −−−=

We have

cm. 24 ln(1.102) 250

105/10511081ln

1082

/11ln

1615

3

3-

0

==

××−

×−×

=

−

−=

−

CCk

kLx

s

10. We have from Eq.18

C ])/exp()1(1[0 LxekekCs −−−=

4

So the ratio )]/exp()1(1[0/ LxekekCsC −−−=

= (1 1/at 52.0)13.0exp()3.01 ==×−•−− Lx = 0 at x/L = 2. 38.

11. For the conventionally-doped silicon, the resistivity varies from 120 Ω-cm to 155 Ω-cm. The

corresponding doping concentration varies from 2.5×1013 to 4×1013 cm-3. Therefore the range of

breakdown voltages of p+ - n junctions is given by

V 11600 to7250/109.2)(106.12

)103(1005.1

)(2

17119

2512

12

=×=××

×××=

≅

−−

−

−

BB

Bcs

B

NN

Nq

VEε

V 4350725011600 =−=∆VB

%307250/2

±=

∆

∴ BV

For the neutron irradiated silicon, ρ = 148 ± 1.5 Ω-cm. The doping concentration is 3×1013 (±1%).

The range of breakdown voltage is

V

. V 9762 to9570

%)1(103/109.2/103.1 131717

=

±××=×= BB N

V 19295709762 =−=∆VB

%19570/2

±=

∆ BV

∴ .

12. We have

ls

CCCC

MM

ms

lm

l

s =−−

==b

b

Tat liquid ofweight Tat GaAs ofweight

Therefore, the fraction of liquid remained f can be obtained as following

5

65.03016

30=

+≈

+=

+=

lsl

MMM

fls

l .

13. From the Fig.2.11, we find the vapor pressure of As is much higher than that of the Ga. Therefore,

the As content will be lost when the temperature is increased. Thus the composition of liquid GaAs

always becomes gallium rich.

14.

−×=×=−=

)300/(8.88exp105)/eV 3.2exp(105)/exp( 2222

TkTkTEN ssn

= 1 K 300 C27at 0cm1023. 0316 =≈× −−

= K 1173 C900at cm107.6 0312 =× −

= . K 1473 C1200at cm107.6 0314 =× −

15. )2/exp(` kTENN ff −=n

= )300//(7.94242/1.1/8.32722 1007.7101105 TkTeVkTeV eee −−− ××=××××

= at 27 1027.5 17−× oC = 300 K

=2.14×1014 at 900oC = 1173 K.

16. 37 × 4 = 148 chips

In terms of litho-stepper considerations, there are 500 µm space tolerance between the mask

boundary of two dice. We divide the wafer into four symmetrical parts for convenient dicing,

and discard the perimeter parts of the wafer. Usually the quality of the perimeter parts is the worst

due to the edge effects.

6

CHAPTER 3

1. From Eq. 11 (with τ=0)

x2+Ax = Bt

From Figs. 3.6 and 3.7, we obtain B/A =1.5 µm /hr, B=0.47 µm 2/hr, therefore A= 0.31 µm. The

time required to grow 0.45µm oxide is

min 44hr 0.720.45)0.31(0.450.47

1 2 ==×+=+= Ax)(xB1t 2 .

2. After a window is opened in the oxide for a second oxidation, the rate constants are

B = 0.01 µm 2/hr, A= 0.116 µm (B/A = 6 ×10-2 µm /hr).

If the initial oxide thickness is 20 nm = 0.02 µm for dry oxidation, the value ofτcan be obtained

as followed:

(0.02)2 + 0.166(0.02) = 0.01 (0 +τ)

or

τ= 0.372 hr.

For an oxidation time of 20 min (=1/3 hr), the oxide thickness in the window area is

x2+ 0.166x = 0.01(0.333+0.372) = 0.007

or

x = 0.0350 µm = 35 nm (gate oxide).

For the field oxide with an original thickness 0.45 µm, the effectiveτis given by

τ= .hr 72.27)45.0166.045.0(01.01)(1 22 =×+=+ Axx

B

x2+ 0.166x = 0.01(0.333+27.72) = 0.28053

or x = 0.4530 µm (an increase of 0.003µm only for the field oxide).

3. x2 + Ax = B )( τ+t

)(4

)2

22 τ+=− tBAAx( +

++= )(

4 )

2

22 τt

BABAx +(

8

when t >> τ , t >> B

A4

2

,

then, x2 = Bt

similarly,

when t >> τ , t >> B

A4

2

,

then, x = )( τ+tAB

4. At 980(=1253K) and 1 atm, B = 8.5×10-3 µm 2/hr, B/A = 4×10-2 µm /hr (from Figs. 3.6 and 3.7).

Since A ≡2D/k , B/A = kC0/C1, C0 = 5.2×1016 molecules/cm3 and C1 = 2.2×1022 cm-3 , the diffusion

coefficient is given by

.s/cm104.79

hr/m101.79

hr/m 102.5102.2

2105.8

222

29-

23

216

223

0

1

0

1

×=

×=×××

=

=

⋅==

−

µ

µ

CCB

CC

ABAAkD

5. For impurity in the oxidation process of silicon,

segregatio =t coefficein n2SiO inimpurity of ionconcentrat mequilibriu

silicon inimpurity of ionconcentrat mequilibriu .

6. . 006.0500

3105103

13

11

==××

=κ

7. The SUPREM input file for the first oxidation step is:

TITLE Problem 3-7a

COMMENT Initialize silicon substrate

INITIALIZE <100> Silicon

COMMENT Oxidize the wafer for 60 minutes at 1100 C in dry O2

DIFFUSION Time=60 Temperature=1100 DryO2

PRINT Layers

STOP End Problem 3-7a

The result of the PRINT Layers command is:

9

layer material type thickness dx dxmin top bottom no. (microns) (microns) node node 2 OXIDE 0.1088 0.0100 0.0010 798 804 1 SILICON 1.9521 0.0100 0.0010 805 1000 This indicates an oxide thickness of 0.1088 µm, which means 0.44 * 0.1088 µm = 0.0479 µm of

silicon has been consumed during the process (i.e., the Si/SiO2 interface is 0.0479 µm below the

original Si surface). The figure below is a graphical representation.

For the half of the wafer, the oxide is removed, and the wafer is re-oxidized in wet O2. For this half,

we use the following SUPREM input file:

TITLE Problem 3-7b





COMMENT Remove the oxide

ETCH Oxide All

COMMENT Oxidize the wafer for 30 minutes at 1000 C in wet O2 DIFFUSION Time=30 Temperature=1000 WetO2 PRINT Layers

STOP End Problem 3-7b

The result of this PRINT Layers command is: layer material type thickness dx dxmin top bottom no. (microns) (microns) node node 2 OXIDE 0.2291 0.0100 0.0010 803 814 1 SILICON 1.8513 0.0100 0.0010 815 1000

This indicates a final oxide thickness of 0.2291 µm on the etched side, which means an additional 0.44 10

* 0.2291 µm = 0.1008 µm of silicon has been consumed during the process. The total distance from

the Si/SiO2 interface to the original Si surface on this side is therefore 0.0479 µm + 0.1008 µm =

0.1487 µm.

The unetched side is simulated using the SUPREM input file:

TITLE Problem 3-7c





COMMENT Oxidize the wafer for 30 minutes at 1000 C in wet O2 DIFFUSION Time=30 Temperature=1000 WetO2 PRINT Layers

STOP End Problem 3-7c

The result of this PRINT Layers command is: layer material type thickness dx dxmin top bottom

no. (microns) (microns) node node 2 OXIDE 0.2897 0.0100 0.0010 798 812 1 SILICON 1.8725 0.0100 0.0010 813 1000

On this side, a total of 0.44 * 0.2897 µm = 0.1275 µm of Si is consumed. The total distance from the

Si/SiO2 interface to the original Si surface on this side is 0.44 * 0.2987 µm = 0.1275 µm. The figure

below is a graphical representation of the final structure.

11

The step heights on the surface and in the substrate are 0.0818 µm and 0.0212 µm, respectively.

12

CHAPTER 4

1. With reference to Fig. 2 for class 100 clean room we have a total of 3500 particles/m3 with particle sizes 0.5 µm ≥

350010021

× = 735 particles/m2 with particle sizes ≥ 1.0 µm

3500100

5.4× = 157 particles/m2 with particle sizes ≥ 2.0 µm

Therefore, (a) 3500-735 = 2765 particles/m3 between 0.5 and 1 µm (b) 735-157 = 578 particles/m3 between 1 and 2 µm (c) 157 particles/m3 above 2 µm.

2. AD

neY 1

9

1

−

=Π=

A = 50 mm2 = 0.5 cm2 %1.302.1)5.01(1)5.025.0(4)5.01.0(4 ==××= −×−×−×− eeeeY .

3. The available exposure energy in an hour is

0.3 mW2/cm2 × 3600 s =1080 mJ/cm2

For positive resist, the throughput is

wafers/hr71401080

=

For negative resist, the throughput is

r wafers/h0129

1080= .

4. (a) The resolution of a projection system is given by

178.065.0

mμ193.06.01 =×==NA

klmλ µm

== 222 )65.0(

m193.05.0)(

µλNA

kDOF = 0.228 µm

(b) We can increase NA to improve the resolution. We can adopt resolution enhancement

techniques (RET) such as optical proximity correction (OPC) and phase-shifting Masks

(PSM). We can also develop new resists that provide lower k1 and higher k2 for better

13

resolution and depth of focus.

(c) PSM technique changes k1 to improve resolution.

5. (a) Using resists with high γ value can result in a more vertical profile but throughput decreases.

(b) Conventional resists can not be used in deep UV lithography process because these resists

have high absorption and require high dose to be exposed in deep UV. This raises the

concern of damage to stepper lens, lower exposure speed and reduced throughput.

6. (a) A shaped beam system enables the size and shape of the beam to be varied, thereby

minimizing the number of flashes required for exposing a given area to be patterned.

Therefore, a shaped beam can save time and increase throughput compared to a Gaussian

beam.

(b) We can make alignment marks on wafers using e-beam and etch the exposed marks. We can

then use them to do alignment with e-beam radiation and obtain the signal from these marks

for wafer alignment.

X-ray lithography is a proximity printing lithography. Its accuracy requirement is very high,

therefore alignment is difficult.

(c) X-ray lithography using synchrotron radiation has a high exposure flux so X-ray has better

throughput than e-beam.

7. (a) To avoid the mask damage problem associated with shadow printing, projection printing

exposure tools have been developed to project an image from the mask. With a 1:1

projection printing system is much more difficult to produce defect-free masks than it is with

a 5:1 reduction step-and-repeat system.

(b) It is not possible. The main reason is that X-rays cannot be focused by an optical lens. When

it is through the reticle. So we can not build a step-and-scan X-ray lithography system.

8. All of the above values can be entered from the Parameters menu or by clicking on the appropriate

14

icon on the toolbar. The resulting resist profile is shown in the figure below.

In comparison to Example 3, we see that no resist feature is printed under the modified process

conditions. The combination of the long pre-bake time and low exposure dose prevents the feature

from being defined.

15

CHAPTER 5

1. As shown in the figure, the profile for each case is a segment of a circle with origin at the

initial mask-film edge. As overetching proceeds the radius of curvature increases so that the

profile tends to a vertical line.

2. (a) 20 sec

0.6 × 20/60 = 0.2 µm…..(100) plane

0.6/16 × 20/60 = 0.0125 µm……..(110) plane

0.6/100 × 20/60 = 0.002 µm…….(111) plane

22.12.025.120 =×−=−= lWWb µm

(b) 40 sec

0.6 × 40/60 = 0.4 µm….(100)plane

0.6/16 × 40/60 = 0.025 µm…. (110) plane

0.6/100 × 40/60 = 0.004 µm…..(111) plane

4.025.120 ×−=−= lWWb = 0.93 µm

(c) 60 sec

0.6 ×1 = 0.6 µm….(100)plane

0.6/16 ×1 = 0.0375 µm…. (110) plane

0.6/100 ×1= 0.006 µm…..(111) plane

=×−=−= 6.025.120 lWWb 0.65 µm.

3. Using the data in Prob. 2, the etched pattern profiles on <100>-Si are shown in below.

(a) 20 sec l = 0.012 µm, W µm 5.10 == bW

16

(b) 40 sec l = 0.025 µm, W µm 5.10 == bW

(c) 60 sec l = 0.0375 µm W µm. 5.10 == bW

4. If we protect the IC chip areas (e.g. with Si3N4 layer) and etch the wafer from the top, the width of the bottom surface is

18846252100021 =×+=+= lWW µm

The fraction of surface area that is lost is

( × 100%=(1884221

2 /) WWW − 2-10002) /18842× 100% = 71.8 %

In terms of the wafer area, we have lost

71.8 % × =127 cm2)2/15(π 2

Another method is to define masking areas on the backside and etch from the back. The width of each square mask centered with respect of IC chip is given by

6252100021 ×−=−= lWW = 116 µm

Using this method, the fraction of the top surface area that is lost can be negligibly small.

5. 1 Pa = 7.52 m Torr

PV = nRT

7.52 /760 × 10-3 = n/V ×0.082 × 273

n/V = 4.42 × 10-7 mole/liter = 4.42 × 10-7 × 6.02 × 1023/1000 =2.7 ×1014 cm-3

mean–free–path

cm = 5× 10P/105 3−×=λ -3 ×1000/ 7.52 = 0.6649 cm = 6649 µm

150Pa = 1128 m Torr

PV = nRT 17

1128/ 760 × 10-3 = n/V × 0.082 × 273

n/V = 6.63 × 10-5 mole/liter = 6.63 ×10-5×6.02×1023/1000 = 4 × 1016 cm-3

mean-free-path

cm = 5× 10P/105 3−×=λ -3 ×1000/1128 = 0.0044 cm = 44 µm.

6. Si Etch Rate (nm/min) = 2.86 × 10-13 × RTE

F

a

eTn−

×× 21

= 2.86 × 10-13 ×3×1015× 298987.11048.2

21

3

)298( ××−

× e

= 224.7 nm/min.

7. SiO2 Etch Rate (nm/min) = 0.614× 10-13 ×3×1015× 298987.11076.3

21

3

)298( ××−

× e = 5.6 nm/min

Etch selectivity of SiO2 over Si = 025.07.224

6.5=

Or etch rate (SiO2)/etch rate (Si) = 025.086.2

614.0 298987.1)48.276.3(

=× ×+−

e .

8. A three–step process is required for polysilicon gate etching. Step 1 is a nonselective etch

process that is used to remove any native oxide on the polysilicon surface. Step 2 is a high

polysilicon etch rate process which etches polysilicon with an anisotropic etch profile. Step 3 is a

highly selective polysilicon to oxide process which usually has a low polysilicon etch rate.

9. If the etch rate can be controlled to within 10 %, the polysilicon may be etched 10 % longer or for

an equivalent thickness of 40 nm. The selectivity is therefore

40 nm/1 nm = 40.

10. Assuming a 30% overetching, and that the selectivity of Al over the photoresist maintains 3. The

minimum photoresist thickness required is

18

(1+ 30%) × 1 µm/3 = 0.433 µm = 433.3 nm.

11. e

e mqB

=ω

31

199

101.9106.11045.22 −

−

×××

=××Bπ

B = 8.75 × 10-2(tesla)

= 875 (gauss).

12. Traditional RIE generates low-density plasma (109 cm-3) with high ion energy.

ECR and ICP generate high-density plasma (1011 to 1012 cm-3) with low ion energy.

Advantages of ECR and ICP are low etch damage, low microloading, low

aspect-ratio dependent etching effect, and simple chemistry. However, ECR and

ICP systems are more complicated than traditional RIE systems.

13. The corrosion reaction requires the presence of moisture to proceed. Therefore, the

first line of defense in controlling corrosion is controlling humidity. Low humidity

is essential,. especially if copper containing alloys are being etched. Second is to

remove as much chlorine as possible from the wafers before the wafers are

exposed to air. Finally, gases such as CF4 and SF6 can be used for fluorine/chlorine

exchange reactions and polymeric encapsulation. Thus, Al-Cl bonds are replaced

by Al-F bonds. Whereas Al-Cl bonds will react with ambient moisture and start

the corrosion process , Al-F bonds are very stable and do not react. Furthermore,

fluorine will not catalyze any corrosion reactions.

19

CHAPTER 6

1. Ea(boron) = 3.46 eV, D0 = 0.76 cm2/sec

From Eq. 6, /scm10142.4122310614.8

46.3exp76.0)exp( 21550

−−

×=

××−

=−

=kTE

DD a

cm 1073.2180010142.4 615 −− ×=××== DtL

From Eq. 9,

××==

−620

1046.5 erfc108.1)

2(erfc)( x

LxCx sC

If ; x = 0.05 ×10320 /cmatoms 108.1)0(,0 ×== Cx -4, C(5× 10-6) = 3.6 × 1019

atoms/cm3; x = 0.075 ×10-4 , C(7.5×10-6) = 9.4 ×1018 atoms/cm3; x = 0.1×10-4,

C(10-5) = 1.8 × 1018 atoms/cm3;

x = 0.15× 10-4, C(1.5×10-5) = 1.8× 1016 atoms/cm3.

The m15.0)(erfc 2 1- µ==s

subj C

CDtx

Total amount of dopant introduced = Q(t)

= 141054.52×=LCsπ

atoms/cm2.

2. /scm1096.4132310614.8

46.3exp76.0exp 21450

−− ×=

××−

=

−

=kTE

DD a

From Eq. 15, 319 atoms/cm10342.2),0( ×===Dt

StCS πC

××=

= −5

19

10673.2erfc10342.2

2erfc)( x

LxCxC S

If x = 0, C(0) = 2.342 × 1019 atoms/cm3; x = 0.1×10-4, C(10-5) = 1.41×1019 atoms/cm3;

x = 0.2×10-4, C(2×10-5) = 6.79×1018 atoms/cm3; x = 0.3×10-4, C(3×10-5) = 2.65×1018

20

atoms/cm3;

x = 0.4×10-4, C(4×10-5) = 9.37×1017 atoms/cm3; x = 0.5×10-4, C(5×10-5) = 1.87×1017

atoms/cm3;

x = 0.6×10-4, C(6×10-5) = 3.51×1016 atoms/cm3; x = 0.7×10-4, C(7×10-5) = 7.03×1015

atoms/cm3;

x = 0.8×10-4, C(8×10-5) = 5.62×1014 atoms/cm3.

The m 72.0ln4 µπ

==DtC

SDtxB

j .

3.

××

×=× −

−

t13

81815

103.2410exp101101

t = 1573 s = 26 min

For the constant-total-dopant diffusion case, Eq. 15 gives Dt

SS π

=C

2131318 atoms/cm104.31573103.2101 ×=××××= −πS .

4. The process is called the ramping of a diffusion furnace. For the ramp-down situation, the

furnace temperature T is given by

T = T0 - rt

where T0 is the initial temperature and r is the linear ramp rate. The effective Dt product

during a ramp-down time of t1 is given by

dttDDtt

eff )()( 1

0 ∫=

In a typical diffusion process, ramping is carried out until the diffusivity is

negligibly small. Thus the upper limit t1 can be taken as infinity:

21

...)1(111

000

++≈−

=Trt

TrtTT

and

20

0200

000

00 exp)(...))(exp(exp...)1(expexpkT

trETD

kTtrE

kTE

DTrt

kTE

DkTEDD aaaaa

−≈

−−=

++

−=

−=

where D(T0) is the diffusion coefficient at T0. Substituting the above equation into the

expression for the effective Dt product gives

∫∞

=−

≈

0

20

020

0 )(exp)( )(a

aeff rE

kTTDdt

kTtrE

TDDt

Thus the ramp-down process results in an effective additional time equal to kT02/rEa at the

initial diffusion temperature T0.

For phosphorus diffusion in silicon at 1000°C, we have from Fig. 6.4:

D(T0) = D (1273 K) = 2× 10-14 cm2/s

sKr /417.060207731273

=×

−=

Ea = 3.66 eV

Therefore, the effective diffusion time for the ramp-down process is

min5.191)106.166.3(417.0

)1273(1038.119

2232

0 ≈=××

×=

−

−

srE

kT

a

.

5. For low-concentration drive-in diffusion, the diffusion is given by Gaussian distribution.

The surface concentration is then

==

kTE

tDS

DtStC a

2exp),0(

0ππ

22

tCt

kTE

DS

dtdC a ×−=

−

= 5.0

22exp

2/3

0π

or tdt

CdC

×−= 5.0

which means 1% change in diffusion time will induce 0.5% change in surface

concentration.

220 222

expkTE

CkTE

kTE

tDS

dTdC aaa −=

−

=

π

or TdT

TdT

TdT

kT

E

CdC a ×−=×

×××

××−=×

−=

−

−

9.1612731038.12

106.16.32 23

19

which means 1% change in diffusion temperature will cause 16.9% change in

surface concentration.

6. At 1100°C, ni = 6×1018 cm-3. Therefore, the doping profile for a surface concentration

of 4 × 1018 cm-3 is given by the “intrinsic” diffusion process:

=

DtxCtxC s 2

erfc),(

where Cs = 4× 1018 cm-3, t = 3 hr = 10800 s, and D = 5x10-14 cm2/s. The diffusion

length is then

m232.0cm1032.2 5 µ=×= −Dt

The distribution of arsenic is

××= −5

18

1064.4erfc104)( xxC

The junction depth can be obtained as follows

×

×= −51815

1064.4erfc10410 jx

xj = 1.2× 10-4 cm = 1.2 µm.

23

7. At 900°C, ni = 2× 1018 cm-3. For a surface concentration of 4×1018 cm-3, given by

the “extrinsic” diffusion process

/scm1077.31021048.45 216

18

1811731038.1

106.105.4

023

19

−××

××−−

×=××

×=×= −

−

enneDD

i

kTEa

nm 3.32cm1023.3108001077.36.16.1 616 =×=××== −−Dtx j .

8. Intrinsic diffusion is for dopant concentration lower than the intrinsic carrier

concentration ni at the diffusion temperature. Extrinsic diffusion is for dopant

concentration higher than ni.

9. The SUPREM input file for this problem is:

TITLE Problem 6-9


INITIALIZE Thickness = 5 <100> Silicon Phosphor Concentration=1e16

COMMENT Diffuse Boron

DIFFUSIONT ime=15 Temperature=850 Boron Solidsol

COMMENT Perform Drive-In

DIFFUSIONT ime=360 Temperature=1175

PRINT Layers Active Concentration Phosphorus Boron Net

PLOT Active Net Cmin=1e12

STOP End Problem 6-9

Note that the thickness of the structure has been increased to 5 µm (in the INITIALIZE

statement) to accommodate an anticipated deeper junction. The resulting plot is shown

below. The junction depth occurs at approximately 3.48 µm.

24


TITLE Problem 6-10


INITIALIZE Thickness = 5 <100> Silicon Phosphor Concentration=1e16

COMMENT Boron Predep

DIFFUSION ime=15 Temperature=850 Boron Solidsol

COMMENT Boron Drive-In

DIFFUSION Time=360 Temperature=1175

COMMENT Phosphorus Predep

DIFFUSION Time=30 Temperature=850 Phosphor Solidsol

COMMENT Phosphorus Drive-In


PRINT Layers Active Concentration Phosphorus Boron Net

PLOT Active Net Cmin=1e13

25

STOP End Problem 6-10

The resulting plot is shown below. There are 2 pn junctions formed. The junction

depths occur at approximately 0.45 and 3.49 µm, respectively.

26

CHAPTER 7

1. The ion dose per unit area is

212

2

19

6

ions/cm 1038.2)

210(

106.16051010

×=×

××××

==−

−

πAqIt

AN

From Eq. 1 and Example 1, the peak ion concentration is at x = Rp. Figure 7.6

indicates the σp is 20 nm.

Therefore, the ion concentration is

3177

12

cm1074.421020

1038.22

−−

×=×

×=

ππσ p

S .

2. From Fig. 7.6, the Rp = 230 nm, and σp = 62 nm.

The peak concentration is

3207

15

cm1029.121062

1022

−−

×=×

×=

ππσ p

S

From Eq. 1,

−−×= 2

22015

2

)(exp1029.110

p

pj Rx

σ

xj = 0.53 µm.

3. Dose per unit area = 211198

140 cm106.8

106.11025011085.89.3 −−−

−

×=×××

×××=

∆=

qVC

qQ T

From Fig. 7.6 and Example 1, the peak concentration occurs at 140 nm from the

surface. Also, it is at (140-25) = 115 nm from the Si-SiO2 interface.

27

4. The total implanted dose is integrated from Eq. 1

∫∞

×=−=

−+=

−−=

0 2

2

9989.12

)]3.2(erfc2[2

)2

(erfc1122

)(exp

2SSRSdx

RxSQp

p

p

p

pT σσπσ

The total dose in silicon is as follows (d = 25 nm):

8991.12

)]87.1(erfc2[2

)2

(erfc1122

)(exp

2

2

2

∫∞

×=−=

−−+=

−−=

dp

p

p

p

pSi

SSdRSdxRxSQ

σσπσ

the ratio of dose in the silicon = QSi/QT = 99.6%.

5. The projected range is 150 nm (see Fig. 7.6).

The average nuclear energy loss over the range is 60 eV/nm (Fig. 7.5).

60× 0.25 = 15 eV (energy loss of boron ion per each lattice plane)

the damage volume = VD = π (2.5 nm)2(150 nm) = 3× 10-18 cm3

total damage layer = 150/0.25 = 600

displaced atom for one layer = 15/15 = 1

damage density = 600/VD = 2×1020 cm-3

2×1020/5.02×1022 = 0.4%.

6. The higher the temperature, the faster defects anneal out. Also, the solubility of

electrically active dopant atoms increases with temperature.

7. ox

t CQ

V 1V 1 ==∆

where Q1 is the additional charge added just below the oxide-semiconductor surface by ion implantation. COX is a parallel-plate capacitance per unit area

given by d

C sox

ε=

(d is the oxide thickness, sε is the permittivity of the semiconductor)

28

cm104.0

F/cm1085.89.31V6

14

1 −

−

××××

=∆= oxtCVQ = 8.63 27

cmC10−×

19

7

106.11063.8

−

−

×× = 5.4 ×1012 ions/cm2

Total implant dose = %45104.5 12× = 1.2 × 1013 ions/cm2.

8. The discussion should mention much of Section 7.3. Diffusion from a surface film

avoids problems of channeling. Tilted beams cannot be used because of

shadowing problems. If low energy implantation is used, perhaps with

preamorphization by silicon, then to keep the junctions shallow, RTA is also

necessary.

9. From Eq.11

84.022.0

6.04.0erfc21

=

−=

SSd

The effectiveness of the photoresist mask is only 16%.

023.022.06.01erfc

21

=

−=

SSd

The effectiveness of the photoresist mask is 97.7%.

10. 510 2

1 −==u

e2-u

πT

02.3=∴u

d = Rp + 4.27 pσ = 0.53 + 4.27 × 0.093 = 0.927 µm

29


TITLE Problem 7-11 COMMENT Initialize silicon substrate INITIALIZE <100> Silicon Phosphor Concentration=1e14 COMMENT Implant Boron IMPLANT Boron Energy=30 Dose=1e13 PRINT Layers Active Concentration Phosphorus Boron Net PLOT Active Net Cmin=1e11 STOP End Problem 7-11

The resulting doping profile is shown in the figure below.

Examining this figure and the SUPREM output file gives: (a) The peak of the implanted boron occurs at a depth of 0.11 µm. (b) The boron concentration at the peak is 8.59e17 cm-3. (c) The junction depth is 0.4492 µm.

30

12. The SUPREM input parameters that must be determined are the dose and

implant energy. The dose can be determined from Eq. 11 in Chapter 6 as

DtCtQ s13.1)( ≅

where Cs can be read directly from the SUPREM output file for Example 3 in

Chapter 6 as 4.6e19 cm-3, 163.2 −≈ eD cm2/s for boron at 850 oC (see Figure

6.4), and t = 900 s. Substituting these numbers into the above expression gives

a dose of 2.36e13 cm-2.

The implant energy required can be approximated by matching the diffused

and implanted concentration profiles at the surface (x = 0) and at the junction

and using Eq. 1 to solve for Rp and σp simultaneously. Note from the

SUPREM output file corresponding to Example 3 in Chapter 6 that the

junction occurs at xj = 0.0555 µm, at which point the doping concentration is

1016 cm-3. As stated before, the surface concentration is 4.6e19 cm-3.

These equations cannot be solved analytically, but after several iterations, the

approximate values of Rp and σp required are found to be 0.011 µm and 0.008

µm, respectively. These values correspond to an implant energy of 5 keV

(extrapolating from Figure 7.6a). The require SUPREM input file is therefore:

TITLE Problem 7-12 COMMENT Initialize silicon substrate INITIALIZE <100> Silicon Phosphor Concentration=1e16 COMMENT Implant Boron IMPLANT Boron Energy=5 Dose=2.36e13 PRINT Layers Active Concentration Phosphorus Boron Net PLOT Active Net Cmin=1e11 STOP End Problem 7-12

The resulting doping profile appears in the figure below.

31

CHAPTER 8

1. MkT

dvf

dvvf

v

v

av πν 8

0

0 ==∫∫

∞

∞

Where

−

=

kTM

kTMf

2exp

24 2

22/3 νν

πν

M: Molecular mass

k: Boltzmann constant = 1.38×10-23 J/k

T: The absolute temperature

ν: Speed of molecular

So that

cm/sec1068.4m/sec 4681067.129

3001038.122 427

23

×==××

×××= −

−

πν av .

2. cm)Pain (

66.0P

=λ

Pa 104.4150

66.066.0 3−×===∴λ

P .

3. For close-packing arrange, there are 3 pie shaped sections in the equilateral

triangle. Each section corresponds to 1/6 of an atom. Therefore

dd

N s

23

21

613

triangle theof area trianglein the contained atoms ofnumber

×

×==

=282 )1068.4(3

232

−×=

d

= . 214 atoms/cm 1027.5 ×

33

dd

4. (a) The pressure at 970°C (=1243K) is 2.9×10-1 Pa for Ga and 13 Pa for As2. The

arrival rate is given by the product of the impringement rate and A/πL2 :

Arrival rate = 2.64×1020

2L

AMTP

π

= 2.64×1020

×

×

× −

2

1

125

124372.69109.2

π

= 2.9×1015 Ga molecules/cm2 –s

The growth rate is determined by the Ga arrival rate and is given by

(2.9×1015)×2.8/(6×1014) = 13.5 Å/s = 810 Å/min .

(b) The pressure at 700ºC for tin is 2.66×10-6 Pa. The molecular weight is 118.69.

Therefore the arrival rate is

s⋅×=

×

××

×−

2102

620 cmmolecular/ 1028.2

125

97369.1181066.21064.2

π

If Sn atoms are fully incorporated and active in the Ga sublattice of GaAs, we

have an electron concentration of

. cm 1074.12

1042.4109.21028.2 3-17

22

15

10

×=

×

××

5. The x value is about 0.25, which is obtained from Fig. 8.7.

34

6. The lattice constants for InAs, GaAs, Si and Ge are 6.05, 5.65,5.43, and 5.65 Å,

respectively. Therefore, the f value for InAs-GaAs system is

066.005.6)05.665.5( −=−=f

And for Ge-Si system is

. 39.065.5)65.543.5( −=−=f

7. (a) For SiNxHy

2.11NSi

==x

∴ x = 0.83

atomic % 2083.01

100=

++ yyH =

∴ y = 0.46

The empirical formula is SiN0.83H0.46.

(b) ρ= 5× 1028e-33.3×1.2 = 2× 1011 Ω-cm

As the Si/N ratio increases, the resistivity decreases exponentially.

8. Set Ta2O5 thickness = 3t, ε1 = 25

SiO2 thickness = t, ε2 = 3.9 Si3N4 thickness = t, ε3 = 7.6, area = A then

tA

3C 01

OTa 52

εε=

AAA 020302ONO

tttC

1εεεεεε

++=

( )tA

32

032ONO 2

Cεε

εεε+

=

( ) ( ) 37.56.79.33

6.729.3253

2C 32

321

ONO

OTa 52 =××

×+=

+=

εεεεε

. C

35

9. Set BST thickness = 3t, ε1 = 500, area = A1 SiO2 thickness = t, ε2 = 3.9, area = A2 Si3N4 thickness = t, ε3 = 7.6, area = A2 then

( )tA

tA

32

2032101

23 εεεεεεε

+=

.0093.0AA

2

1 =

10. Let

Ta2O5 thickness = 3t, ε1 = 25 SiO2 thickness = t, ε2 = 3.9 Si3N4 thickness = t, ε3 = 7.6 area = A then

dA

tA 0201

3εεεε

=

.468.03

1

2 tt

d ==εε

36

11. The deposition rate can be expressed as

r = r0 exp (-Ea/kT)

where Ea = 0.6 eV for silane-oxygen reaction. Therefore for T1 = 698 K

−== 116.0 exp2

)()(

211

2

kTkTTrTr

ln 2 =

− 300

698300

0259.06.

2T0

4 T2 =1030 K= 757 .

12. We can use energy-enhanced CVD methods such as using a focused energy

source or UV lamp. Another method is to use boron doped P-glass which will

reflow at temperatures less than 900 .

13. Moderately low temperatures are usually used for polysilicon deposition, and

silane decomposition occurs at lower temperatures than that for chloride reactions.

In addition, silane is used for better coverage over amorphous materials such

SiO2.

14. There are two reasons. One is to minimize the thermal budget of the wafer,

reducing dopant diffusion and material degradation. In addition, fewer gas phase

reactions occur at lower temperatures, resulting in smoother and better adhering

films. Another reason is that the polysilicon will have small grains. The finer

grains are easier to mask and etch to give smooth and uniform edges. However,

for temperatures less than 575 ºC the deposition rate is too low.

15. The flat-band voltage shift is

FBV∆ = 0.5 V ~ 0C

Qot

288

14

0 F/cm109.610500

1085.89.3 −−−

−

×=×

××==

dC oxε

.

∴ Number of fixed oxide charge is

37

2-1119

80 cm101.2

106.1109.65.05.0

×=×

××=

−

−

qC

To remove these charges, a 450 heat treatment in hydrogen for about 30

minutes is required.

16. 20/0.25 = 80 sqs.

Therefore, the resistance of the metal line is

5×50 = 400 Ω .

17. For TiSi2

30 × 2.37 = 71.1nm For CoSi2

30 × 3.56 = 106.8nm.

18. For TiSi2:

Advantage: low resistivity

It can reduce native-oxide layers

TiSi2 on the gate electrode is more resistant to

high-field-induced hot-electron degradation.

Disadvantage: bridging effect occurs.

Larger Si consumption during formation of TiSi2

Less thermal stability

For CoSi2:

Advantage: low resistivity

High temperature stability

No bridging effect

A selective chemical etch exits

Low shear forces

Disadvantage: not a good candidate for polycides

38

Ω×=×××

××==−−

− 344

6 102.3103.01028.0

11067.2ALρR19. (a)

F..

...STL

dAC 13

4

64414

109210360

1010110301085893 −−

−−−

×=×

×××××××===

εε

ns 93.0109.2103.2 155 =×××= − RC

(b) Ω×=×××

××==−−

− 344

6 102103.01028.0

1107.1LA

R ρ

F101.21036.0

1103.01085.88.2dA 13

4

414−

−

−−

×=×

×××××===

SC εε

TL

ns 42.0101.2102 133 =×××= −RC

(c) We can decrease the RC delay by 55%. Ratio = 093

42.0 = 0.45.

××× 44 103.01028.0AR ρ Ω×=××== − 36 102.311067.2L20. (a)

F107.81036.0

31103.01085.89.3 134

414−

−−

×=×

××××××===

STL

dAC εε

RC = 3.2 ×103 ×8.7 × 10-13 = 2.8 ns.

.

(b) Ω×=×××

××== − 344

6 102103.01028.0

1107.1ALR ρ

F103.61036.0

31103.01085.88.2d

134

414−

−−

×=×

××××××===

STLAC εε

ns. 5.2107.8102.3

ns 5.2107.810133

133

=×××=

=×××−

−

RCRC 2=

21. (a) The aluminum runner can be considered as two segments connected in

series: 20% (or 0.4 mm) of the length is half thickness (0.5 µm) and the

remaining 1.6 mm is full thickness (1µm). The total resistance is

××

+×

×=

+=

−−−−−

)105.0(1004.0

101016.0103 4444

6

2

2

1

1

AAR ρ

39

= 72 Ω.

The limiting current I is given by the maximum allowed current density times

cross-sectional area of the thinner conductor sections:

I = 5×105 A/cm2× (10-4×0.5×10-4) = 2.5×10-3 A = 2.5 mA.

The voltage drop across the whole conductor is then

V = 0.18V. A 105.272 3−××Ω== RI

22.

=

0.5 µ m

0.5 µm

Cu 40 nm

Al 60 nm

h: height , W : width , t : thickness, assume that the resistivities of the cladding

layer and TiN are much larger than CuA and ρρ

5.0)1.05.0(

7.2×−

=×

×=Wh

R AlAl ρ

)25.0()25.0(

7.1ttWh

R CuCu −×−=

××= ρ

When R = CuAl R

Then 2)25.0(7.1

5.04.07.

t−=

×2

⇒ t = 0.073 µm = 73 nm .

40

CHAPTER 9

1. Each U-shape section (refer to the figure) has an area of 2500 µm × 8 µm = 2 × 104

µm2. Therefore, there are (2500)2/2 ×104 = 312.5 U-shaped section. Each section

contains 2 long lines with 1248 squares each, 4 corner squares, 1 bottom square,

and 2 half squares at the top. Therefore the resistance for each section is

1 kΩ / (1248×2 + 4×0.65 +2) = 2500.6 kΩ

The maximum resistance is then

312.5×2500.6 = 7.81 × 108 Ω = 781 MΩ

2. The area required on the chip is

41

2514

127

cm 1035.41085.89.3

)105)(1030( −−

−−

×=××××

==ox

dC

Aε

= 4.35 × 103 µm2 = 66 × 66 µm

Refer to Fig.9.4a and using negative photoresist of all levels

(a) Ion implantation mask (for p+ implantation and gate oxide)

(b) Contact windows (2×10 µm)

(c) Metallization mask (using Al to form ohmic contact in the contact window and

form the MOS capacitor).

Because of the registration errors, an additional 2 µm is incorporated in all critical

dimensions.

42

3. If the space between lines is 2 µm, then there is 4 µm for each turn (i.e., 2×n, for one

turn). Assume there are n turns, from Eq.6, L ≈ µ0n2r ≈ 1.2 × 10-6n2r, where r can be

replaced by 2 × n. Then, we can obtain that n is 13.

43

4. (a) Metal 1, (b) contact hole, (c) Metal 2.

(a) Metal 1,

(b) contact hole,

(c) Metal 2.

44

5. The circuit diagram and device cross-section of a clamped transistor are shown in (a)

and (b), respectively.

6. (a) The undoped polysilicon is used for isolation.

(b) The polysilicon 1 is used as a solid-phase diffusion source to form the

extrinsic base region and the base electrode.

(c) The polysilicon 2 is used as a solid-phase diffusion source to form the emitter region

and the emitter electrode.

7. (a) For 30 keV boron, Rp = 100 nm and ∆Rp = 34 nm. Assuming that Rp and ∆Rp for

45

boron are the same in Si and SiO2 the peak concentration is given by

3167

11

cm 104.9)1034(2

1082

−−

×=×

×=

∆ ππ pRS

The amount of boron ions in the silicon is

( )

211

11

2

2

cm1088.7

3402750erfc2

2108

2erfc2

2

2exp

2

−

∞

×=

×

−×

=

∆

−−=

∆

−−

∆= ∫

p

p

dp

p

p

R

dRS

dxRRx

RS

qQ

π

Assume that the implanted boron ions form a negative sheet charge near the Si-SiO2

interface, then

( ) 91.01025/1085.89.3

)1088.7(106.1/ 714

1119

=×××

×××=

=∆

−−

−

oxT CqQqV V

(b) For 80 keV arsenic implantation, Rp = 49 nm and ∆ Rp = 18 nm. The peak arsenic

concentration is 3217

16

cm 1021.2)1018(

102

−

−×=

××=

∆ ππ pRS .

46

8. (a) Because (100)-oriented silicon has lower (~ one tenth) interface-trapped charge and a

lower fixed oxide charge.

(b) If the field oxide is too thin, it may not provide a large enough threshold

voltage for adequate isolation between neighboring MOSFETs.

(c) The typical sheet resistance of heavily doped polysilicon gate is 20 to

30 Ω /, which is adequate for MOSFETs with gate lengths larger than 3 µm. For

shorter gates, the sheet resistance of polysilicon is too high and will cause large RC

47

delays. We can use refractory metals (e.g., Mo) or silicides as the gate material to

reduce the sheet resistance to about 1 Ω /.

(d) A self-aligned gate can be obtained by first defining the MOS gate structure, then

using the gate electrode as a mask for the source/drain implantation. The

self-aligned gate can minimize parasitic capacitance caused by the source/drain

regions extending underneath the gate electrode (due to diffusion or

misalignment).

(e) P-glass can be used for insulation between conducting layers, for diffusion and

ion implantation masks, and for passivation to protect devices from impurities,

moisture, and scratches.

9. The lower insulator has a dielectric constant ε1/ε0 = 4 and a thickness d1= 10 nm The

upper insulator has a dielectric constant ε2/ε0 = 10 and a thickness d2 = 100 nm. Upon

application of a positive voltage VG to the external gate, electric field E1 and E2 are

established in the d1 and d2 respectively. We have, from Gauss’ law, that ε1E1 = ε2E2 +Q

and VG = E1d1 + E2d2

where Q is the stored charge on the floating gate. From these above two equations, we

obtain

( ) ( )212121211 // dd

QddVG

εεεε ++

+=E

48

QQJ 5

14

77

1 1026.22.01085.8

10010104

10410010

101010 ×−=

××

+

+

+

×==

−

−Eσ

(a) If the stored charge does not reduce E1 by a significant amount (i.e., 0.2 >> 2.26×105 Q,

we can write

Q ( )∫ −− ×=××=∆≈=

0

861 1051025.02.02.0'

tCtdtEσ

( ) ( ) 565.010100/1085.810

105714

8

2

=×××

×== −−

−

CQVT∆ V

(b) when t we have 0, →∞→ J ≅×→ 51026.2/2.0Q 8.84×10-7 C.

Then ( ) 98.910/1085.810

1084.8514

7

2

=×××

==∆ −−

−

CQVT V.

10.

49

11. The oxide capacitance per unit area is given by

7105.32 −×==d

CSiO

ox

εF/cm2

and the maximum current supplied by the device is

( ) ( ) 5105.35.0

521

21 272 ≈−×=−≈ −

TGTGoxDS VVm

mVVCL

WIµ

µµ mA

51

and the maximum allowable wire resistance is 0.1 V/5 mA, or 20Ω. Then, the

length of the wire must be

074.0cm107.2

cm10208

28

=−Ω×

×Ω=

×≤ −

−

ρAreaRL cm

or 740 µm. This is a long distance compared to most device spacing. When

driving signals between widely spaced logic blocks however, minimum feature

sized lines would not be appropriate.

12.

52

13. To solve the short-channel effect of devices.

14. The device performance will be degraded from the boron penetration. There are

53

methods to reduce this effect: (1) using rapid thermal annealing to reduce the time

at high temperatures, consequently reduces the diffusion of boron, (2) using

nitrided oxide to suppress the boron penetration, since boron can easily combine

with nitrogen and becomes less mobile, (3) making a multi-layer of polysilicon to

trap the boron atoms at the interface of each layer.

15. Total capacitance of the stacked gate structure is :

C =

+×=

+×

1025

5.07

1025

5.07

2

2

1

1

2

2

1

1

ddddεεεε

= 2.12

d9.3

= 2.12

12.29.3

=∴d =1.84 nm.

16. Disadvantages of LOCOS: (1) high temperature and long oxidation time cause VT

shift, (2) bird’s beak, (3) not a planar surface, (4) exhibits oxide thinning effect.

Advantages of shallow trench isolation: (1) planar surface, (2) no high

temperature processing and long oxidation time, (3) no oxide thinning effect, (4)

no bird’s beak.

17. For isolation between the metal and the substrate.

18. GaAs lacks of high-quality insulating film.

19. Answers will vary. If we ignore the contributions of isolation region processing, the

structure can be simulated using four SUPREM input decks. The first deck simulates

54

processing in the active region of the device, up to the point of the isolation oxidation.

The second deck starts with the results from the first deck and completes all processing

in the active regions. This allows the doping profile through the emitter to be plotted

(for part b). The third deck is similar to the second, except it eliminates the emitter

implant and facilitates plotting of the doping profile through the base region (for part a).

The final deck is also similar to the second, except that it eliminates the base implant

and facilitates plotting the doping profile through the collector region (for part c). The

complete process sequence is as follows:

1) Begin with a high-resistivity, <100>, p-type silicon substrate.

2) Grow a 1 µm SiO2 layer.

3) Remove the oxide in the areas where the buried layers are to be placed.

4) Implant antimony at a dose of 1e15 cm-2. Drive in the buried layer for 5 hours at

1150 oC.

5) Etch the silicon dioxide from the surface.

6) Grow a 1.6 µm arsenic-doped epitaxial layer.

7) Grow a 400 Å pad oxide.

8) Deposit 800 Å of silicon nitride.

9) Etch the oxide and nitride from the isolation regions.

10) Etch the silicon halfway through the epi-layer.

55

11) Implant boron in the field regions with a dose of 1e13 cm-2 at an energy of 50

keV.

12) Oxidize the field regions to a thickness approximately one-half that of the

epi-layer.

13) Implant the base region with boron at a dose of 1e14 cm-2 at an energy of 50

keV.

14) Etch the oxide from the emitter region.

15) Implant emitter collector contact regions with arsenic at a dose of 5e15 cm-2 at

an energy of 100 keV.

16) Drive-in the arsenic and activate the base diffusion.

The SUPREM input decks are as follows:

TITLE BJT – Deck 1

COMMENT Initial Active Region Processing


INITIALIZE <100> Silicon Boron Concentration=5e14

COMMENT Grow masking oxide for non-active regions

DIFFUSION Time=100 Temperature=1150 WetO2

COMMENT Etch oxide over buried layer regions

ETCH Oxide

COMMENT Implant and drive-in antimony buried layer

IMPLANT Antimony Dose=5e14 Energy=120



COMMENT Etch the oxide

ETCH Oxide

COMMENT Grow 1.6 µm of arsenic-doped epi

EPITAXY Temperature=1050 Time=4 Growth.Rate=0.4 Arsenic Gas.Conc=5e15

56

COMMENT Grow 400 A pad oxide


COMMENT Deposit nitride to mask the field oxidation

DEPOSITION Nitride Thickness=0.08

SAVEFILE Structur Filename=bjtactiveinit.str

STOP End BJT 1


COMMENT Final Active Region Processing for Emitter Profile

COMMENT Start with previous results

INITIALIZE Structur=bjtactiveinit.str

COMMENT Field oxide growth

DIFFUSION Time=30 Temperature=800 t.rate=10


DIFFUSION Time=210 Temperature=1100 Wet02


DIFFUSION Time=10 Temperature=1100 t.rate=-30

COMMENT Etch the oxide and nitride layers

ETCH Oxide

ETCH Nitride

ETCH Oxide

COMMENT Implant boron base

IMPLANT Boron Dose=1e14 Energy=50

COMMENT Remove oxide from emitter region

ETCH Oxide

COMMENT Implant arsenic emitter and collector contacts

IMPLANT Arsenic Dose=5e15 Energy=100

COMMENT Drive-in emitter and collector contact regions


PRINT Layers

PLOT Chemical Boron Arsenic Phosphor Net

STOP End BJT 2


COMMENT Active Region Processing for Base Profile


57









ETCH Oxide

ETCH Nitride

ETCH Oxide

COMMENT Implant boron base



ETCH Oxide

COMMENT Drive-in emitter and collector contact region


PRINT Layers


STOP End BJT 3


COMMENT Active Region Processing for Collector Profile










ETCH Oxide

ETCH Nitride

ETCH Oxide


ETCH Oxide

58

COMMENT Implant arsenic emitter and collector contacts

IMPLANT Arsenic Dose=5e15 Energy=100

COMMENT Drive-in emitter and collector contact regions


PRINT Layers


STOP End BJT 4

The resulting doping profiles though the base, emitter, and collector (parts a, b, and c),

respectively, are shown in the following three figures:

(a)

59

(b)

60

(c)

20. Answers will vary. For the sake of simplicity, we will ignore isolation-related

processing. The structure can be simulated using four SUPREM input decks (one for

each requested profile). The complete process sequence is as follows:

61

1) Start with a <100>, n-type silicon substrate.

2) Grow a 0.9 µm SiO2 layer.

3) Remove the oxide in the p-well areas.

4) Implant boron well at a dose of 5e14 cm-2 at 50 keV.

5) Drive in the p-well for 6 hours at 1150 oC.

6) Remove oxide in PMOS source/drain regions.

7) Implant boron for PMOS source/drain at a dose of 1e14 cm-2 at 20 keV.

8) Drive in the PMOS source/drain regions for 2.5 hours at 1100 oC.

9) Etch oxide in NMOS source/drain regions.

10) Implant phosphorus for NMOS source/drain at a dose of 1e14 cm-2 at 20 keV.

11) Drive in the NMOS source/drain regions for 2.5 hours at 1100 oC.

12) Etch oxide in gate areas.

13) Grow 500 Å gate oxide.

14) Deposit and pattern polysilicon gates.

15) Grow passivation oxide.

16) Deposit and pattern metallization.

The SUPREM input decks are and corresponding outputs as follows:

TITLE CMOS – Deck 1

COMMENT PMOS source/drain


INITIALIZE <100> Silicon Phosphorus Concentration=5e15 Thickness=5

62

COMMENT Grow field oxide


COMMENT Etch oxide after p-well implant

ETCH Oxide

COMMENT P-well drive-in


COMMENT Etch the oxide prior to PMOS source/drain implant

ETCH Oxide

COMMENT PMOS source/drain implant


COMMENT PMOS source/drain drive-in


COMMENT NMOS source/drain drive-in and gate oxidation


COMMENT Etch oxide

ETCH Oxide

COMMENT Deposit metal

DEPOSITION Aluminum Thickness=1.0

PRINT Layers

PLOT Chemical Boron Phosphor Net

STOP End CMOS 1

63

(a)


COMMENT PMOS Gate





COMMENT Etch oxide after p-well implant

ETCH Oxide



64

COMMENT Etch the oxide prior to PMOS source/drain implant

ETCH Oxide





COMMENT Deposit polysilicon

DEPOSITION Polysilicon Thickness=0.5

COMMENT Grow passivation oxide


PRINT Layers


STOP End CMOS 2

65

(b)


COMMENT NMOS source/drain





COMMENT Etch oxide in p-well region

ETCH Oxide

COMMENT P-well implant

66






COMMENT Etch the oxide prior to NMOS source/drain implant

ETCH Oxide

COMMENT NMOS source/drain implant

IMPLANT Phosphorus Dose=1e14 Energy=20



COMMENT Etch oxide

ETCH Oxide

COMMENT Deposit metal

DEPOSITION Aluminum Thickness=1.0

PRINT Layers


STOP End CMOS 3

67

(c)


COMMENT NMOS gate





COMMENT Etch oxide in p-well region

ETCH Oxide

68

COMMENT P-well implant






COMMENT Etch the oxide prior to NMOS source/drain implant

ETCH Oxide



COMMENT Deposit polysilicon

DEPOSITION Polysilicon Thickness=0.5

COMMENT Grow passivation oxide


PRINT Layers


STOP End CMOS 4

69

(d)

70

CHAPTER 10

1. x -chart: Center = µ = 0.75 V

UCL =10

)1.0(375.03+=+

nσµ = 0.845 V

LCL = 3-nσ3 = 0.655 V

s-chart: Center = s = c4σ = 0.9727(0.1) = 0.0973 V

UCL = s + 3 21

24 )9727.01)(1.0(3973.01 −+=− cσ = 0.167 V

LCL = s - 3 241 c−σ = 0.028 V

2. x -chart: Center = x = 0.734 V

UCL =nc

s

4

3x + = 0.846 V

LCL = nc

s

4

3x − = 0.622 V

s-chart: Center = s = 0.125 V

UCL = 24

4

13 ccss −+ = 0.215 V

LCL = 24

4

13 ccss −− = 0.036 V

3. Let ED = exposure dose, DT = develop time, BT = bake temperature

ED DT BT Y (1) (2) (3) Div. Eff. ID - - - 60 137 264 534 8 66.75 Avg.

71

+ - - 77 127 270 92 4 23 ED - + - 59 140 26 -20 4 -5 DT + + - 68 130 66 6 4 1.5 ED x DT - - + 57 17 -10 6 4 1.5 BT + - + 83 9 -10 40 4 10 ED x BT - + + 45 26 -8 0 4 0 DT x BT + + + 85 40 14 22 4 5.5 ED x DT x BT 4. Let: days = blocks (i.e., n = 3)

processes = treatments (i.e., k = 5)

Then we have: A B C D E iy Day 1 509 512 532 506 509 513.6 Day 2 505 507 542 520 519 518.6 Day 3 465 472 498 483 475 478.6

ty 493 497 524 503 501 y = 503.6

ANOVA Table: Source Sum of Squares Degrees of Freedom Mean Square Average (SA) 3,804,194.4 1 3,804,194.4 Blocks (SB) 4,750 2 2,375 ( ) 2

BsTreatments (ST) 1,737.6 4 434.4 ( ) 2

TsResidual (SR) 210 8 26.25 ( ) 2

Rs

where: 2ynkSA = = 3,804,194.4

(2

1∑

=

−=n

iiB yykS ) , DF = n – 1

(2

1∑

=

−=k

ttT yynS ) , DF = k – 1

(2

1 1∑∑

= =

+−−k

t

n

ititiR yyyyS ) , DF = (n – 1)(k – 1)

Now: = 90.48 22 / RB ss

72

= 16.55 22 / RT ss

A. Significance level for the null hypothesis that the blocks are the same is very

low, since

P( F ~0 )48.908,2 >

B. The same is true for the hypothesis that the treatments are the same, since:

P 0~)55.16( 8,4 >F

I. The processes are significantly different. II. The processing dates have significant differences.

5. From Eq. 33: Y = exp(-AcD0)N = exp(-NAcD0)

where: Y = 0.95 N = 100,000 Ac = WL = (10e-4 cm)(1e-4 cm) = 1e-7 cm2

=> cNAYD ln−

= = 5.13 cm-2

6. Murphy’s Yield Integral (Eq. 34): Y dDDfe DAc )(0∫∞

−=

Uniform defect distribution: 02/1)( DDf = for 020 DD ≤≤

00

2

00

2

0 0 21

2

D

c

DAD DA

Ae

DdD

De cc

−==

−−

∫Y

=> c

AD

uniform ADe c

0

2

21 0−−

=Y

Triangular defect distribution: for 20/)( DDDf = 00 DD ≤≤

0

20

2DD

D+−= for 00 2DDD ≤≤

73

dDDD

DedDDDe

D

D

DAD

DA cc

+−+= ∫∫ −−

020

2

200

20

0

0

Y

( ) ( )0

0

0

0

0

2

0

222

0022

0

21111D

Dc

DAD

Dcc

DAD

cc

AD

Ae

DDA

Ae

DDA

Ae

D

cc

−+−−−−−=

−−−

Y

=> 2

0

01

−=

−

c

AD

triangular ADe c

Y

Exponential Defect Distribution:

−=

00

exp1)(D

DD

Df

∞∞∞−−

+−+

=

+−== ∫∫

00

0

00 0

0

00

/

0

)1(exp1

1)1(exp110

DDAD

DAdD

DDAD

DdDee

DY c

c

cDDDAc

=> c

onential ADY

0exp 1

1+

=

7. Use Murphy’s Yield Integral (Eq. 34):

dDDfeY AD )(∫ −= , where: A = 100cm2, f(D) = -100D+10

( )dDDeY D 101001.0

05.0

100 +−= ∫ −

= -100 dDedDDe DD ∫∫ −− +1.0

05.0

1001.0

05.0

100 10

= ( ) 1.0

05.0

1001.0

05.0100

4 100101

10100 DD eADe −− −−

−

=> Y = 0.094 %

74

CHAPTER 11

1. (a)

( )

( ) ns. 38.11038.11003.692000

105.010111085.89.3

105.01110

914

4

414

85

=×=××=

×××

×××

×××=

=

−−

−

−−

−−

s

dA

ALRC oxερ

(b) For a polysilicon runner

( )ns 207

s 1007.21003.6910

130 7144

=

×=×

=

=

−−−

dA

WLRRC oxsquare ε

Therefore the polysilicon runner’s RC time constant is 150 times larger than the

aluminum runner.

2. When we combine the logic circuits and memory on the chip, we need multiple

supply voltages. For reliability issue, different oxide thicknesses are needed for

different supply voltages.

3. (a) nitrideOTatotal

11152

CCC +=

hence 3.17710

2575

9.3 =+=EOT Å

(b) EOT = 16.7 Å.

75

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