ISSCC 2007/1 SESSION 6 1 UWB anid mm-nWAVE COMMUNICATIONS SYSTEMS / 6.7

6.7 A Fully Integrated 24GHz 4-Channel Phased-Array in the PLL loop bandwidth, the strength of this downconvertedTransceiver in 0.13pm CMOS Based on a Variable- siI-NAO-AOPhase Ring Oscillator and PLL Architecture signal at V,tri is 2 where co is the PLL oscillation2QKvcO N sin AO-AO

2Harish Krishnaswamy, Hossein Hashemi frequency without any injection, Q is the VPRO resonator quali-

ty factor, Kvco is the VCO gain, E is the ratio of the injected signalUniversity of Southern California, Los Angeles, CA amplitude to the undisturbed oscillation amplitude, and AO and

AO are the phase progressions of the VPRO and the received sig-Phased arrays are a special class of multiple antenna systems nals, respectively. The strength of the downconverted signal atthat allow for electronic beam-steering through the introduction V,tri exhibits the very same spatial selectivity as a conventionalor compensation of time delays in the signal paths of different phased-array receiver does. It should be emphasized that theantennas. The amount of additional time delay that is intro- phase-shifting, power combining, and downconversion are doneduced/compensated in each successive signal path determines the through the combined VPRO-PLL action without any explicitangle of radiation/incidence at which the electromagnetic signals blocks.add up coherently. In addition to spatial selectivity, the SNR of an Each 24GHz differential LNA is a 2-stage, inductively degenerat-N-channel phased-array receiver is enhanced by 1Olog10(N) deci- ed design, where cascode configuration is used to improve thebels compared to that of a single-channel receiver [1]. Phased- reverse isolation and stability (Fig. 6.7.3). The input and outputarray transmitters represent a high-efficiency spatial power-com- of both stages are matched to 100Q differential impedances. Thebining scheme and relax the PA output power requirements of 24GHz on-chip PA is a single-stage pseudo-differential-pair witheach channel [2]. The complete integration of phased-array trans- cascode transistors. A PA driver feeds the VPRO signal to theceivers in a CMOS process offers tremendous possibilities for low- appropriate PA. All the on-chip high-frequency signal routing iscost high-speed wireless communication systems and radar. accomplished through differential substrate-shielded coplanar

striplines [5] with characteristic impedance of 100Q. A stand-In narrowband phased arrays,tth reie time delay is often alone PA has a measured small-signal power gain of lldB atapproximated with a phase shifttoa the plementatin. 22GHz and a saturated output power in excess of 12.9dBm withCMOS implemen atiins, Hct phaseshltilng andt power comoin- a peak drain efficiency greater than 18.8% (Fig. 6.7.4). The cen-ing, prior to the mixing action, is challenging due to the loss of on- ter frequency of all tuned blocks can be adjusted through NMAOSchip passive components. Alternately, phase shifting may be varactorstaccomplished in the LO path [1-3], where the loss of the phaseshifters is moved out of the RF path. Multi-phase oscillators have The VPRO stages are implemented as differential pairs with LCbeen used to produce the necessary LO phases [1, 2]. However, resonant loads using NMOS varactors. The design and layout ofthe interconnect structure required to distribute these LO phas- the VPRO should be symmetric to guarantee a linear phase pro-es consumes significant chip area. The LO phases can also be gression between adjacent elements. In this implementation, therealized locally through phase interpolation of a quadrature oscil- phase shifter is realized as 4 tuned differential pairs identical tolator to reduce the size of the LO distribution structure [3]. the VPRO stages. The varactor control voltages of these addition-

al stages are tied together and control the phase of the VPRO.In this paper, a fully integrated phased-array transceiver archi- Each VPHO stage can sustain a maximum phase shift of +60°.tecture is introduced that eliminates all the RF phase shifters, al h nOtale in this potyehexrphase shift ,ditibto newrs powe.r cobnes an Fmxes h Although not realized in this prototype, the extra phase shift,dilstribDution networkis, power combiners, and HF mixers. The

transceiver is based on a variable-phase ring oscil- necessary for extreme steering angles, can be obtained by flippingphasedl-array the differential connections. It can be shown that the proposedlator in a PLL (VPHO-PLL). In the transmit mode, the VPRO VPHO phased-array architecture is less sensitive to componentPLL modulates the baseband information and provides the mismatches by an order of magnitude compared to other phasedappropriately phase-shifted modulated signal to each antenna arrays that do not use phase shifters such as those using coupledelement. In the receive mode, the incoming RF signals for all oscillators. The VPRO is locked in a charge-pump-based PLLchannels are phase shifted, downconverted, and coherently com- where the dividers are implemented using static D-flip flops (Fig.bined inside the VPRO-PLL. Figure 6.7.1 shows the compact 6.7.5).implementation of a 4-channel phased-array transceiver proto-type at 24GHz based on the VPRO-PLL concept. The chip is Transmit and receive array patterns are measured to test theimplemented in a 0.13gm CMOS process with 8 metal layers and phased-array functionality. Power splitters and variable phaseoccupies an area of 2.35x2.15mm2. shifters are used to emulate the propagation of a plane wave in

aspace. Transmit and receive array patterns for the same anglesThe 4-stage VPRO consists of tuned amplifiers connected in aremeasure d becsimilar,Fg 6.7.6rshow the measuredrincofgrto wit an adiioa phs shftr Th .diin are measured to be similar. Fig. 6.7.6 shows the measured 4-ring configuration with- an addtittonal phrase shifter, The addititon- channel tlranslmit patterns and 2-channel rseceive patterns for a

al phase shift is distributed evenly among all 4 VPRO stages to fwangl oradiation/indenchene aenna paratin issatisfy the loop boundary condition in such a way that the total half-wavelength at 24GHz. A close match between themneasuredphase shift in the ring is zero. Hence, a linear phase progression and ideal array patterns is observed. The phased array in theis established across the VPRO stages, which is the requirement ivemo achievesaio f 42dB an reticallyto electronically steer the beam in narrowband phased arrays, improves the receiver SNR by 6dB. In the transmit mode, theThe VPRO oscillation frequency is set to the desired value array EIRP is enhanced to 24.9dB. Figure 6.7.7 summarizes the

through the PLL. measured performance of the chip.In the transmit mode, the baseband information is fed into the References:PLL through the control voltage, Vctri (Fig. 6.7.2). The baseband [11 H. Hashemi, X. Guan, and A. Hajimiri, "A Fully Integrated 24GHz 8-signal is frequency modulated around the VPRO oscillation fre- Path Phased-Array Receiver in Silicon," ISSCC Dig. Tech. Papers, pp. 390-quency. The output signal of each VPRO stage is the frequency- 391, Feb., 2004.modulated signal with a controllable phase shift relative to the [2] A. Natarajan, A. Komijani, and A. Hajimiri, "A 24GHz Phased Arrayadjacent stage. Each VPRO stage drives a 24GHz on-chip power Transmitter in 0.18pm CMOS," ISSCC Dig. Tech. Papers, pp. 212-213,amplifier for each antenna element without requiring any power Feb., 2005.distribution network. [31 A. Natarajan, A. Komijani, and A. Hajimiri, "A Silicon-Based 77GHz

Phased-Array Transmitter with Local LO-Path Phase-Shifting," ISSCCIn the receive mode, each 24GHz on-chip LNA injects its received Dig Tech, Papers, pp. 1S2-183 Feb. 2006l > |11.~~~~~~~~~[41 B. Razavi, "A Study of Injectionl Locking and Pullinlg inl Oscillators,"signalintothe tune rsnao of th corsodngVR .tg IEEE J. Solid-Stalte Circuizts, vol. 39, pp. 1415-1424, Sept., 2004.in thne current domain (Fig. 6.7.2). In thne abDsence of thnese input [51 T. Cheung, J. Long, KE. Vaed, H. Volant, A. Chinthakindi, C. Schnabel,

signals, the PLL is locked to a reference frequency anLd Vctri is J. Florkey, K. SteinL, "'On-chip Interconnlect for mmrn-Wave ApplicationLsfixed. The incomilng mnodulated signals pull the VPHO frequency. Using an All-Copper Technology and Wavelength Reduction," ISSCC Dig.In an attempt to maintain lock, the value of Vitri in the PLL is Tech, Patpers, pp. 396-397, Feb., 2003.modified to follow the modulationl [4]. It can be shown that, with-

112 *207IEInentoa Solid-State1111Circuits11Conference111l1142441108521 O/07/$25001 ©2007 IEEE.111

ISSCC 2007 1 February 12, 2007 /4:15 PM

OscillatorLNA Input Buffer

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Figure 6.7.2: Principle of operation of the VPRO-PLL phased-array architecture -receive and transmit modes.12 j|S2i|T] °

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m 61 I xos ~~~~~L.....J 1-20_ | 11 WL -8~~~~~~~~~~~~~~C -10 40 ll-,o 0 0t- 4 400. C) X -=- I I =.,t II X.lLL2 .5 E-0o -20 t- 4 <g >2 1 \ t ~~~~~~ ~ ~ ~~~~-12~I. |X

^ | *1 o -~~~~~~~130o -14gr u 30d48I -ioo-2 |-10 4 23.93 23.94 23.99 23.96 23.97

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Figure 6.7.4: MlVleasured power amplifier small-signal S-parameters and large-signalperformance at 22.25GHlz. Figure 6.7.5: Measured spectrum of the locked VPRO.

ConZtinoued on Page 591

DIGEST OFTECHNICAL PAPERS * 125

ISSCC 2007 PAPER CONTINUATIONS

Phased Array SpecificationNumber of channels 4

Frequency of Operation 24GHz

Transmitter Performanceo o 0o_______________~~30 7 30 30 [Maximum PA Output Power >12.9dBm

[4-element EIRP >24.9dBm

X |||i -- - . \60 /,4||||| -, \60 / i1111 \60 [Peak PA Drain Efficiency >18.8%

[PA Power Consumption per element 78mA @1.5V

[PA Driver Power Consumption per element 13mA @1.5V0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1

4-element TX patterns Receiver Performance0 0

3030 [Receiver Gain 30dB

[Total Array Gain 42dB/ .--i.- || | || --;i . 60 /||. | 60 SNR Improvement 12dB

[LNA Power Consumption per element 25mA @1.5V

[VPRO Input Buffer Power Consumption per element 2.5mA @1.5V0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1 LO Path Performance

2-element RX patternsVPRO Power Consumption per element 7.5mA @1.5V

Digital Dividers Power Consumption 85mA@1.5V

PFD + Charge Pump Power Consumption 16mA@1.5V

ImplementationProcess Technology 0.13pm CMOS

Chip Size 2.35mmx2.15mm

Figure 6.7.6: Measured array patterns for half-wavelength antenna separation. Figure 6.7.7: Measured performance summary.

59 1111* 207IEE ntrntional Solid-State Circuits Conference 1-4244-0852-O/07/$25001 ©2007 IEEE