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26-6-2013 Zinan Technologies GmbH Slide 1
Solder Bump Process Solder Bump Process
OptimizationOptimization
Ren P. Zingg
Zinan Technologies GmbH

Outline
Bump requirements
Geometric considerations
Bump fabrication methods
Material considerations
Test methods, industry standards
Degradation mechanisms: brittle fail
Observed issues: Pad Lift, poor die shear
results
Conclusions.

Bump Requirements
Depending on application (consumer: mobile phone or automotive: under the hood, power control: battery management) elasticity (resistance to drop test), strain absoption (resistance to thermal cycling), or low electromigration (resistance to brittle failure) will be most critical.
These requirements affect bump material, bump size and placement on die, and use of parallel conduction paths (redundant bumps). The following slides address these aspects.

Geometric Considerations
Bump should be placed with minimum separation in hexagonal (rectangular) arrangement.
Cylindrical bumps would be ideal to absorb shear strain from mis-match in thermal expansion.
Surface tension leads to spherical bumps, pad on silicon and landing on PCB need optimization.
Silicon
PCB
PCB
Silicon

Deformed Bump after Reflow
5

Bump Fabrication Methods
Screen-Print Free choice of materials
Some risk of void formation
Limited aspect ratio
Electroplating Only bimetallic alloys such as Sn-Ag possible
Limited bump height
Gang ball placement Free choice of materials
Some risk of poor wetting to under-bump metalization
High flexibility in bump size (volume).

Bump Material
Average shear strength varies strongly with
alloy.
Use of strain buffers, such as polyimide
collars can further increase bump strength.
Bump Shear Force
-3.15
-2.1
-1.05
0
1.05
2.1
3.15
30 40 50 60 70 80 90 100 110 120 130 140 150 160 170[cN]
SAC305 PI collar
SAC351 Sn1.8%Ag
SAC105 %
50%
1%
2%
5%
10%
20%
30%
40%
60%
70%
80%
90%
95%
98%
99%

Effect of Polyimide
8

Bump Tests, Industry Standards
Process well known from wire bond testing (ball shear test BST).
JEDEC JESC-22b117A and AEC-Q100-10A are not very specific on shear speed, standoff, and reject criteria except for wetting problems and brittle intermetalic formation.
Alternate processes, such as pull tests have been tried.
Stage, moving with shear speed
Shear
tool,
sensing
shear
force
Wafer with solder bumps
Solder ball
Standoff

Shear Modes of AEC Q100-010A
5% of shear surface in mode 2 is a fail criteria, as well as any mode 3 or 5.
AlNi
IMC
Chip
Solder
Separation with the bulk of the solder separating from
the solder pad, but with the plating remaining on the
solder pad. This condition is typically due to improper
wetting.
5
Separation occurs in the substrate material beneath the
solder pad causing the pad to rip out or peel from the
substrate. The solder ball remains attached to the pad.
4
Separation occurs between the barrier metal layers
under the bump (typically as a loss of adhesion between
the copper and nickel). The pad typically appears flat in
these areas.
3
Separation occurs as a fracture through the metal-to-
metal brittle intermetallic layer (typically through the
nickel-tin or gold-tin intermetallic). The pad typically
appears flat in these area.
2
Separation occurs through the bulk solder.
Characterized by solder remaining on entire solder pad.
1
Separation Mode Definition#

Degradation mechanisms
Interdiffusion, combined with electromigration and stress-migration can lead to formation of brittle intermetallic compound.
Choice and thickness of under-bump metalization on chip side and wiring (barrier) on PCB side can be critical.
40
50
60
70
80
90
100
110
120
virgin 240hHTSL 550hHTSL 1000hHTSL
Shear Force [cN]
+ 1 1 mode 1
+ 1 1 mode 4
AEC
Q100:
40
50
60
70
80
90
100
110
120
virgin 240cTC 576cTC 1000cTC
Shear Force [cN]
+ 1 1 mode 1
+ 1 1 mode 4
AEC Q100:
3200g/cm2
HTSL: 150C
TC: -50 to 150C, 10 min ramp, 20 min dwell

Observed Issue: Pad Lift at Bump Shear
On average about 7% pad lift.
Random occurrence, typically on wafers with relatively high shear force.
Shear Value
0%
20%
40%
60%
80%
100%
120%
140%
1 11 21 31 41 51 61 71 81 91 101 111 121 131 141 151 161 171 181 191 201 211 221 231 241 251 261 271 281 291 301 311 321 331 341 351 361
Pad Lif t
0
20
40
60
80
100
120
140
Shear St reng t h
frct old new
average average
average + 1 - 1 + 1 - 1 + 1 - 1

Observed Issue: Poor Die Shear Results
Low and variable die shear performance.
No correlation to bump shear data
(average force, occurrence of pad lift).
Cpk DieShear
-1
0
1
2
3
4
5
6

Conclusions
Solder bump assemby (flip-chip) can be a valuable assembly
technology even for demanding applications such as automotive or high-current power control.
Special requirements on pad placement, quite different from
wire bonding.
Different solder compounds allow optimization to specific
requirements.
Occurrence of pad lift is not understood, but has no impact on product reliability.
Observed low die shear performance apparently related to
mounting on PCB, solder ductility, and bump placement on die.

26-6-2013 15
Thank you for your attention
(Crystalline SiO2 from Mt. Zinggenstock, Switzerland)

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