soc design - sharif university of...

SoCSoC DesignDesignSoCSoC DesignDesign

Lecture Lecture 11: Introduction: Introduction

Shaahin HessabiShaahin HessabiDepartment of Computer EngineeringDepartment of Computer EngineeringDepartment of Computer EngineeringDepartment of Computer Engineering

Sharif University of TechnologySharif University of Technology

SystemSystem--onon--ChipChipSystem: a set of related parts that act as a whole to achieve System: a set of related parts that act as a whole to achieve a given goal.a given goal.A system is a set of interacting components, which has A system is a set of interacting components, which has inputs and outputs, and exhibits specific behavior. inputs and outputs, and exhibits specific behavior.

Behavior: a function that translates inputs into outputs Behavior: a function that translates inputs into outputs

System: an entity consisting of hardware and softwareSystem: an entity consisting of hardware and softwareH d hi h d l ti l iH d hi h d l ti l iHardware: high speed, low power consumption, less price Hardware: high speed, low power consumption, less price (probably)(probably)Software: flexibility, ease of modification and upgradeSoftware: flexibility, ease of modification and upgradey, pgy, pg

Hardware system: a system whose physical components Hardware system: a system whose physical components are electronic blocksare electronic blocks

AnalogAnalogDigitalDigitalMi d i lMi d i l

Sharif University of Technology Slide Slide 22 of of 3232

Mixed signalMixed signal

SoC: Introduction

Digital vs. Analog Systems Digital vs. Analog Systems

The critical advantage of digital systems is their ability toThe critical advantage of digital systems is their ability toThe critical advantage of digital systems is their ability to The critical advantage of digital systems is their ability to deal with electrical signals that have been degraded.deal with electrical signals that have been degraded.

Due to the discrete nature of the outputs, a slight variation in an Due to the discrete nature of the outputs, a slight variation in an input is still interpreted correctly.input is still interpreted correctly.

In In analoganalog circuits, a slight error at the input generates an circuits, a slight error at the input generates an t th t tt th t terror at the output.error at the output.

The simplest form of a digital system is binary.The simplest form of a digital system is binary.AA bi i lbi i l ii d l dd l d t ki l t di tt ki l t di tA A binary signalbinary signal is is modeledmodeled as taking on only two discrete as taking on only two discrete values (values (0 0 or or 11, LOW or HIGH, False or True)., LOW or HIGH, False or True).

Sharif University of Technology Slide Slide 33 of of 3232SoC: Introduction

Advantages of Digital SystemsAdvantages of Digital Systems

1.1. High noise immunityHigh noise immunity22 Adjustable precisionAdjustable precision2.2. Adjustable precisionAdjustable precision3.3. Less sensitivity to variations in components and Less sensitivity to variations in components and

environmental parameters (especially temperature)environmental parameters (especially temperature)environmental parameters (especially temperature)environmental parameters (especially temperature)4.4. Ease of design (Ease of design ( automation) and fabrication, and automation) and fabrication, and

therefore, low costtherefore, low costtherefore, low costtherefore, low cost5.5. Better reliabilityBetter reliability66 Less need to calibration and maintenanceLess need to calibration and maintenance6.6. Less need to calibration and maintenanceLess need to calibration and maintenance7.7. Ease of diagnosis and repairEase of diagnosis and repair88 Easy to duplicate similar circuitsEasy to duplicate similar circuits8.8. Easy to duplicate similar circuitsEasy to duplicate similar circuits9.9. Easily controllable by computerEasily controllable by computer


Disadvantages of Digital SystemsDisadvantages of Digital Systems

1.1. Lower speedLower speedN d l t di it l (A/D) d di it l t l (D/A)N d l t di it l (A/D) d di it l t l (D/A)2.2. Need analog to digital (A/D) and digital to analog (D/A) Need analog to digital (A/D) and digital to analog (D/A) converters to communicate with real world; therefore, converters to communicate with real world; therefore, more expensive or less precisemore expensive or less precisemore expensive or less precisemore expensive or less precise


Contemporary Digital DesignContemporary Digital Design

Major changes in digital design in recent years:Major changes in digital design in recent years:More complex designs More complex designs New methodologies and techniques required, New methodologies and techniques required, like like SoCSoCShorter timeShorter time--toto--market (TTM)market (TTM)Cheaper productsCheaper productsp pp p

ScaleScalePervasive use of computerPervasive use of computer--aided design tools over hand methodsaided design tools over hand methodsM lti l l l f d i t tiM lti l l l f d i t tiMultiple levels of design representation Multiple levels of design representation

TimeTimeEmphasis on abstract design representationsEmphasis on abstract design representationsp g pp g pProgrammable rather than fixed function componentsProgrammable rather than fixed function componentsAutomatic synthesis techniquesAutomatic synthesis techniquesImportance of sound design methodologiesImportance of sound design methodologiesImportance of sound design methodologiesImportance of sound design methodologies

CostCosthigher levels of integrationhigher levels of integration


use of simulation to debug designsuse of simulation to debug designsSoC: Introduction

Software Tools Software Tools

Digital design need not involve any software tools; however,Digital design need not involve any software tools; however,Software tools are nowadays an essential part of digital designSoftware tools are nowadays an essential part of digital designSoftware tools are nowadays an essential part of digital design.Software tools are nowadays an essential part of digital design.HDLs (HDLs (Hardware Description LanguagesHardware Description Languages) and the corresponding simulation ) and the corresponding simulation and synthesis tools are widely used.and synthesis tools are widely used.

In a CAD (ComputerIn a CAD (Computer--Aided Design) environment, the tools improve Aided Design) environment, the tools improve the productivity and help in correcting errors and predicting the productivity and help in correcting errors and predicting behaviorbehavior..

Schematic entry;Schematic entry;HDLs compilers, simulators and synthesis tools;HDLs compilers, simulators and synthesis tools;Timing analysers;Timing analysers;Timing analysers;Timing analysers;SimulatorsSimulatorsTest benches.Test benches.


Integrated Circuits (ICs) Integrated Circuits (ICs)

An IC is a collection of gates/blocks/... fabricated on a single silicon An IC is a collection of gates/blocks/... fabricated on a single silicon chipchipchip.chip.ICs are classified by their size:ICs are classified by their size:

SSI (small scale integration): SSI (small scale integration): 1 1 to to 30 30 gatesgates( g )( g ) gg-- a small number of gates.a small number of gates.MSI (medium scale integration): MSI (medium scale integration): 30 30 to to 300 300 gatesgates

decoder register counterdecoder register counter-- decoder, register, counter.decoder, register, counter.LSI (large scale integration): LSI (large scale integration): 300 300 to to 300300,,000 000 gatesgates-- small memories, PLDs.small memories, PLDs.VLSI (very large scale integration): > VLSI (very large scale integration): > 11,,000000,,000 000 transistorstransistors-- microprocessors, memories.microprocessors, memories.

The Core The Core 2 2 Extreme QXExtreme QX9650 9650 Quad Core Processor (Intel Quad Core Processor (Intel 20082008 45 45 The Core The Core 2 2 Extreme QXExtreme QX9650 9650 Quad Core Processor (Intel Quad Core Processor (Intel 20082008, , 45 45 nm technology) has nm technology) has 820 820 million transistors (million transistors (420 420 M transistors per die)M transistors per die)


Implementation TechnologiesImplementation Technologies


Modern SystemsModern Systems

Basic elements:Basic elements:Microprocessors, buses and ASICs.Microprocessors, buses and ASICs.p ,p ,

Basic problems:Basic problems:HW/SW partitioning.HW/SW partitioning.HW/SWHW/SW i l ti (i l di i ti d li )i l ti (i l di i ti d li )HW/SW coHW/SW co--simulation (including communication modeling).simulation (including communication modeling).Different design tradeDifferent design trade--offs.offs.Separate HW and SW design flows.Separate HW and SW design flows.gg


What is an SoC?What is an SoC?SoC Concept in the past simply implied higher levels of SoC Concept in the past simply implied higher levels of

integration (Moore’s law):integration (Moore’s law):A i l hi l h h l l i hiA i l hi l h h l l i hiA single chip replaces the whole multichip systemA single chip replaces the whole multichip system--onon--boardboardDifferent chips on PCB (Different chips on PCB (Printed Circuit BoardPrinted Circuit Board) are now) are nowDifferent chips on PCB (Different chips on PCB (Printed Circuit BoardPrinted Circuit Board) are now ) are now building blocks (building blocks (corescores) of SoC chip) of SoC chipAdvantages:Advantages:

OnOn chip interconnects are man times faster than offchip interconnects are man times faster than off chip ireschip iresOnOn--chip interconnects are many times faster than offchip interconnects are many times faster than off--chip wireschip wiresGet a compact system with the same functionalityGet a compact system with the same functionalityReduces pin overheadReduces pin overhead

–– Saves much powerSaves much power–– Reduces noise in the mixedReduces noise in the mixed--signal/analog circuitssignal/analog circuits

Lower overall costLower overall cost


What is an SoC? (cont’d)What is an SoC? (cont’d)( )( )Today’s concept: gaining overall productivity gains through Today’s concept: gaining overall productivity gains through

reusable design and integration of componentsreusable design and integration of components

Complex IC that Complex IC that

g g pg g p

ppintegrates the major integrates the major functional elements of a functional elements of a complete endcomplete end--product product into a single chip using into a single chip using intellectual property (IP)intellectual property (IP)intellectual property (IP) intellectual property (IP) blocks.blocks.

IPs: preIPs: pre--designed and designed and pp ggprepre--verifiedverifiedAlso called: virtual Also called: virtual componentscomponents


componentscomponents

SoC: Introduction

Design Productivity GapDesign Productivity Gapg y pg y p

, , th

e IE

EE

,th

e IE

EE

,0606

edin

gs o

f t

edin

gs o

f t

June

Ju

ne 2

00200

Proc

eePr

ocee

SoC/IP approach improves the situationSoC/IP approach improves the situationSoC/IP approach improves the situationSoC/IP approach improves the situationPlatformPlatform--Based Design improves it furtherBased Design improves it further


Inside an Inside an SoCSoCAn An SoCSoC usually contains:usually contains:

ReusableReusable IPIP–– Requires connecting computational units to communication mediumRequires connecting computational units to communication medium

Embedded processor, memoryEmbedded processor, memoryRealReal--world interface (wireless receiver/transmitter )world interface (wireless receiver/transmitter )RealReal world interface (wireless receiver/transmitter, …)world interface (wireless receiver/transmitter, …)SensorSensorMixedMixed--signal blockssignal blocksProgrammable hardwareProgrammable hardwareRTOS and embedded software, device driversRTOS and embedded software, device drivers

Has more thanHas more than 500500 K gatesK gatesHas more than Has more than 500 500 K gates,K gates,Uses .Uses .25 25 μmμm technology or belowtechnology or belowIs not an ASICIs not an ASICIs not an ASICIs not an ASIC

Primary difference from ASIC: in SOC design, the goal is to Primary difference from ASIC: in SOC design, the goal is to maximize reuse of existing blocks or “cores”maximize reuse of existing blocks or “cores”


Why Why SoCSoC ??yy

Increased functionality/performance in reduced footprintIncreased functionality/performance in reduced footprintTighter design scheduleTighter design scheduleBandwidth and performanceBandwidth and performanceSimplified PCB designSimplified PCB designIncreased product mechanical robustnessIncreased product mechanical robustnessLower power consumptionLower power consumptionTechnology scalingTechnology scalingLower system costLower system cost……


SystemSystem--inin--aa--Package (SIP)Package (SIP)SoCSoC technology technology –– a great success, EXCEPT for radio a great success, EXCEPT for radio receiver/transmittersreceiver/transmitters

SystemSystem inin aa Package (SIP)Package (SIP)

receiver/transmittersreceiver/transmittersCan sustain mixed analog/digital hardware together on one chip, Can sustain mixed analog/digital hardware together on one chip, provided that:provided that:

A l h d i i th lA l h d i i th l f b df b d–– Analog hardware is in the lowAnalog hardware is in the low--frequency bandfrequency band–– Digital clocks & their harmonics are carefully chosen to avoid Digital clocks & their harmonics are carefully chosen to avoid

polluting key parts of the spectrum with noisepolluting key parts of the spectrum with noiseKey result: Still unable to integrate radio frequency (RF) Key result: Still unable to integrate radio frequency (RF) hardware into hardware into SoCSoC

–– Substrate coupling between digital and analog parts causesSubstrate coupling between digital and analog parts causesSubstrate coupling between digital and analog parts causes Substrate coupling between digital and analog parts causes digital clock noise to destroy the signaldigital clock noise to destroy the signal--toto--noise ratio of RF noise ratio of RF partpart

–– RF tuners still require precision inductors but onRF tuners still require precision inductors but on--chipchipRF tuners still require precision inductors, but onRF tuners still require precision inductors, but on chip chip inductors are expensive and inadequateinductors are expensive and inadequate


SystemSystem--inin--aa--Package (SIP)Package (SIP)yy g ( )g ( )

Interim solution: Combine separate digital & analog chips Interim solution: Combine separate digital & analog chips and passive components into a single package (SIP orand passive components into a single package (SIP orand passive components into a single package (SIP, or and passive components into a single package (SIP, or MCM= MultiMCM= Multi--Chip Module)Chip Module)

Common Common 22--D or D or 33--D substrateD substrateMay contain SoC as one of the chipsMay contain SoC as one of the chips

Proceedings of the IEEE, Proceedings of the IEEE, June June 20062006JJ


SoCSoC Challenges Challenges

Increasing complexityIncreasing complexityTimeTime--toto--market pressuremarket pressureTimeTime toto market pressuremarket pressureVerification bottleneckVerification bottleneck

IntegrationIntegrationggHardware Hardware v.sv.s. software. softwareDigital circuits Digital circuits v.sv.s. . analoganalog circuitscircuitsTesting issuesTesting issues

Deep submicron effectsDeep submicron effectsTi i l blTi i l blTiming closure problemTiming closure problemSignal integrity problemSignal integrity problemReliability problemReliability problemReliability problemReliability problem


TimeTime--toto--Market PressureMarket Pressure

Pressure from shorter product lifespanPressure from shorter product lifespan

An additional key factor in TTM, specific for SoC: An additional key factor in TTM, specific for SoC: System System integration = integration = integrating different silicon IPs on the same ICintegrating different silicon IPs on the same IC


gg g gg g

TimeTime--toto--Market Pressure (cont’d)Market Pressure (cont’d)

Profit model showing the value of TTM:Profit model showing the value of TTM:


Verification BottleneckVerification Bottleneck

Verification becomes the major bottleneck of the modern Verification becomes the major bottleneck of the modern design flowsdesign flows


HW/SW IntegrationHW/SW Integration

Integrating HW/SW at the final step may require high Integrating HW/SW at the final step may require high cost.cost.

Early integration (HW/SW codesign)Early integration (HW/SW codesign)

Trend toward increasing design Trend toward increasing design complexity due to integrationcomplexity due to integrationcomplexity due to integrationcomplexity due to integration


Challenges for Mixed Signal DesignsChallenges for Mixed Signal Designs

Design challengesDesign challengesChiChi l l i l ti t k t h til l i l ti t k t h tiChipChip--level simulation takes too much timelevel simulation takes too much timeDesign budgets are not distributed in a wellDesign budgets are not distributed in a well--defined mannerdefined mannerToo much time is spent on lowToo much time is spent on low--level iterationslevel iterationsToo much time is spent on lowToo much time is spent on low level iterationslevel iterationsDesign is not completely systematicDesign is not completely systematicThere is limited or no use of HDLThere is limited or no use of HDL


SoC Testing ChallengesSoC Testing Challenges

Distributed design and testDistributed design and testC id d t k th t t i tC id d t k th t t i tCore provider does not know the target environmentCore provider does not know the target environmentSystem integrator is responsible for manufacturing testingSystem integrator is responsible for manufacturing testing

Test accessTest accessTest accessTest accessBedBed--ofof--nails (decomposition) system testing is not possiblenails (decomposition) system testing is not possibleMost of the cores are surrounded by many other coresMost of the cores are surrounded by many other cores

R lt i t ll bilit dR lt i t ll bilit d b bilitb bilit–– Results in very poor controllability and Results in very poor controllability and observabilityobservability–– Need electronic test hardware to access these blocks during testingNeed electronic test hardware to access these blocks during testing–– Bandwidth, I/O pin count limitationsBandwidth, I/O pin count limitations

Test optimizationTest optimizationMinimizing test cost while satisfying constraints such as power, Minimizing test cost while satisfying constraints such as power, resources coverage etcresources coverage etcresources, coverage, etc.resources, coverage, etc.


Timing Closure ProblemTiming Closure ProblemTraditional silicon design flows: used statistical wireTraditional silicon design flows: used statistical wire--load load models to estimate metal interconnects for premodels to estimate metal interconnects for pre--layout timing layout timing

l il ianalysisanalysisload on a specific node: estimated by the sum of the input load on a specific node: estimated by the sum of the input capacitances of the gates being drivencapacitances of the gates being drivenstatistical wire estimate based on the size of the block and the statistical wire estimate based on the size of the block and the number of gates being drivennumber of gates being drivenCorrect for Correct for 250 250 nm and above, because the gate propagation nm and above, because the gate propagation delays and gate load capacitances dominatedelays and gate load capacitances dominate

Wire delay starts to dominate total delay in DSM processWire delay starts to dominate total delay in DSM processLack of physical information about wire lengthLack of physical information about wire lengthLack of physical information about wire lengthLack of physical information about wire length

Only statistical wire delay model can be used at design phaseOnly statistical wire delay model can be used at design phaseInaccurate because they represent a statistical value based on the Inaccurate because they represent a statistical value based on the block si eblock si eblock size block size

Incorrect estimations require long iterations to meeting timingIncorrect estimations require long iterations to meeting timing


Signal Integrity, ReliabilitySignal Integrity, Reliability

Feature size ↓→ subFeature size ↓→ sub--wavelength lithography (impacts wavelength lithography (impacts of process variation), noise, crossof process variation), noise, cross--talk, SEU, reliabilitytalk, SEU, reliabilityFrequency ↑, dimension ↑ →interconnect delay, Frequency ↑, dimension ↑ →interconnect delay, l t ti fi ld ff t ti i ll t ti fi ld ff t ti i lelectromagnetic field effects, timing closureelectromagnetic field effects, timing closure

Supply voltage ↓→ signal integrity (noise, IR drop, Supply voltage ↓→ signal integrity (noise, IR drop, etc)etc)etc)etc)Wiring level ↑→ manufacturabilityWiring level ↑→ manufacturabilityPower consumption ↑ power & thermal issuesPower consumption ↑ power & thermal issuesPower consumption ↑→ power & thermal issues Power consumption ↑→ power & thermal issues


General Architecture of General Architecture of CoreCore--Based SoCBased SoC


Design FlowDesign Flow

Traditional Design Flow:Traditional Design Flow:11 FrontFront--end designend design1.1. FrontFront--end designend design

Begins with system definition in behavioral or algorithmic form Begins with system definition in behavioral or algorithmic form and ends with floor planningand ends with floor planning

2.2. BackBack--end designend designBegins with placement/routing through layout release (tapeBegins with placement/routing through layout release (tape--out)out)

Engineers in either phase don’t know much about the Engineers in either phase don’t know much about the other phaseother phase


Design Flow (cont’d)Design Flow (cont’d)

Vertical Integrated Design Environment:Vertical Integrated Design Environment:E i h f ll ibilit f bl k f tE i h f ll ibilit f bl k f tEngineers have full responsibility for a block from system Engineers have full responsibility for a block from system design specifications to physical design prior to chipdesign specifications to physical design prior to chip--level integrationlevel integrationlevel integrationlevel integration

Necessary for functional verification of complex blocks with postNecessary for functional verification of complex blocks with post--layout timinglayout timingAvoids last minute surprises related to block aspect ratio, timing, Avoids last minute surprises related to block aspect ratio, timing, routing, or architectural and area/performance traderouting, or architectural and area/performance trade--offsoffsMust be familiar with several CAD tools in a complex EDAMust be familiar with several CAD tools in a complex EDAMust be familiar with several CAD tools in a complex EDA Must be familiar with several CAD tools in a complex EDA environmentenvironment


Task responsibilities of an engineer in a Task responsibilities of an engineer in a rti l d i n n ir nm ntrti l d i n n ir nm ntvertical design environmentvertical design environment


soc design - sharif university of...

Documents