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Table 1: Summary of pixel designs

APSG2 P-well photogate with light shield 28 x 28APSG4 P-well square photogate 28 x 28APSG1 P-well tiny pixel photogate 28 x 28APSG3B P-well single poly tiny pixel 28 x 28APSG5 N-well photodiode 28 x 28AR28NCB N-well photogate with a'owlr 28 x 28

windows of Interest. The image sensors are opexated with 1TLclocks and at most two other d.c. voltages. These image senso.hieve lateral blooming conirol through roper biasing of the

=1== F. 1: Pphofcom;n_cütLdouble sampling (CDS) to eliminate kTC noise, 1/f noise and y

fixed pattern noise from the pixeL Low noise and high dynamieiinge are hieved. The option of using a radiation hard CMOS process is also available. CMOS &tive pixel image seisoiare suitable for many applications including rthotics and mhine vision, guidate and navigation, automotive ajlicafions,and consumer elutrothcs such as video phones, computer inpots and home surveillace deviees.

This paper presents recent arthievements in CMOS APS research. Sectin 2 describes the basic chip archilectureemployed in the design of CMOS tive pixel image sensors. Section 3 presents the baseline design, its operation andexperimental results. Section 4 describes the different pixel unit cell designs expkBed and compares their pezformance withthe baseline design. Two fixed pattern noise siqçression methods that were investigated are presented in section 5.

2. CMOS APS TEST CHIPS

The 10 different active pixel arrays that were fabricated are summarized in table 1. All the designs were fabricated atOrbit Semiconductor through the MOSIS foundry seriice. In the baseline design, e&h pixel contains a photogate imagingelement like a single CCD stage with a floating diffusion output. This design was first implemented using a p-well CMOStechnology as a 28 x 28 test any (AR28P2) and later expanded to a 128 x 128 array (AR12SP2) and n-well implementations(AR2SN and AR128N1). Other test arrays we demonstrated for pixel designs with a light shield on the transistors withinthe pixel (APSG2), a square photogate (APSG4), a minimum size photogate (APSG1) and a single-poly implementation ofthe minimum size photogate (APSG3B). A 28 x 28 photodiode &tive pixel sensor array was also implemented (APSG5). Atest array of the baseline pixel design with a modified readout circuit w developed for fixed pattern noise suppression usingan n-well CMOS technology (AR28NCB).

2.1 Chip architecture

The CMOS artive pixel nsor chips were fabricated using 2 tm CMOS technology with two levels of polysiliconand two levels of metal. The resulting pixel size was 40 tm x 40 pin. A photograph of a completed 128 x 128 CMOS APSalTay is shown in Fig. 1. A column parallel architecture was used, where an entire column of pixels shares one readoutcircuit. The row decoders and clock generator circuits to the left of the Al'S array and the column decods and readoutcircuits below the APS array were all designed to fit within the 40 j.un pixel pitch. The 7-bit row and column address

20/SPIEV0!. 2172

eP-well photogate

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The stored reset and signal levels are sequentially scannedout through the oixl set of source followers by enablingcolumn address Switches Yl and Y2. This timing sequenceis shown in Fig. 2(b).

Sampling both the reset and signal levels permitscorrelated double sampling (CDS) which suppresses kitnoise from the floating diffusion node cC the pixel and 1/fnoise and threshold variations from the sotce4ollower inputtransistor within the pixel [14]. The main source of noise inthis system is the kTC noise introduced by the sample andhold capacitors in the readout circuit. The sample and holdcapitersofthe28x28testarraysandthe 128x 128p-wellarray were designed to be polylpoly2 capacitors of 1 pF. Thecalculated r.ms. noise is 64 tV per capacitor, resulting in91 jiV fc differential mode. The sample and hold capacitorsof the nweil 128 x 128 arrays were increased toapproximately 2.3 pF by using an MOS capacitor under thepoly1-po1y2 capacitor. The calculated r.m.s. noise for thiscircuit is 42 &V per capacitor, resulting in 60 tV fordifferential mode.

The active pixel image senrs were operated with the timing and voltages desCribed above. However in the nwellimager sensors, the load transistor of the first source follower had to be biased at 1.25 V. Higher biasing made the columnamplifiers "glOW" and saturate the bottom part o( the image sensor array. This effect can be reduced by switching off columnselection transistors Yl and Y2 in all the columns during long integration periods. Both dark and illuminated testing of thesensors were performed. Through shot noise measurements, the pixel sensitivity was determined to be 3.7 tV/e for the p-well design and 6.5 p.tWe for the n-well design. By performing electrical tests on a test structure on a separate IC, theseftsitivity at the output of the first sowve follower w measured to be 4.0 tV/e for the p-well design. Although the wellcapacity was calcUlated to be approximately 6 x 1O e, saturation was determined by the output amplifier. The observedsaWration level was 600 mV corresponding to 162,000 efor the p-well design and 1.2V corresponding to 185,000 e for thenwell design. However, higher saturation levels can be achieved by operating the image sensors with a higher supply voltage.For example, by increasing the supply voltage to 6V, the sataration level in the p.well design was increased to approximately1.1v corresponding to 297,000 e.

The sensors were nominally clocked at 2 Wpixel, corresponding to a frame rate of approximately 30 Hz. For 5Voperation, power dissipation was measured to be approximately 7 mW for the 128 x 128 arrays and 5.9 mW for the 28 x 28arrays. The major power dissipation w in the p.channel transistors (87%) compared to the column-parallel n-channeltransistors (13%). Low power operation of the test array was demonstrated with a supply voltage of 3V. The power dissipationwas 0.84 mW and the saturation level was 200 mV for this mode of operation.

A raw output image from the 128 x 128 p-well image sensor is shown in Fig. 4(a). The fixed pattern noise isdominated by column-wise fixed pattern noise as evidenced by faint vertical streaks in the image. (Note that the half-toningprocess gives rise to artificial streaks not present in the original photograph.) In the p-well designs, global fixed pattern noise(FPN) observed in the differential output signal was approximately 20 mY p-p (3.3% sat.), with a local variation ofapproximately 8 mV p-p. The global variation is attributed to poor control of the p-well potential towards the center of thearray since slower clocking rates reduced the effect, and the 28 x 28 array showed a similar but much smaller effect DarkcwTent was measured to be approximately 0.26 Ws, or under 1 nA/cm2. Noise in the fabricated p-well array is fundamentally

22 ISPIE Vol. 2172

ii(c) (d)

3.2 Experimetital Results

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high& response and higher aoss talk in the n-well gns than the pwdll &signs.The pixel layout cC the baseline pixel is shown in Fig. 6(a) for comparison with theresponsivity maps. The 632.8 nm HeNe Iasei had a beam diameter o( approximately1.5 tm and a step size of approximately2 rim. The reSPOnSIVItY maps of the p-well and

n-well pixel are presented in FIg. 5(b) and 5(c) respectively. In the p-well design, theresponse is unifcwm acro the phosogate area with only polyl and drops off rapidly atthe edges. A lower response is noiicethle in areas overlapped by poly2 or metaL In then-well design, the response drops off more gradually, and cross talk from adjacentpixels is evident. The responsivity maps at 488 nm in Figs. 5(d) and 5(e) show similarpatterns. However, the response is lower than at 632.8nm due to the polysiliconphotogate.

Fig. 6(b): responsivity map of p-well pixel at 632.8 nm

Fig. 6(d): responsivity map of p-well pixel at 488 nm

24 /SPIE Vol. 2172

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5.1 Subtracting a column reference

5. FIXEDPATIERN NOISE SUPPRESSION

It was evident in all the CMOS active pixel image sensor designs described above that the fixed pattern noise wasdominated by the column to column vaiiations. FPN can thefore be greatly reduced by eliminating or reducing the columnwise FPN. The first such method demonstrated uses coinpoter softw&e to subtract a dark reference vtage from the signal.The reference f e&h column is obtained from the last row of pixels in the array, which is covered by light SIUeld. Fig. 4(b)demonstrates the improvement in image quality when FPN supression is on. With FPN suppression on, the measured globalFPN reduces to 0.8% p-p from 33% pp in the pwell baseline design. Of course, an entire dark image can be subtracted froman acquired image for greater FPN suppression, but this requires acquisition of the dark image.

5.2 Crowbar circuit

A column-FPN suppression scheme was incoporated into the output circuit of the next design. The baseline designof a phosogate pixel with floating diffusion output was used with the modified output circuit shown in Fig. 12(a). In eachcolumn output circuit, a crowbar switch (CB) and two column selection SW1S on either side (Si and S2) were added toselectively short the two sample..and-hold capacitors CS and cR. The image senr is operated as described previously up tothe sampling of the reset and signal levels onto the two sample-and.hold capacitors. However, during the scanning of thecolumns, an additiOnal step is performed. Aft& differentially reading out the reset level and signal level stored in eachcolumn (zM), the crowbar switch is pulsed, thereby shorting the two sample..andhold capacitors in the column that is beingaddressed. The outputs of the reset and signal branches are again read out differentially and this reference level (2) is

Fig. 12(a): CMOS APS unit cell and crowbar relout circuit Fig. 12(b): liming for crowbar readout

SPIE Vol. 2172 /27

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