snx5hvd308xe low-power rs-485 transceivers, available ...r t r t r a b r re de d d r a b r re de d d...

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

SN65HVD3082E, SN75HVD3082E, SN65HVD3085E, SN65HVD3088ESLLS562J –AUGUST 2009–REVISED OCTOBER 2017

SNx5HVD308xE Low-Power RS-485 Transceivers, Available in a Small MSOP-8 Package

1

1 Features1• Available in a Small MSOP-8 Package• Meets or Exceeds the Requirements of the

TIA/EIA-485A Standard• Low Quiescent Power

– 0.3-mA Active Mode– 1-nA Shutdown Mode

• 1/8 Unit Load up to 256 Nodes on a Bus• Bus-Pin ESD Protection up to 15 kV• Industry-Standard SN75176 Footprint• Failsafe Receiver (Bus Open, Bus Shorted,

Bus Idle)• Glitch-Free Power-Up and Power-Down Bus

Inputs and Outputs

2 Applications• Energy Meter Networks• Motor Control• Power Inverters• Industrial Automation• Building Automation Networks• Battery-Powered Applications• Telecommunications Equipment

3 DescriptionThe SNx5HVD308xE devices are half-duplextransceivers designed for RS-485 data bus networks.Powered by a 5-V supply, they are fully compliantwith TIA/EIA-485A standard. With controlled transitiontimes, these devices are suitable for transmitting dataover long twisted-pair cables. SN65HVD3082E andSN75HVD3082E devices are optimized for signalingrates up to 200 kbps. The SN65HVD3085E device issuitable for data transmission up to 1 Mbps, whereasthe SN65HVD3088E device is suitable forapplications that require signaling rates up to20 Mbps.

These devices are designed to operate with very lowsupply current, typically 0.3 mA, exclusive of the load.When in the inactive-shutdown mode, the supplycurrent drops to a few nanoamps, which makes thesedevices ideal for power-sensitive applications.

The wide common-mode range and high ESD-protection levels of these devices makes themsuitable for demanding applications such as energymeter networks, electrical inverters, status andcommand signals across telecom racks, cabledchassis interconnects, and industrial automationnetworks where noise tolerance is essential. Thesedevices match the industry-standard footprint of theSN75176 device. Power-on-reset circuits keep theoutputs in a high-impedance state until the supplyvoltage has stabilized. A thermal-shutdown functionprotects the device from damage due to system faultconditions. The SN75HVD3082E is characterized foroperation from 0°C to 70°C and SN65HVD308xE arecharacterized for operation from –40°C to 85°C airtemperature. The D package version of theSN65HVD3082E has been characterized foroperation from –40°C to 105°C.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

SN65HVD3082ESN65HVD3088E

SOIC (8) 4.90 mm × 3.91 mmVSSOP (8) 3.00 mm × 3.00 mmPDIP (8) 9.81 mm × 6.35 mm

SN75HVD3082ESN65HVD3085E

SOIC (8) 4.90 mm × 3.91 mmVSSOP (8) 3.00 mm × 3.00 mm

(1) For all available packages, see the orderable addendum atthe end of the data sheet.

Simplified Schematic

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SN65HVD3082E, SN75HVD3082E, SN65HVD3085E, SN65HVD3088ESLLS562J –AUGUST 2009–REVISED OCTOBER 2017 www.ti.com

Product Folder Links: SN65HVD3082E SN75HVD3082E SN65HVD3085E SN65HVD3088E

Submit Documentation Feedback Copyright © 2009–2017, Texas Instruments Incorporated

Table of Contents1 Features .................................................................. 12 Applications ........................................................... 13 Description ............................................................. 14 Revision History..................................................... 25 Pin Configuration and Functions ......................... 36 Specifications......................................................... 3

6.1 Absolute Maximum Ratings ...................................... 36.2 ESD Ratings.............................................................. 36.3 Recommended Operating Conditions....................... 46.4 Thermal Information ................................................. 46.5 Electrical Characteristics: Driver ............................... 56.6 Electrical Characteristics: Receiver ......................... 56.7 Power Characteristics ............................................... 66.8 Switching Characteristics: Driver .............................. 66.9 Switching Characteristics: Receiver.......................... 76.10 Typical Characteristics ............................................ 8

7 Parameter Measurement Information ................ 108 Detailed Description ............................................ 14

8.1 Overview ................................................................. 148.2 Functional Block Diagram ....................................... 14

8.3 Feature Description................................................. 148.4 Device Functional Modes........................................ 14

9 Application and Implementation ........................ 169.1 Application Information............................................ 169.2 Typical Application ................................................. 16

10 Power Supply Recommendations ..................... 2011 Layout................................................................... 20

11.1 Layout Guidelines ................................................. 2011.2 Layout Example .................................................... 2011.3 Thermal Considerations for IC Packages ............. 21

12 Device and Documentation Support ................. 2212.1 Device Support...................................................... 2212.2 Related Links ........................................................ 2212.3 Receiving Notification of Documentation Updates 2212.4 Community Resources.......................................... 2212.5 Trademarks ........................................................... 2212.6 Electrostatic Discharge Caution............................ 2212.7 Glossary ................................................................ 22

13 Mechanical, Packaging, and OrderableInformation ........................................................... 23

4 Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision I (September 2016) to Revision J Page

• Changed 3.3 V to 5 V on the VCC pin in Figure 25............................................................................................................... 18

Changes from Revision H (August 2015) to Revision I Page

• Added text to the Description, "The D package version of the SN65HVD3082E has been characterized for operationfrom -40°C to 105°C."............................................................................................................................................................. 1

• Changed the Operating free-air temperature for SN65HVD3082E (D package) From: MAX = 85°C To: 105°C inRecommended Operating Conditions ................................................................................................................................... 4

Changes from Revision G (May 2009) to Revision H Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device FunctionalModes, Application and Implementation section, Power Supply Recommendations section, Layout section, Deviceand Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

• Deleted Dissipation Ratings table .......................................................................................................................................... 1• Added storage temperature Tstg to Absolute Maximum Ratings table ................................................................................... 3• Deleted Package Thermal Information table ......................................................................................................................... 6

Changes from Revision F (March 2009) to Revision G Page

• Added Graph - Driver Rise and Fall Time vs Temperature.................................................................................................... 8• Added IDLE Bus to the Function Table ................................................................................................................................ 14• Added Receiver Failsafe section .......................................................................................................................................... 18





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DE

RE

8

D 5

6

7

R VCC

GND

1

4

3

2

A

B

3

SN65HVD3082E, SN75HVD3082E, SN65HVD3085E, SN65HVD3088Ewww.ti.com SLLS562J –AUGUST 2009–REVISED OCTOBER 2017


Submit Documentation FeedbackCopyright © 2009–2017, Texas Instruments Incorporated

5 Pin Configuration and Functions

D, P, and DGK Packages8-Pin SOIC, VSSOP, and PDIP

Top View

Pin FunctionsPIN

TYPE DESCRIPTIONNAME NO.A 6 Bus input/output Driver output or receiver input (complementary to B)B 7 Bus input/output Driver output or receiver input (complementary to A)D 4 Digital input Driver data inputDE 3 Digital input Driver enable, active highGND 5 Reference potential Local device groundR 1 Digital output Receive data outputRE 2 Digital input Receiver enable, active lowVCC 8 Supply 4.5-V to 5.5-V supply

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under Recommended OperatingConditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.

6 Specifications

6.1 Absolute Maximum Ratingsover operating free-air temperature range unless otherwise noted (1) (2)

MIN MAX UNITSupply voltage, VCC –0.5 7 VVoltage at A or B –9 14 VVoltage at any logic pin –0.3 VCC + 0.3 VReceiver output current –24 24 mAVoltage input, transient pulse, A and B, through 100 Ω (see Figure 20) –50 50 VJunction Temperature, TJ 170 °CStorage temperature, Tstg 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.(3) Tested in accordance with IEC 61000-4-4.

6.2 ESD RatingsVALUE UNIT

V(ESD)Electrostaticdischarge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)

Bus pins and GND ±15000

VAll pins ±4000

Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000Electrical Fast Transient/Burst, A, B, and GND (3) ±4000





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4




(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.

6.3 Recommended Operating Conditionsover operating free-air temperature range unless otherwise noted (1)

MIN NOM MAX UNITSupply voltage, VCC 4.5 5.5

VVoltage at any bus terminal (separately or common mode) , VI –7 12High-level input voltage (D, DE, or RE inputs), VIH 2 VCC VLow-level input voltage (D, DE, or RE inputs), VIL 0 0.8 VDifferential input voltage, VID –12 12 V

Output current, IODriver –60 60

mAReceiver –8 8

Differential load resistance, RL 54 60 Ω

Signaling rate, 1/tUI

SN65HVD3082E, SN75HVD3082E 0.2MbpsSN65HVD3085E 1

SN65HVD3088E 20

Operating free-air temperature, TA

SN65HVD3082E (D package) –40 105

°CSN65HVD3082E (DGK and P packages),SN65HVD3085E, SN65HVD3088E –40 85

SN75HVD3082E 0 70Junction temperature, TJ –40 130 °C

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics applicationreport, SPRA953.

6.4 Thermal Information

THERMAL METRIC (1)

SN65HVD3082E, SN75HVD3082E,SN65HVD3085E, SN65HVD3088E

SN65HVD3082E,SN65HVD3088E

UNITD (SOIC) DGK (VSSOP) P (PDIP)8 PINS 8 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 130 180 70 °C/WRθJC(top) Junction-to-case (top) thermal resistance 80 66 80 °C/WRθJB Junction-to-board thermal resistance 55 110 40 °C/WψJT Junction-to-top characterization parameter 7.9 4.6 17.6 °C/WψJB Junction-to-board characterization parameter 47 73.1 28.3 °C/W





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http://www.ti.com/lit/pdf/spra953

5




(1) All typical values are at 25°C and with a 5-V supply.

6.5 Electrical Characteristics: Driverover recommended operating conditions unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT

|VOD| Differential output voltage

IO = 0, No Load 3 4.3

VRL = 54 Ω (see Figure 8) 1.5 2.3RL = 100 Ω 2VTEST = –7 V to 12 V (see Figure 9) 1.5

Δ|VOD| Change in magnitude of differentialoutput voltage See Figure 8 and Figure 9 –0.2 0 0.2 V

VOC(SS)Steady-state common-mode outputvoltage

See Figure 101 2.6 3

VΔVOC(SS)

Change in steady-state common-modeoutput voltage –0.1 0 0.1

VOC(PP)Peak-to-peak common-mode outputvoltage See Figure 10 500 mV

IOZ High-impedance output current See receiver input currents in ElectricalCharacteristics: Receiver

II Input current D, DE –100 100 µAIOS Short-circuit output current −7 V ≤ VO ≤ 12 V (see Figure 14) –250 250 mA


6.6 Electrical Characteristics: Receiverover recommended operating conditions unless otherwise noted


VIT+Positive-going differential input thresholdvoltage IO = –8 mA –85 –10 mV

VIT–Negative-going differential input thresholdvoltage IO = 8 mA –200 –115 mV

Vhys Hysteresis voltage (VIT+ – VIT–) 30 mVVOH High-level output voltage VID = 200 mV, IOH = –8 mA (see Figure 15) 4 4.6 VVOL Low-level output voltage VID = –200 mV, IO = 8 mA (see Figure 15) 0.15 0.4 VIOZ High-impedance-state output current VO = 0 or VCC, RE = VCC –1 1 μA

II Bus input current

VIH = 12 V, VCC = 5 V 0.04 0.1

mAVIH = 12 V, VCC = 0 V 0.06 0.125VIH = –7 V, VCC = 5 V –0.1 –0.04VIH = –7 V, VCC = 0 V –0.05 –0.03

IIH High-level input current, (RE) VIH = 2 V –60 –30 μAIIL Low-level input current, (RE) VIL = 0.8 V –60 –30 μACdiff Differential input capacitance VI = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V 7 pF





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6





6.7 Power Characteristicsover operating free-air temperature range (unless otherwise noted)


ICC

Driver and receiver enabled D at VCC or open, DE at VCC,RE at 0 V, No load 425 900 µA

Driver enabled, receiverdisabled

D at VCC or open, DE at VCC,RE at VCC, No load 330 600 µA

Receiver enabled, driverdisabled

D at VCC or open, DE at 0 V,RE at 0 V, No load 300 600 µA

Driver and receiver disabled D at VCC or open, DE at 0 V,RE at VCC

0.001 2 µA

P(AVG) Average power dissipation

Input to D is a 50% dutycycle square wave at maxspecified signal rateRL = 54 Ω VCC = 5.5 V, TJ =130°C

ALL HVD3082E 203

mWALL HVD3085E 205

ALL HVD3088E 276

6.8 Switching Characteristics: Driverover recommended operating conditions unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

tPLHtPHL

Propagation delay time, low-to-high-level outputPropagation delay time, high-to-low-level output

RL = 54 Ω, CL = 50 pF(see Figure 11)

HVD3082E 700 1300nsHVD3085E 150 500

HVD3088E 12 20

trtf

Differential output signal rise timeDifferential output signal fall time

RL = 54 Ω, CL = 50 pF(see Figure 11)

HVD3082E 500 900 1500nsHVD3085E 200 300

HVD3088E 7 15

tsk(p) Pulse skew (|tPHL – tPLH|) RL = 54 Ω, CL = 50 pF(see Figure 11)

HVD3082E 20 200nsHVD3085E 5 50

HVD3088E 1.4 2

tPZHtPZL

Propagation delay time, high-impedance-to-high-level outputPropagation delay time, high-impedance-to-low-level output

RL = 110 Ω, RE at 0 V(see Figure 12 andFigure 13)

HVD3082E 2500 7000

nsHVD3085E 1000 2500

HVD3088E 13 30

tPHZtPLZ

Propagation delay time, high-level-to-high-impedance outputPropagation delay time, low-level-to-high-impedance output

RL = 110 Ω, RE at 0 V(see Figure 12 andFigure 13)

HVD3082E 80 200

nsHVD3085E 60 100

HVD3088E 12 30

tPZH(SHDN)tPZL(SHDN)

Propagation delay time, shutdown-to-high-leveloutputPropagation delay time, shutdown-to-low-leveloutput

RL = 110 Ω, RE at VCC(see Figure 12)

HVD3082E 3500 7000

nsHVD3085E 2500 4500

HVD3088E 1600 2600





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6.9 Switching Characteristics: Receiverover recommended operating conditions unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

tPLHPropagation delay time, low-to-high-level output

CL = 15 pF (seeFigure 16)

HVD3082EHVD3085E 75 200

nsHVD3086E 100

tPHLPropagation delay time, high-to-low-level output

HVD3082EHVD3085E 79 200

nsHVD3088E 100

tsk(p) Pulse skew (|tPHL – tPLH|)HVD3082EHVD3085E 4 30

nsHVD3088E 10

tr Output signal rise time VID = –1.5 V to 1.5 V,CL = 15 pF (see Figure 16)

1.5 3 nstf Output signal fall time 1.8 3 ns

tPZH Output enable time to high level

CL = 15 pF,DE at 3 V(see Figure 17 andFigure 18)

HVD3082EHVD3085E 5 50

nsHVD3088E 30

tPZL Output enable time to low levelHVD3082EHVD3085E 10 50

nsHVD3088E 30

tPHZ Output enable time from high levelHVD3082EHVD3085E 5 50

nsHVD3088E 30

tPLZ Output disable time from low levelHVD3082EHVD3085E 8 50

nsHVD3088E 30

tPZH(SHDN)Propagation delay time,shutdown-to-high-level output CL = 15 pF, DE at 0 V,

(see Figure 19)

1600 3500 ns

tPZL(SHDN)Propagation delay time,shutdown-to-low-level output 1700 3500 ns





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RL = 120W

RL = 60W

T = 25 C

V = 5 VA

CC

o

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

0 10 20 30 40 50

IO - Differential Output Current - mA

VO

D-

Dif

fere

nti

al O

utp

ut

Vo

ltag

e -

V

00

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

VID - Differential Input Voltage - V

VO

- R

eceiv

er

Ou

tpu

t V

olt

ag

e -

V

T = 25 C

V = 5 V

V = 0.75 V

A

CC

IC

o

-200 -180 -160 -140 -120 -100 -80 -60 -40 -20

0.1

1000

Signal Rate - kbps

I CC

- S

up

ply

Cu

rre

nt

- m

A

100

1

10 100

Receiver Only

Driver and Receiver

No Load,V = 5 V,

T = 25 C

50% Square Wave Input

CC

Ao

1

10

No Load,V = 5 V,

T = 25 C


CC

Ao

Receiver Only

Driver and Receiver

0.1

I CC

- S

up

ply

Cu

rre

nt

- m

A

100

1

10

-60

-40

-20

0

20

40

60

-8 -6 -4 -2 0 2 4 6 8 12

VCC = 5 V

VCC = 0 V

VI - Bus Input Voltage - V

I I-

Inp

ut

Bia

s C

urr

en

t -

Am

80

10

Receiver Only

Driver and Receiver

No Load,V = 5 V,

T = 25 C


CC

Ao

100

Signal Rate - kbps

1 100.1

I CC

- S

up

ply

Cu

rren

t -

mA

1

10

8




6.10 Typical Characteristics

Figure 1. Bus Input Currentversus Bus Input Voltage

Figure 2. SN65HVD3082E RMS Supply Currentversus Signaling Rate

Figure 3. SN65HVD3085E RMS Supply Currentversus Signaling Rate

Figure 4. SN65HVD3088E RMS Supply Currentversus Signal Rate

Figure 5. Driver Differential Output Voltageversus Driver Output Current

Figure 6. Receiver Output Voltageversus Differential Input Voltage





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580

6

7

8

9

10

TA - Temperature - Co

Ris

e/F

all T

ime -

ns

-40 -20 0 20 40 60

V = 4.5 VCC

V = 5 VCC

V = 5.5 VCC

9




Typical Characteristics (continued)

Figure 7. SN65HVD3088E Driver Rise and Fall Timeversus Temperature





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1.5 V

50 WOutput

VOD(L)

tPLH

tf

C = 50 pFL

R = 50L W

SignalGenerator

0 V

0 V10%

VOD

Input1.5 V

3 V

VOD(H)90%

tPHL

tr

-1.75 V

50 WSignal

Generator VOC

VOC

DVOC(SS)50 pF

27 W

BVB

A

27 W

VA -3.25 V

VOC(PP)

0 V or 3 V60 W

375 WIOB

VOD

IOA

VTEST

= -7 V to 12 V

375 W

VTEST

0 V or 3 V 50 pF

27 WB IOB

VOD

VOC

IOAII

A 27 W

10




7 Parameter Measurement InformationTest load capacitance includes probe and jig capacitance (unless otherwise specified). Signal generatorcharacteristics: rise and fall time < 6 ns, pulse rate 100 kHz, 50% duty cycle. ZO = 50 Ω (unless otherwisespecified).

Figure 8. Driver Test Circuit, VOD and VOC Without Common-Mode Loading

Figure 9. Driver Test Circuit, VOD With Common-Mode Loading

Figure 10. Driver VOC Test Circuit and Waveforms

Figure 11. Driver Switching Test Circuit and Waveforms





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50 W C = 15 pFL

Input A

1.5 V

B

VID

SignalGenerator

SignalGenerator

AR

tPHL

0 V

VOL

IO

VO

50 W

Output

Input B

VOH

10%

tPLH

tf

50%

90%

tr

VoltageSource

VO

IOS

VID

IO

VO

1.5 V

R = 110L W

SignalGenerator

5 V

S1

DE0 V or 3 V0 V if Testing A Output3 V if Testing B Output

2.5 V

D

DE

Output1.5 V

tPLZ

0.5 V

50 W

C = 50 pFL

B

A3 V

5 V

0 V

VOL

Output

tPZL

V 0Off

SignalGenerator 50 W

R = 110L WC = 50 pFL

S1

0 V or 3 V3 V if Testing A Output0 V if Testing B Output

B

DA

DE

Output

1.5 VDE

Output

3 V

tPHZ

VOH

0 V

2.5 V

1.5 V

tPZH0.5 V

11




Parameter Measurement Information (continued)

Figure 12. Driver Enable and Disable Test Circuit and Waveforms, High Output

Figure 13. Driver Enable and Disable Test Circuit and Waveforms, Low Output

Figure 14. Driver Short-Circuit Figure 15. Receiver Switching Test Circuit andWaveforms

Figure 16. Receiver Switching Test Circuit and Waveforms





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1.5 V

50 W

1 kW

C = 15 pFL

Switch Down for V = 1.5 V(A)

Switch Up for V = -1.5 V(A)

SignalGenerator

0 V

R

R

A

RE

RE1.5 V

1.5 V or-1.5 V 3 V

B

tPZH(SHDN)

tPZL(SHDN)

VCC

VOL

VOH

0 V

5 V

54 W

VCC

tPLZ

V +0.5 VOH

5 VR

A

DE

VOL

SignalGenerator

B

0 V D

50 W

RE

1 kW

C = 15 pFL

R

RE

0 V

3 V

VCC

1.5 V

1.5 V

tPZL

50 W

54 W

A

RE

SignalGenerator

B

VCCDE

VCCD

1 kW

C = 15 pFL

0 VR

1.5 V

GND

tPHZ

V -0.5 VOH

0 V

R

RE1.5 V

3 V

VOH

tPZH

12





Figure 17. Receiver Enable and Disable Test Circuit and Waveforms, Data Output High

Figure 18. Receiver Enable and Disable Test Circuit and Waveforms, Data Output Low

Figure 19. Receiver Enable From Shutdown Test Circuit and Waveforms





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500 W

16 V

Input

D and RE Input

500 W

9 V

VCC

Input

R Output

50 kW

50 kW

180 kW

36 kW

VCC

DE Input

A and B Output

VCC

VCC

Input

Output

9 V

9 V

16 V

36 kW

16 V

5 W

16 V

36 kW

B InputA Input

VCC

16 V

16 V

Input

VCC

Output

180 kW

36 kW

100 W

0 V

Pulse Generator,

15 s Duration,1% Duty Cycle

m -VTEST

VTEST

15 ms15 sm

13





Figure 20. Test Circuit and Waveforms, Transient Overvoltage Test

Figure 21. Equivalent Input and Output Schematic Diagrams





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R

D

DE

RE

B

A

GND

VCC

14




(1) H = high level, L = low level, Z = high impedance, X = irrelevant, ? = indeterminate

8 Detailed Description

8.1 OverviewThe SNx5HVD308xE family of half-duplex RS-485 transceivers is suitable for data transmission at rates up to200 kbps (for SN65HVD3082E and SN75HVD3082E), 1 Mbps (for SN65HVD3085E), or 20 Mbps (forSN65HVD3088E) over controlled-impedance transmission media (such as twisted-pair cabling). Up to 256 unitsof SNx5HVD308xE may share a common RS-485 bus due to the family’s low bus input currents. The devicesalso feature a high degree of ESD protection and typical standby current consumption of 1 nA.

8.2 Functional Block Diagram

8.3 Feature DescriptionThe SNx5HVD308xE provides internal biasing of the receiver input thresholds for open-circuit, bus-idle, or short-circuit failsafe conditions. It features a typical hysteresis of 30 mV in order to improve noise immunity. InternalESD protection circuits protect the transceiver bus terminals against ±15-kV Human Body Model (HBM)electrostatic discharges.

The devices protect themselves against damage due to overtemperature conditions through use a of a thermalshutdown feature. Thermal shutdown is entered at 165°C (nominal) and causes the device to enter a low-powerstate with high-impedance outputs.

8.4 Device Functional ModesWhen the driver enable pin, DE, is logic high, the differential outputs A and B follow the logic states at data inputD. A logic high at D causes A to turn high and B to turn low. In this case the differential output voltage defined asVOD = VA – VB is positive. When D is low, the output states reverse, B turns high, A becomes low, and VOD isnegative.

When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant. The DE pinhas an internal pull-down resistor to ground, thus when left open the driver is disabled (high-impedance) bydefault. The D pin has an internal pull-up resistor to VCC, thus, when left open while the driver is enabled, outputA turns high and B turns low.

Table 1. Driver Function TableINPUT ENABLE (1) OUTPUTS (1)

FUNCTIOND DE A BH H H L Actively drive bus HighL H L H Actively drive bus LowX L Z Z Driver disabledX OPEN Z Z Driver disabled by default

OPEN H H L Actively drive bus High by default





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15




When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltagedefined as VID = VA – VB is positive and higher than the positive input threshold, VIT+, the receiver output, R,turns high. When VID is negative and lower than the negative input threshold, VIT–, the receiver output, R, turnslow. If VID is between VIT+ and VIT– the output is indeterminate.

When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VIDare irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver isdisconnected from the bus (open-circuit), the bus lines are shorted (short-circuit), or the bus is not actively driven(idle bus).

Table 2. Receiver Function TableDIFFERENTIAL INPUT ENABLE OUTPUT

FUNCTIONVID = VA – VB RE R

VIT+ < VID L H Receive valid bus HighVIT– < VID < VIT+ L ? Indeterminate bus state

VID < VIT– L L Receive valid bus LowX H Z Receiver disabledX OPEN Z Receiver disabled by default

Open-circuit bus L H Fail-safe high outputShort-circuit bus L H Fail-safe high output

Idle (terminated) bus L H Fail-safe high output





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RT RT

R

A B

R RE DE D

DR

A B

R RE DE D

D

R

D

R

RE

DE

D

A

B

R

D

R

RE

DE

D

A

B

R

D

R

RE

DE

D

A

B

R

D

R

RE

DE

D

A

B

R

D

R

RE

DE

D

A

B

16




9 Application and Implementation

NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.

9.1 Application InformationThe SNx5HVD308xE devices are half-duplex RS-485 transceivers commonly used for asynchronous datatransmissions. The driver and receiver enable pins allow for the configuration of different operating modes.

Figure 22. Half-Duplex Transceiver Configurations

Using independent enable lines provides the most flexible control as it allows for the driver and the receiver to beturned on and off individually. While this configuration requires two control lines, it allows for selective listeninginto the bus traffic whether the driver is transmitting data or not.

Combining the enable signals simplifies the interface to the controller by forming a single direction-control signal.In this configuration, the transceiver operates as a driver when the direction-control line is high and as a receiverwhen the direction-control line is low.

Additionally, only one line is required when connecting the receiver-enable input to ground and controlling onlythe driver-enable input. In this configuration, a node not only receives the data from the bus, but also the data itsends and can verify that the correct data have been transmitted.

9.2 Typical ApplicationAn RS-485 bus consists of multiple transceivers connecting in parallel to a bus cable. To eliminate linereflections, each cable end is terminated with a termination resistor, RT, whose value matches the characteristicimpedance, Z0, of the cable. This method, known as parallel termination, allows for higher data rates over longercable length.

Figure 23. Typical Application Circuit





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10000

1000

100

10

Cab

le L

en

gth

(ft

)

100 1k 10k 100k 1M 10M 100M

Data Rate (bps)

Conservative

Characteristics

5%, 10%, and 20% Jitter

17




Typical Application (continued)9.2.1 Design RequirementsRS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range ofapplications with varying requirements, such as distance, data rate, and number of nodes.

9.2.1.1 Data Rate and Bus LengthThere is an inverse relationship between data rate and bus length, meaning the higher the data rate, the shorterthe cable length; and conversely, the lower the data rate, the longer the cable may be without introducing dataerrors. While most RS-485 systems use data rates between 10 kbps and 100 kbps, some applications requiredata rates up to 250 kbps at distances of 4,000 feet and longer. Longer distances are possible by allowing forsmall signal jitter of up to 5 or 10%.

Figure 24. Cable Length vs Data Rate Characteristic

9.2.1.2 Stub LengthWhen connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known asthe stub, must be as short as possible. Stubs present a non-terminated piece of bus line which can introducereflections as the length of the stub increases. As a general guideline, the electrical length, or round-trip delay, ofa stub must be less than one-tenth of the rise time of the driver, thus giving a maximum physical stub length asshown in Equation 1.

Lstub ≤ 0.1 × tr × v × c

where:• tr is the 10/90 rise time of the driver• c is the speed of light (3 × 108 m/s)• v is the signal velocity of the cable or trace as a factor of c (1)

9.2.1.3 Bus LoadingThe RS-485 standard specifies that a compliant driver must be able to driver 32 unit loads (UL), where 1 unitload represents a load impedance of approximately 12 kΩ. Because the SNx5HVD308xE is a 1/8 UL transceiver,it is possible to connect up to 256 receivers to the bus.





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5 V

VCC

GND

D

DE

R

RE

B

A

RxD

TxD

DIR

MCU/

UART

10 kΩ

10 kΩ

TVS

R2

R1

100 nF100 nF

Copyright © 2017, Texas Instruments Incorporated

18




Typical Application (continued)9.2.1.4 Receiver Failsafe

The differential receiver is fail-safe to invalid bus states caused by:• open bus conditions such as a disconnected connector,• shorted bus conditions such as cable damage shorting the twisted-pair together, or• idle bus conditions that occur when no driver on the bus is actively drivingIn any of these cases, the differential receiver outputs a failsafe logic High state, so that the output of thereceiver is not indeterminate.

Receiver failsafe is accomplished by offsetting the receiver thresholds so that the input indeterminate range doesnot include zero volts differential. To comply with the RS-422 and RS-485 standards, the receiver output mustoutput a High when the differential input VID is more positive than +200 mV, and must output a Low when the VIDis more negative than –200 mV. The receiver parameters which determine the failsafe performance are VIT+ andVIT– and VHYS. As seen in the table, differential signals more negative than –200 mV will always cause a Lowreceiver output. Similarly, differential signals more positive than +200 mV will always cause a High receiveroutput.

When the differential input signal is close to zero, it will still be above the VIT+ threshold, and the receiver outputis High. Only when the differential input is more negative than VIT– will the receiver output transition to a Lowstate. So, the noise immunity of the receiver inputs during a bus fault condition includes the receiver hysteresisvalue VHYS (the separation between VIT+ and VIT– ) as well as the value of VIT+.

9.2.2 Detailed Design ProcedureIn order to protect bus nodes against high-energy transients, the implementation of external transient protectiondevices is necessary.

Figure 25. Transient Protection Against ESD, EFT, and Surge Transients

Figure 25 suggests a protection circuit against 10-kV ESD (IEC 61000-4-2), 4-kV EFT (IEC 61000-4-4), and 1-kVsurge (IEC 61000-4-5) transients. Table 3 shows the associated Bill of Materials.

Table 3. Bill of MaterialsDEVICE FUNCTION ORDER NUMBER MANUFACTURER

XCVR RS-485 Transceiver SNx5HVD308xE TIR1, R2 10-Ω, Pulse-Proof Thick-Film Resistor CRCW060310RJNEAHP VishayTVS Bidirectional 400-W Transient Suppressor CDSOT23-SM712 Bourns





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19




9.2.2.1 Power Usage in an RS-485 TransceiverPower consumption is a concern in many applications. Power supply current is delivered to the bus load as wellas to the transceiver circuitry. For a typical RS-485 bus configuration, the load that an active driver must driveconsists of all of the receiving nodes, plus the termination resistors at each end of the bus.

The load presented by the receiving nodes depends on the input impedance of the receiver. The TIA/EIA-485-Astandard defines a unit load as allowing up to 1 mA. With up to 32 unit loads allowed on the bus, the total currentsupplied to all receivers can be as high as 32 mA. The HVD308xE is rated as a 1/8 unit load device. As shownin , the bus input current is less than 1/8 mA, allowing up to 256 nodes on a single bus.

The current in the termination resistors depends on the differential bus voltage. The standard requires activedrivers to produce at least 1.5 V of differential signal. For a bus terminated with one standard 120-Ω resistor ateach end, this sums to 25 mA differential output current whenever the bus is active. Typically the HVD308xE candrive more than 25-mA to a 60-Ω load, resulting in a differential output voltage higher than the minimum requiredby the standard (see Figure 3).

Overall, the total load current can be 60 mA to a loaded RS-485 bus. This is in addition to the current required bythe transceiver itself; the HVD308xE circuitry requires only about 0.4 mA with both driver and receiver enabled,and only 0.3 mA with either the driver enabled or with the receiver enabled. In low-power shutdown mode,neither the driver nor receiver is active, and the supply current is low.

Supply current increases with signaling rate primarily due to the totem pole outputs of the driver (see Figure 2).When these outputs change state, there is a moment when both the high-side and low-side output transistors areconducting and this creates a short spike in the supply current. As the frequency of state changes increases,more power is used.

9.2.2.2 Low-Power Shutdown ModeWhen both the driver and receiver are disabled (DE low and RE high) the device is in shutdown mode. If theenable inputs are in this state for less than 60 ns, the device does not enter shutdown mode. This guards againstinadvertently entering shutdown mode during driver or receiver enabling. Only when the enable inputs are held inthis state for 300 ns or more, the device is assured to be in shutdown mode. In this low-power shutdown mode,most internal circuitry is powered down, and the supply current is typically 1 nA. When either the driver or thereceiver is re-enabled, the internal circuitry becomes active.

If only the driver is re-enabled (DE transitions to high) the driver outputs are driven according to the D input afterthe enable times given by tPZH(SHDN) and tPZL(SHDN) in the driver switching characteristics. If the D input is openwhen the driver is enabled, the driver outputs defaults to A high and B low, in accordance with the driver failsafefeature.

If only the receiver is re-enabled (RE transitions to low) the receiver output is driven according to the state of thebus inputs (A and B) after the enable times given by tPZH(SHDN) and tPZL(SHDN) in the receiver switchingcharacteristics. If there is no valid state on the bus the receiver responds as described in the failsafe operationsection.

If both the receiver and driver are re-enabled simultaneously, the receiver output is driven according to the stateof the bus inputs (A and B) and the driver output is driven according to the D input.

NOTEThe state of the active driver affects the inputs to the receiver. Therefore, the receiveroutputs are valid as soon as the driver outputs are valid.





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MCU

R

R

Via to ground

SN65HVD3082E

JM

P

R

R

R

C

5

6

6

1

4R

5

Via to VCC

TVS

75

20




10 Power Supply RecommendationsTo ensure reliable operation at all data rates and supply voltages, each supply must be decoupled with a 100-nFceramic capacitor located as close to the supply pins as possible. This helps to reduce supply voltage ripplepresent on the outputs of switched-mode power supplies and also helps to compensate for the resistance andinductance of the PCB power planes.

11 Layout

11.1 Layout GuidelinesRobust and reliable bus node design often requires the use of external transient protection devices in order toprotect against EFT and surge transients that may occur in industrial environments. Because these transientshave a wide frequency bandwidth (from approximately 3 MHz to 3 GHz), high-frequency layout techniques mustbe applied during PCB design.• Place the protection circuitry close to the bus connector to prevent noise transients from entering the board.• Use VCC and ground planes to provide low-inductance.

NOTEHigh-frequency currents follow the path of least inductance and not the path of leastimpedance.

• Design the protection components into the direction of the signal path. Do not force the transients currents todivert from the signal path to reach the protection device.

• Apply 100-nF to 220-nF bypass capacitors as close as possible to the VCC pins of transceiver, UART, andcontroller ICs on the board.

• Use at least two vias for VCC and ground connections of bypass capacitors and protection devices tominimize effective via-inductance.

• Use 1-kΩ to 10-kΩ pullup or pulldown resistors for enable lines to limit noise currents in these lines duringtransient events.

• Insert series pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than thespecified maximum voltage of the transceiver bus pins. These resistors limit the residual clamping current intothe transceiver and prevent it from latching up.

• While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxidevaristors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transientblocking units (TBUs) that limit transient current to 200 mA.

11.2 Layout Example

Figure 26. SNx5HVD308xE Layout Example





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Junction

PC Board

qJB

Calculated/Measured

Surface Node

Ambient Node

qCA

Calculated

qJC

Calculated/Measured

21




11.3 Thermal Considerations for IC PackagesθJA (Junction-to-Ambient Thermal Resistance) is defined as the difference in junction temperature to ambienttemperature divided by the operating power.

θJA is not a constant and is a strong function of:• the PCB design (50% variation)• altitude (20% variation)• device power (5% variation)

θJA can be used to compare the thermal performance of packages if the specific test conditions are defined andused. Standardized testing includes specification of PCB construction, test chamber volume, sensor locations,and the thermal characteristics of holding fixtures. θJA is often misused when it is used to calculate junctiontemperatures for other installations.

TI uses two test PCBs as defined by JEDEC specifications. The low-k board gives average in-use conditionthermal performance and consists of a single trace layer 25-mm long and 2-oz thick copper. The high-k boardgives best case in-use condition and consists of two 1-oz buried power planes with a single trace layer 25-mmlong with 2-oz thick copper. A 4% to 50% difference in θJA can be measured between these two test cards.

θJC (Junction-to-Case Thermal Resistance) is defined as difference in junction temperature to case divided by theoperating power. It is measured by putting the mounted package up against a copper block cold plate to forceheat to flow from die, through the mold compound into the copper block.

θJC is a useful thermal characteristic when a heatsink is applied to package. It is NOT a useful characteristic topredict junction temperature as it provides pessimistic numbers if the case temperature is measured in a non-standard system and junction temperatures are backed out. It can be used with θJB in 1-dimensional thermalsimulation of a package system.

θJB (Junction-to-Board Thermal Resistance) is defined to be the difference in the junction temperature and thePCB temperature at the center of the package (closest to the die) when the PCB is clamped in a cold-platestructure. θJB is only defined for the high-k test card.

θJB provides an overall thermal resistance between the die and the PCB. It includes a bit of the PCB thermalresistance (especially for BGAs with thermal balls) and can be used for simple 1-dimensional network analysis ofpackage system (see Figure 27).

Figure 27. Thermal Resistance





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22




12 Device and Documentation Support

12.1 Device Support

12.1.1 Third-Party Products DisclaimerTI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOTCONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICESOR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHERALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 Related LinksThe table below lists quick access links. Categories include technical documents, support and communityresources, tools and software, and quick access to sample or buy.

Table 4. Related Links

PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICALDOCUMENTS

TOOLS &SOFTWARE

SUPPORT &COMMUNITY

SN65HVD3082E Click here Click here Click here Click here Click hereSN75HVD3082E Click here Click here Click here Click here Click hereSN65HVD3085E Click here Click here Click here Click here Click hereSN65HVD3088E Click here Click here Click here Click here Click here

12.3 Receiving Notification of Documentation UpdatesTo receive notification of documentation updates, navigate to the device product folder on ti.com. In the upperright corner, click on Alert me to register and receive a weekly digest of any product information that haschanged. For change details, review the revision history included in any revised document.

12.4 Community ResourcesThe following links connect to TI community resources. Linked contents are provided "AS IS" by the respectivecontributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaborationamong engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and helpsolve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools andcontact information for technical support.

12.5 TrademarksE2E is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.

12.6 Electrostatic Discharge CautionThese devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

12.7 GlossarySLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.





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http://www.ti.com/product/SN65HVD3082E?dcmp=dsproject&hqs=sandbuy&#samplebuy

http://www.ti.com/product/SN65HVD3082E?dcmp=dsproject&hqs=td&#doctype2

http://www.ti.com/product/SN65HVD3082E?dcmp=dsproject&hqs=sw&#desKit

http://www.ti.com/product/SN65HVD3082E?dcmp=dsproject&hqs=support&#community











http://www.ti.com/product/SH65HVD3088E?dcmp=dsproject&hqs=pf

http://www.ti.com/product/SH65HVD3088E?dcmp=dsproject&hqs=sandbuy&#samplebuy

http://www.ti.com/product/SH65HVD3088E?dcmp=dsproject&hqs=td&#doctype2

http://www.ti.com/product/SH65HVD3088E?dcmp=dsproject&hqs=sw&#desKit

http://www.ti.com/product/SH65HVD3088E?dcmp=dsproject&hqs=support&#community

http://www.ti.com/corp/docs/legal/termsofuse.shtml

http://www.ti.com/corp/docs/legal/termsofuse.shtml

http://e2e.ti.com

http://support.ti.com/

http://www.ti.com/lit/pdf/SLYZ022

23




13 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.





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PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead finish/Ball material

(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

SN65HVD3082ED ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP3082

SN65HVD3082EDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP3082

SN65HVD3082EDGK ACTIVE VSSOP DGK 8 80 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 NWN

SN65HVD3082EDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 NWN

SN65HVD3082EDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP3082

SN65HVD3082EDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP3082

SN65HVD3082EP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 65HVD3082

SN65HVD3082EPE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 65HVD3082



SN65HVD3085EDGK ACTIVE VSSOP DGK 8 80 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 NWK

SN65HVD3085EDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 NWK




SN65HVD3088EDGK ACTIVE VSSOP DGK 8 80 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 NWH

SN65HVD3088EDGKG4 ACTIVE VSSOP DGK 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 NWH

SN65HVD3088EDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 NWH

SN65HVD3088EDGKRG4 ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 NWH


http://www.ti.com/product/SN65HVD3082E?CMP=conv-poasamples#samplebuy






















Addendum-Page 2

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead finish/Ball material

(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

SN65HVD3088EDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP3088

SN75HVD3082ED ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 VN3082

SN75HVD3082EDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 VN3082

SN75HVD3082EDGK ACTIVE VSSOP DGK 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 NWM

SN75HVD3082EDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green Call TI | NIPDAU Level-1-260C-UNLIM 0 to 70 NWM

SN75HVD3082EDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 VN3082

SN75HVD3082EDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 VN3082

SN75HVD3082EP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 75HVD3082

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.











Addendum-Page 3

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

SN65HVD3082EDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

SN65HVD3082EDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

SN65HVD3082EDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1


SN65HVD3085EDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1


SN65HVD3088EDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

SN75HVD3082EDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 10-Mar-2021

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

SN65HVD3082EDGKR VSSOP DGK 8 2500 350.0 350.0 43.0

SN65HVD3082EDR SOIC D 8 2500 340.5 338.1 20.6

SN65HVD3082EDR SOIC D 8 2500 853.0 449.0 35.0


SN65HVD3085EDR SOIC D 8 2500 340.5 338.1 20.6


SN65HVD3088EDR SOIC D 8 2500 340.5 338.1 20.6

SN75HVD3082EDR SOIC D 8 2500 340.5 338.1 20.6

PACKAGE MATERIALS INFORMATION

www.ti.com 10-Mar-2021

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

C

.228-.244 TYP[5.80-6.19]

.069 MAX[1.75]

6X .050[1.27]

8X .012-.020 [0.31-0.51]

2X.150[3.81]

.005-.010 TYP[0.13-0.25]

0 - 8 .004-.010[0.11-0.25]

.010[0.25]

.016-.050[0.41-1.27]

4X (0 -15 )

A

.189-.197[4.81-5.00]

NOTE 3

B .150-.157[3.81-3.98]

NOTE 4

4X (0 -15 )

(.041)[1.04]

SOIC - 1.75 mm max heightD0008ASMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash.5. Reference JEDEC registration MS-012, variation AA.

18

.010 [0.25] C A B

54

PIN 1 ID AREA

SEATING PLANE

.004 [0.1] C

SEE DETAIL A

DETAIL ATYPICAL

SCALE 2.800

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EXAMPLE BOARD LAYOUT

.0028 MAX[0.07]ALL AROUND

.0028 MIN[0.07]ALL AROUND

(.213)[5.4]

6X (.050 )[1.27]

8X (.061 )[1.55]

8X (.024)[0.6]

(R.002 ) TYP[0.05]


4214825/C 02/2019

NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METALSOLDER MASKOPENING

NON SOLDER MASKDEFINED

SOLDER MASK DETAILS

EXPOSEDMETAL

OPENINGSOLDER MASK METAL UNDER

SOLDER MASK

SOLDER MASKDEFINED

EXPOSEDMETAL

LAND PATTERN EXAMPLEEXPOSED METAL SHOWN

SCALE:8X

SYMM

1

45

8

SEEDETAILS

SYMM

www.ti.com

EXAMPLE STENCIL DESIGN

8X (.061 )[1.55]

8X (.024)[0.6]

6X (.050 )[1.27]

(.213)[5.4]

(R.002 ) TYP[0.05]


4214825/C 02/2019

NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLEBASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

SYMM

SYMM

1

45

8

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