sm3-8r 8 reference stratum 3 module · 17 ref8 reference input 8 – 8 khz to 77.76 mhz auto...

Application

TheSM3-8RTimingModuleisacompletesystemclockmoduleforStratum3timingapplicationsandconformstoGR-1244-CORE(Issue2),GR-253-CORE(Issue3)andITU-TG.812(Option3).Applicationsincludesharedportadapters,datadigitalcrossconnects,ADM’s,DSLAM’s,multiserviceplatforms,switchesandroutersinTDM,SDHandSONETenvironments. TheSM3-8RTimingModuleguaranteesfullStratum3compliancewithaminimumofeffortandcostinthesmallestcompletepackageavailable.

Features SmallPackageSize:

2.05”x1.25”x0.515”

EightAutoSelectInputReferences,8kHz-77.76MHz

FrequencyQualificationandLossofReferencedetectionforeachinput

HitlessReferenceSwitching

Master/SlaveOperationwithPhaseAdjustment

Manual/AutonomousOperation

Bi-DirectionalSPIPortControlandStatusReporting

ThreeCMOSFrequencyOutputs-Output1from1.544-77.76MHz,M/S_Out@8KHz,[email protected]

3.3Voperation

SM3-8R8 REFERENCE

STRATUM 3 MODULE

2111 Comprehensive Drive

Aurora, Illinois 60505

Phone: 630-851-4722

Fax: 630- 851- 5040

www.conwin.com

Bulletin TM059 of 32Revision 05Date 26 Jan 2011IssuedBy ENG

SM3-8R Data Sheet #: TM059 of 32 Rev: 05 Date: 01/26/11

© Copyright 2011 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice

General DescriptionThe SM3-8R timing module provides a clock output that meets or exceeds Stratum 3 specifications given in GR-1244-CORE (Issue 2), GR-253-CORE (Issue 3) and ITU-T G.812 (option 3). The SM3-8R features eight reference inputs. Each input will auto-detect the following reference frequencies: 8 kHz, 1.544 MHz, 2.048 MHz, 12.96 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz and 77.76 MHz. The SM3-8R timing module can be configured during production to produce an output up to 77.76MHz. This output is derived from an onboard VCXO and must be specified when ordering. The second output is a BITS output select-able for either 1.544 or 2.048 MHz. The master/slave output is 8KHz. The user communicates with the SM3-8R module through a SPI port. The user controls the SM3-8R operation by writing to the appropriate registers. The user can also enable or disable SPI operation through a SPI_Enable pin. The SM3-8R offers a wide range of options for the system designer. The bandwidth is SPI Port-selectable from 0.025 Hz to 1.6 Hz. 0.098 Hz is the recommended operational bandwidth for Stratum 3 applications. The 8 kHz output has an adjustable pulse width. The pull-in range is also adjustable to establish the desired reference frequency rejec-tion limits. A Free Run frequency calibration value can be written to the module to provide a high degree of accuracy in the free run mode. The reference frequency for any given reference input is automatically detected. A wealth of status information is available through the SPI Port registers. The user also has a choice between autonomous or full manual control operation. In manual mode, the user controls the module operating modes Free Run, Hold Over or locked to a specific refer-ence. If the chosen reference is unavailable or disqualified the module automatically enters Hold Over. In autonomous control mode, operational mode selection occurs automatically based on reference priority and qualification status. When the active reference becomes disqualified, the module will switch to another qualified refer-ence. If none is available, it will switch to Hold Over. In the revertive mode the module will seek to acquire the highest priority qualified reference. In the non-revertive mode the module will not return to the previous reference even after it is re-qualified unless there are no other qualified references. Switching between references is hitless. Likewise, the output frequency slew rate is minimized during any change of op-erating mode, including entry into and return from Free Run or Holdover to protect traffic from transient-induced bit errors. Reference Status information and the operating mode information is accessed through status registers. The module will set the Interrupt pin (SPI_INT) low to indicate a status change. Free Run operation guarantees an output within 4.6ppm of nominal frequency and Hold Over operation guarantees the output frequency will not change by more than 0.37ppm during the first 24 hours. Frequency accuracy is based on a precision oven to provide the stabilty required for Stratum 3 compliance. The SM3-8R can be programmed to startup in any mode or bandwidth. The module may even be programmed to operate in an a fully autonomous mode with no further configuration required. The module operates on 3.3V ± 5% with a typical power drain of less than 1.6W at turn on, dropping to approximately 1W @ room temperature after warming up. The module operates over the 0° to 70° C commercial temperature range. Phase buildout can be enabled or disabled by means of the SPI port.

Functional Block DiagramFigure 1

Reference Input Monitor

ControlMode

ReferenceSelection DPLL APLL

Reference Priority, Revertivity and Mask

Table

Bus Interface

EEPROM DACOCXO VCXO

TRST

TCK

TDO

TDI

TMS

M/S REF

Ref 1 - 8

Reset

MASTER SELECT

T1/E1

SPI_ENBL

SPI_Clk

SPI_In

SPI_Out

SPI_INT

8

Output 1

M/S_OUT

BITS_Clk

LOS

LOL

Hold_Good

M3-8R Data Sheet #: TM059 of 32 Rev: 05 Date: 01/26/11


Specifications for Ultra Miniature Stratum 3Table 1

Parameter SpecificationVoltage 3.3V±5%Power 1.6WMaximumduringstartup,1.0WTypical@roomtemperatureOperatingTempRange 0°-70°CReferenceFrequency1-8 8kHz-77.76MHz(Determinedbycustomer’sapplication)CMOSOutputFrequency#1 8kHz-77.76MHzM/S_Out 8kHzBITS_Clk 1.544/2.048MHz(Selectable)Master/SlaveInputReference 8kHz-77.76MHzInputReferencePulseWidth 10nsMin@8kHz,5nsMin@>8kHzFreeRunAccuracy 4.6ppmHoldOverAccuracy 0.37ppmDimensions 2.05x1.25x0.515inches(52.07x31.75x13.08mm)

Pin DescriptionTable 2

Pin# I/O PinName PinDescription 1 O LOS AlarmOutput-LossofActiveReferenceSignal 2 O LOL AlarmOutput-LossofLock 3 I M/SREF Master/SlaveReferenceInput 4 I REF1 ReferenceInput1–8kHzto77.76MHzautodetected 5 I REF2 ReferenceInput2–8kHzto77.76MHzautodetected 6 I REF3 ReferenceInput3–8kHzto77.76MHzautodetected 7 I REF4 ReferenceInput4–8kHzto77.76MHzautodetected 8 TDI JTAGTDIpin 9 TMS JTAGTMSpin 10 TRST JTAGTRSTpin 11 O BITS_CLK 1.544or2.048MHzoutputselectedbypin14 12 O M/S_OUT Master/Slave8kHzoutput 13 O OUTPUT1 SynchronousPrimaryOutput 14 VPP PositiveProgrammingSupplyPin.Duringnormaloperation,itis recommendedtofloatthispin. 15 REF5 ReferenceInput5–8kHzto77.76MHzautodetected 16 REF6 ReferenceInput6–8kHzto77.76MHzautodetected 17 REF8 ReferenceInput8–8kHzto77.76MHzautodetected 18 REF7 ReferenceInput7–8kHzto77.76MHzautodetected 19 VPN NegativeProgrammingSupplyPin.Duringnormaloperation,itis recommendedtofloatthispin. 20 I T1/E1 BITS_CLKselectinput–1=1.544MHz,0=2.-48MHz,4.7kOhmPull-up 21 O HOLD_GOOD HoldoverGoodOutputFlag–1=HoldoverAvailable 22 TDO JTAGTDOpin 23 TCK JTAGTCKpin 24 GND ModuleGround 25 I SPI_CLK SPIPortClockinput 26 I SPI_IN SPIPortDatainput 27 VCC 3.3VdcVCCSupplyInput 28 I SPI_ENBL SPIPortEnableinput–ActiveLow,4.7kOhmPull-up 29 I RESET ModuleReset–ActiveLow,4.7kOhmPull-up 30 O SPI_OUT SPIPortDataOutput 31 O SPI_INT SPIPortInterruptOutput 32 I MASTERSELECT Master/Slaveselectinput–1=Master,0=Slave



Register MapTable 3

Address RegName Description Type0x00 Chip_ID_Low LowbyteofchipID R0x01 Chip_ID_High HighbyteofchipID R0x02 Chip_Revision Chiprevisionnumber R0x03 Bandwidth_PBO Bandwidth&PhaseBuild-Outoption R/W0x04 Ctl_Mode ManualorautomaticselectionofOp_Mode,BITSclockoutputfrequency R/W indication,andframe/multi-framesyncpulsewidthmodecontrol0x05 Op_Mode MasterFreeRun,Locked,orHoldOvermode,orSlavemode R/W0x06 Max_Pullin_Range Maximumpull-inrangein0.1ppmunits R/W0x07 M/SInput_Activity CrossReferenceactivity R0x08 Ref_Activity Activitiesof8referenceinputs R0x09 Ref_Pullin_Sts Inoroutofpull-inrangeof8referenceinputs R0x0a Ref_Qualified Qualificationof8referenceinputs R0x0b Ref_Mask Availabilitymaskfor8referenceinputs R/W0x0c Ref_Available Availabilityof8referenceinputs R0x0d Ref_Rev_Delay Referencereversiondelaytime,0-255minutes R/W0x0e Phase_Offset PhaseoffsetbetweenM/SREF&M/SOutput(fortheSlavein M/Soperation)in250psresolution R/W0x0f Calibration Localoscillatordigitalcalibrationin0.05ppmresolution R/W

Pin DiagramFigure 2

SM3-8R

LOS

LOL

M/S REF

REF1

REF2

REF3

REF4

TDI

TMS

TRST

BITS_CLK

M/S_OUT

OUTPUT1

VPP

REF5

REF6

MASTER SELECT

SPI_INT

SPI_OUT

RESET

SPI_ENBL

Vcc

SPI_IN

SPI_CLK

GND

TCK

TDO

HOLD_GOOD

T1/E1

VPN

REF7

REF8

1

14

2

3

4

5

6

7

8

9

10

11

12

13

15

16 17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

(TOP VIEW)



Register Map ContinuedTable 3

0x10 Fr_Pulse_Width Framesyncpulsewidth R/W0x11 DPLL_Status DigitalPhaseLockedLoopstatus R0x12 Intr_Event Interruptevents R0x13 Intr_Enable Enableindividualinterruptevents R/W0x14 Ref1_Frq_Offset Ref1frequencyoffsetin0.2ppmresolution R0x15 Ref2_Frq_Offset Ref2frequencyoffsetin0.2ppmresolution R0x16 Ref3_Frq_Offset Ref3frequencyoffsetin0.2ppmresolution R0x17 Ref4_Frq_Offset Ref4frequencyoffsetin0.2ppmresolution R0x18 Ref5_Frq_Offset Ref5frequencyoffsetin0.2ppmresolution R0x19 Ref6_Frq_Offset Ref6frequencyoffsetin0.2ppmresolution R0x1a Ref7_Frq_Offset Ref7frequencyoffsetin0.2ppmresolution R0x1b Ref8_Frq_Offset Ref8frequencyoffsetin0.2ppmresolution R0x1c Ref1_Frq_Priority Ref1frequencyandpriority R/W0x1d Ref2_Frq_Priority Ref2frequencyandpriority R/W0x1e Ref3_Frq_Priority Ref3frequencyandpriority R/W0x1f Ref4_Frq_Priority Ref4frequencyandpriority R/W0x20 Ref5_Frq_Priority Ref5frequencyandpriority R/W0x21 Ref6_Frq_Priority Ref6frequencyandpriority R/W0x22 Ref7_Frq_Priority Ref7frequencyandpriority R/W0x23 Ref8_Frq_Priority Ref8frequencyandpriority R/W0x24 FreeRunPriority ControlandPriorityfordesignationofFreeRunasareference R/W0x25 History_Policy SetspolicyforHoldOverhistoryaccumulation R/W0x26 History_CMD Save,restoreandflushcomandsforHoldOverhistory R/W0x27 HoldOver_Time IndicatesthetimesinceenteringHoldOverstate R0x30 Cfgdata Configurationdatawriteregister R/W0x31 Cfgctr_Lo Configurationdatawritecounter,lowbyte R0x32 Cfgctr_Hi Configurationdatawritecounter,highbyte R0x33 Chksum Configurationdatachecksumpass/failindicator R0x35 EE_Wrt_Mode Disables/EnableswritingtotheexternalEEPROM R/W0x37 EE_Cmd Read/Writecommand&readyindicationregisterforext.EEPROMaccess R/W0x38 EE_Page_Num PagenumberforexternalEEPROMaccess R/W0x39 EE_FIFO_Port Read/WritedataforexternalEEPROMaccess R/W



Detailed Description

TheSM3-8Rcanacceptupto8externalreferencesfrom8kHzto77.76MHzandeachismonitoredforsignalpresenceandfrequencyoffset.Additionally,across-couplereferenceinputisprovidedformaster/slaveoperation.Referenceselectionmaybemanualorautomatic,accordingtopre-programmedpriorities.Allreferenceswitchesareperformedinahitlessmanner,andfrequencyrampcontrolsensuresmoothoutputsignaltransitions.Whenreferencesareswitched,thedeviceprovidesanautomaticphasebuild-outtominimizephasetransitionsintheoutputclocks. Threeoutputsignalsareprovided,thefirstupto77.76MHz,thesecondfixedat8kHzforuseasaFrameSyncsignalaswellasacross-couplereferenceformaster/slaveoperation.Inslavemode,theoutputphasemaybeadjustedfrom-32to+31.75nSrelativetothemaster,toaccommodatedownstreamsystemneeds,suchasdifferentclockdistributionpathlengths.ThethirdoutputisaBITSclock,selectableaseither1.544MHzor2.048MHz. DeviceoperationmaybeinFreeRun,locked,orHoldOvermodes.InFreeRun,theclockfrequenciesaresimplydeterminedbytheaccuracyofthecalibratedinternalclock.Inlockedmode,theSM3-8Rphaselockstotheselectedinputreference.Whilelocked,afrequencyhistoryisaccumulated.InHoldOvermode,theoutputfrequenciesaregeneratedaccordingtothishistory. TheDigitalPhaseLockedLoopprovidesthecriticalfilteringandfrequency/phasecontrolthatmeetorexceedallrequirementsincriticaljitterandaccuracyperformanceparameters.Filterbandwidthmaybeconfiguredtosuitapplicationsrequirements. ControlfunctionsareprovidedviastandardSPIbusregisterinterface.Registeraccessprovidesvisibilityintoavarietyofregisteredinformationaswellasprovidingextensiveprogrammablecontrolcapability.Operating Modes: The SM3-8R Operates in Either Free Run, Locked, or Hold Over Mode: Free Run–InFreeRunmode,Output 1, M/S Output, and BITS_Clk,theoutputclocks,aredetermineddirectlyfromandhavetheaccuracyofthecalibratedfreerunninginternalclock.Referenceinputscontinuetobemonitoredforsignalpresenceandfrequencyoffset,butarenotusedtosynchronizetheoutputs. Locked–TheOutput 1, M/S Output, andBITS_Clk,outputsarephaselockedandtracktheselectedinputreference.UponenteringtheLockedmode,thedevicebeginsanacquisitionprocessthatincludesreferencequalificationandfrequencyslewratelimiting,ifneeded.Oncesatisfactorylockisachieved,the“Locked”bitissetintheDPLL_Statusregister,andacompilationofthefrequencyhistoryoftheselectedreferenceisstarted.WhenausableHoldOverhistoryhasbeenestablished,theHold_Goodpinisset,andthe“HoldOverAvailable”bitissetintheDPLL_Statusregister. PhasecomparisonandphaselockloopfilteringoperationsintheSM3-8Rarecompletelydigital.Asaresult,deviceandloopbehaviorareentirelypredictable,repeatable,andextremelyaccurate.Carefullydesignedandprovenalgorithmsandtechniquesensurecompletelyhit-lessreferenceswitches,operationalmodechanges,andmaster/slaveswitches. Basicloopbandwidthisprogrammablefrom.025Hzto1.6Hz,givingtheuserawiderangeofcontroloverthesystemresponse. Whenanewreferenceisacquired,maximumfrequencyslewlimitsensuresmoothfrequencychanges.Oncelockisachieved,(<100secondsforstratum3),the“Locked”bitisset.IftheSM3-8Risunabletomaintainlock,LossofLock(LOL)isasserted.Alltransitionsbetweenlocked,HoldOverandFreeRunmodesareperformedwithminimalphaseeventsandsmoothfrequencyandphasetransitions. Referencephasehitsorphasedifferencesencounteredwhenswitchingreferences(orwhenenteringlockedmode)arenulledoutwithanautomaticphasebuild-outfunction,witharesidualphaseerroroflessthan1ns. Hold Over–UponenteringHoldOvermode,theOutput 1, M/S Output, and BITS_Clk,outputsaredeterminedfromtheHoldOverhistoryestablishedforthelastselectedreference.OutputfrequencyisdeterminedbyaweightedaverageoftheHoldOverhistory,andaccuracyisdeterminedbytheinternalclock.HoldOvermodemaybeenteredmanuallyorautomatically.AutomaticentryintoHoldOvermodeoccurswhenoperatingintheautomaticmode,thereferenceislost,andnoothervalidreferenceexists.ThetransferintoandoutofHoldOvermodeisdesignedtobesmoothandfreeofhits.Thefrequencyslewisalsolimitedtoamaximumof±2ppm/sec. Thehistoryaccumulationalgorithmusesafirstorderfrequencydifferencefilteringalgorithm.Typicalholdoveraccumulationtakesabout15minutes.Whenausableholdoverhistoryhasbeenestablished,theHold_Good pinisset,andthe“HoldoverAvailable”bitissetintheDPLL_Status register.Theholdoverhistorycontinuestobeupdatedafter“HoldoverAvaialble”isdeclared. ThealgorithmaccumulatestheholdoverhistoryonlywhenithaslockedtoeitheranexternalreferenceinMasteroperationortheM/S REF clockinSlaveoperation,starting15minutesafterpowerup.TrackingwillbesuspendedautomaticallywhenswitchingtoanewreferenceandinHoldOverorFreeRunmode.Asetofregistersallowstheapplicationtocontrolaholdoverhistorymaintenancepolicy,enablingeitherare-buildorcontinuanceofthehistorywhenareferenceswitchoccurs.



Detailed Description continued

TheM/SOutputortheOutput1ofeachdevicemaybecross-connectedtotheotherdevice’sM/SRefinput.Thedeviceauto-detectsthefrequencyontheM/SRefinput.MasterorslavestateofadeviceisdeterminedbytheM/Spin.Thus,master/slavestateisalwaysmanuallycontrolledbytheapplication.Themastersynchronizestotheselectedinputreference,whiletheslavesynchronizestotheM/SRefinput.(Notethat8kHzframephasealignmentismaintainedacrossamaster/slavepairofdevicesonlyifM/SOutputisusedasthecrosscouplesignal.) Theunitoperatinginslavemodelocksonandphase-alignstothecross-referenceclock(M/SOutputorOutput1)fromtheunitinmastermode.Thephaseskewbetweentheinputcross-referenceandtheoutputclockfortheslaveunitistypicallylessthan±1ns(under±3nsindynamicsituations,includingreferencejitterandwander). PerfectphasealignmentofthetwoOutput1outputclockswouldrequirenodelayonthecross-referenceclockconnection.Toaccommodatepathlengthdelays,theSM3-8Rprovidesaprogrammablephaseskewfeature.Theslave’sOutput1orM/SOutputmaybephaseshifted-32nSto+31.75nSrelativetoM/SInputaccordingtothecontentsoftheMS_Phase_OffsetregistertocompensateforthepathlengthoftheM/SOutputorOutput1toM/SInputconnection.Thisoffsetmaythereforebeprogrammedtoexactlycompensatefortheactualpathlengthdelayassociatedwiththeparticularapplication’scross-referencetraces.Theoffsetmayfurtherbeadjustedtoaccommodateanyoutputclockdistributionpathdelaydifferences.Thus,master/slaveswitcheswiththeSM3devicesmaybeaccomplishedwithnear-zerophasehits. Thefirsttimeaunitbecomesaslave,suchasimmediatelyafterpower-up,itsoutputclockphasestartsoutarbitrary,andwillquicklyphase-aligntothecross-referencefromthemasterunit.Thephaseskewwillbeeliminated(orconvergedtotheprogrammedphaseoffset)stepbystep.Thewholepull-in-and-lockprocesswillcompleteinabout60seconds.Thereisnofrequencyslewprotectioninslavemode.Inslavemode,theunit’smissionistolocktoandfollowthemaster. Onceapairofunitshasbeenoperatinginalignedmaster/slavemode,andamaster/slaveswitchoccurs,theunitthatbecomesmasterwillmaintainitsoutputclockphaseandfrequencywhileaphasebuild-out(tothecurrentoutputclockphase)isperformedonitsselectedreferenceinput.Therefore,asmastermodeoperationcommences,therewillbenophaseorfrequencyhitsontheclockoutput. Likewise,theunitthatbecomestheslavewillmaintainitsoutputclockfrequencyandphasefor1msecbeforestartingtofollowthecross-reference,protectingthedownstreamclockusersduringtheswitch.Assumingthephaseoffsetisprogrammedfortheactualpropagationdelayofthiscross-referencepath,therewillagainbenophasehitsontheoutputclockoftheunitthathastransitionedfrommastertoslave.

Master / Slave ConfigurationFigure 3

Furthermore,underregisteraccesscontrol,abackupholdoverhistoryregisterisprovided.Itmaybeloadedfromtheactiveholdoverhistoryorrestoredtotheactiveholdoverhistory.Theactiveholdoverhistorymayalsobeflushed. Holdovermodemaybeenteredatanytime.Ifthereisnoholdoverhistoryavailable,theprioroutputfrequencywillbemaintained.Wheninholdover,theapplicationmayread(viaregisteraccess)thetimesinceholdoverwasenterred.

Master/Slave Operation PairsofSM3-8Rdevicesmaybeoperatedinamaster/slaveconfigurationforredundanttimingsourceapplications.Atypicalconfigurationisshownbelow.:

STC3500M/S_OUT / OUTPUT1

M/S_OUT / OUTPUT1

M/S REF

REFS1-8

REFS1-8

M/S REF

SM3-8R

2

SM3-8R

1



Serial Interface Timing, Write AccessFigure 5


Serial Interface Timing, Read AccessFigure 4

NOTE:SPI_OUTisnormallyheldatlogic0exceptwhentri-statedduringan addressreadcycleontheSPI_INpinorwhendataisbeingoutputonthe SPI_OUTpin.

Serial Communication TheusercancontroltheoperationoftheSM3-8RmodulethroughtheSPIport.Timingdiagramsareshownbelow.Thisinterfaceisonlyforpoint-to-pointapplications.

CS

SCLK

SDI

tRWs

1 2 3 4

A0 A1 A2 A3 A4 A5 A6

5 6 7 8 13 14 15 169 10 11 12

1

tRWh

LSB MSB

tCH tCL

tCS

D0 D1 D2 D3 D4 D5 D6 D7

LSB MSB

tCSMIN

CS

SCLK

SDI

1 2 3 4

A0 A1 A2 A3 A4 A5 A6

5 6 7 8 13 14 15 169 10 11 12

0

D0

LSB MSB

SDOMSBLSB

tDRDY

tCH tCL

tCS

tRWs tRWh

tCSMIN

tDHLD

tCSTRI

D1 D2 D3 D4 D5 D6 D7



Reference Input Quality Monitoring Eachreferenceinputismonitoredforsignalpresenceandfrequencyoffset.SignalpresencefortheRef1-8inputsisindicatedintheRef_ActivityregisterandsignalpresencefortheM/S REFisindicatedinbit0oftheM/S REF_Activityregister.ThefrequencyoffsetbetweentheRef1-8inputsandthecalibratedlocaloscillatorisavailableintheRef_Frq_Offsetregisters(8).RegisterRef_Pullin_Stsindicates,foreachoftheRef1-8inputs,ifthereferenceiswithinthemaximumpull-inrange.Themaximumpull-inrangeisindicatedinregisterMax_Pullin_Range,andmaybesetin0.1ppmincrements.Typically,itwouldbesetaccordingtothevaluesspecifiedbythestandards(GR-1244)appropriatefortheparticularstratumofoperation. TheRef_Qualifiedregistercontainsthe“anded”conditionoftheRef_ActivityandRef_Pullin_StsregistersforeachoftheRef1-8 inputs,qualifiedfor10seconds.Whenareferencesignalhasbeenpresentfor>10secondsandiswithinthepull-inrange,it’sbitisset. TheRef_Availableregistercontainsthe“anded”conditionoftheRef_QualifiedregisterandtheRef_Maskregister,andthereforerepresentstheavailabilityofareferenceforselectionwhenautomaticreferenceandoperationalmodeselectionisenabled.

Reference Input Selection, Frequencies, and Mode Selection Oneofeightreferenceinputsignals(Ref 1-8)areselectedforsynchronizationinMastermode(asbelowintheOp_Moderegisterdescription.0x05).Ref 1-8mayeachbe8kHz,1.544MHz,2.048MHz,12.96MHz,19.44MHz,25.92MHz,38.88MHz,51.84MHzor77.76MHz. Referencefrequenciesareauto-detectedandthedetectedfrequencycanbereadfromtheRef_Frq_Priority registers(SeeRegister Descriptions and Operationsection). Activereferenceandoperationalmodeselectionmaybemanualorautomatic,asdeterminedbybit1intheCtl_Moderegister.Inmanualmode,registerwritestoOp_Modeselectthereferenceandmode.Theresetdefaultismanualmode. TheM/SREFinputforslaveoperationisfrequencyauto-detectedandmaybe8kHz,1.544MHz,2.048MHz,12.96MHz,19.44MHz,25.92MHz,38.88MHz,51.84MHzor77.76MHz.SignalpresenceandfrequencyfortheM/SREFinputisindicatedinbits0-3oftheM/S REF_Activityregister. Inautomaticmode,thereferenceisselectedaccordingtotheprioritieswrittentotheeightRef_Frq_Priorityregisters.Individualreferencesmaybemaskedforuse/non-useaccordingtotheRef_Maskregister.Areferencemayonlybeselectedifitis“available”-thatis,itisqualified,asindicatedintheRef_Qualified register,andisnotmasked(SeeReference Input Quality Monitoring and Register Descriptions and Operation sections). Furthermore,Bit3ofeachRef_Frq_Priority registerwilldetermineifthatreferenceisrevertiveornon-revertive.Whenareferencefails,thenexthighestpriority“available”(signalpresent,non-masked,andacceptablefrequencyoffset)referencewillbeselected.Whenareferencereturns,itwillbeswitchedtoonlyifitisofhigherpriorityandthecurrentactivereferenceismarked“Revertive”.Additionally,thereversionisdelayedaccordingtothevaluewrittentotheRef_Rev_Delayregister(From0to255minutes).


Serial Interface TimingTable 4

Symbol Parameter Minimum Nominal Maximum Units NotestCS SPI_EnablelowtoSPI_CLKlow 15 - - nstCH SPI_CLKhightime 25 - - nstCL SPI_CLKlowtime 25 - - nstRWs Read/Writesetuptime 15 - - nstRWh Read/Writeholdtime 15 - - nstDRDY Dataready - - 25 nstHLD DataHold 15 - - nstCSTRI ChipSelecttodatatri-state 5 - - nstCSMIN Minimumdelaybetweensuccessiveaccesses 300 - - ns




The automatic reference selection is shown in the following state diagram:

The operational mode is according to the following state diagram: NoavailablereferenceandnoHoldOverhistoryReflossw/nogoodHoldOverhistoryandnootheravailablereference

Automatic Reference SelectionFigure 6

Automatic Operational Mode SelectionFigure 7

Lockedon Ref n

Select &Lock onRef m

Ref n returns,

Ref m marked

“non-revertive”

Locked on Ref mtime for t=

Ref_Rev_DelayRef_Rev_Delay

time expired

Loss of Ref n

Select new reference:

Qualified (within max. pull-in range, signal present > 10 sec.),

Non-masked

Ref n returns,Ref m marked

“revertive”

Next highest priority,

Stay

Ref

Return

Ref Loss w/good hold over history and no alternate reference available

Ref Loss w/alternate reference available

Return Ref

Ref loss w/no good hold

over history and no other

available reference

No available

reference and

no hold over

history

Reference Available

Locked

Hold OverFree Run

(Select highest priority)

Higher priority Ref return withprior reference marked

“revertive”




Output Signals and Frequency Output 1istheprimarychipoutput,andinlockedmodeissynchronizedtotheselectedreference.Output 1maybeanyofthefollowingfrequencies:12.96MHz,19.44MHz,25.92MHz,38.88MHz,51.84MHzor77.76MHz. M/S_Out isan8kHzoutputavailableasaframereferenceorsynchronizationsignalforcross-coupledpairsofSM3-8Rdevicesoperatedinmaster/slavemode.Inmastermode,M/S_Outissynchronizedtotheselectedreference.Inslavemode,M/S_OutisinphasewiththeM/S REF offsetbythevaluewrittentothePhase_offset register(+31.75to-32nS,with.25nSresolution).M/S_Outmaybea50%dutycyclesignal,orvariablehigh-goingpulsewidth,asdeterminedbytheCtl_ModeandFr_Pulse_Widthregisters.Invariablepulsewidthmode,thewidthmaybefrom1to15multiplesoftheOutput 1cycletime.SeeRegisterDescriptionsandOperationsection. BITS_ClkistheBITSclockoutputateither1.544MHzor2.048MHz.ItisselectedbytheT1/E1inputanditsstatemaybereadinbit3oftheCtl_Moderegister.WhenT1/E1=1,theBITSfrequencyis1.544MHz,andwhenT1/E1=0,theBITSfrequencyis2.048MHz.

Interrupts TheSM3-8RmodulesupportseightdifferentinterruptsandappearsinINTR_EVENT (0x12)register.EachinterruptcanbeindividuallyenabledordisabledviatheINTR_ENABLE (0x13)register.EachbitenablesordisablesthecorrespondinginterruptfromassertingtheSPI_INTpin.InterrupteventsstillappearintheINTR_EVENT (0x12)registerindependentoftheirenablestate.AllinterruptsareclearedonceINTR_EVENT (0x12)registerisread.Theinterruptsare: • Anyreferencechangingfromavailabletonotavailable • Anyreferencechangingfromnotavailabletoavailable • M/S REFchangingfromactivitytonoactivity • M/S REFchangingfromnoactivitytoactivity • DPLLModestatuschange • Referenceswitchinautomaticreferenceselectionmode • LossofSignal • LossofLock

Interrupts and Reference Change in Autonomous Mode Interruptscanbeusedtodeterminethecauseofareferencechangeinautonomousmode.LetusassumethatthemoduleiscurrentlylockedtoREF1.ThemoduleswitchestoREF2andSPI_INTpinisasserted.TheuserreadstheINTR_EVENT (0x12)register. Ifthemoduleisoperatinginautonomousnon-revertivemode,thecausecanbedeterminedfrombits4,5,6and7.Bit5issettoindicateActivereferencechange.IfBit6issetthenthecauseofthereferencechangeisLossofActiveReference.IfBit7issetthenthecauseofthereferencechangeisaLossofLockalarmontheactivereference. Ifthemoduleisoperatinginautonomousrevertivemode,thecausecanbedeterminedfrombits1,4,5,6and7.Bit5issettoindicateActivereferencechange.IfBit6issetthenthecauseofthereferencechangeisLossofActiveReference.IfBit7issetthenthecauseofthereferencechangeisaLossofLockalarmontheactivereference.IfBit1issetthenthecauseofthereferencechangeistheavailabilityofahigherpriorityreference. Note:TheDPLLModeStatusChangebit(Bit4)isalsosettoindicateachangeinDPLL_STATUS (0x11)register,duringaninterruptcausedbyareferencechange.Thedatain DPLL_STATUS (0x11)registerhoweverisnotusefulindeterminingthecauseofareferencechange.Thisisbecausebits0-2ofthisregisteralwaysreflectsthestatusofthecurrentactivereferenceandhencecannotbeusedtodeterminethestatusofthelastactivereference.

Interrupts in Manual Mode Inmanualoperatingmode,whentheactivereferencefailsduetoaLossofSignalorLossofLockalarm,aninterruptisgenerated.Forexample,incaseofaLossofSignal,bits4and6ofINTR_EVENT (0x12) registerwouldbesettoindicateLossofSignalandDPLLModeStatusChange.TheusermaychoosetoreadtheDPLL_STATUS (0x11)register,thoughinmanualmodebit6ofINTR_EVENT (0x12)registerisamirrorofbit0ofDPLL_STATUS (0x11)register.ThisholdstrueforaLossofLockalarm,wherebit7ofINTR_EVENT (0x12) registerisamirrorofbit1ofDPLL_STATUS (0x11)register.

Internal Clock Calibration Theinternalclockmaybecalibratedbywritingafrequencyoffsetv.s.nominalfrequencyintotheCalibrationregister.ThiscalibrationisusedbythesynchronizationsoftwaretocreateafrequencycorrectedfromtheactualinternalclockoutputbythevaluewrittentotheCalibrationregister.Seeregisterdescriptions.



Register Descriptions and Operation

Chip_ID_low, 0x00 (R)Bit7~Bit0

LowbyteofchipID:0x11

Chip_ID_High, 0x01 (R)Bit7~Bit0

HighbyteofchipID:0x30

Chip_Revision, 0x02 (R)Bit7~Bit0

Chiprevisionnumber:0x05

Bandwidth_PBO, 0x03 (R/W) Bit7~Bit5 Bit4 Bit3~Bit0Reserved Reserved BandwidthSelectioninHz: 0:Default 0000:0.025 0001:0.025 0010:0.025 0011:0.025 0100:0.025 0101:0.025 0110:0.049 0111:0.098(ResetDefault) 1000:0.20 1001:0.39 1010:0.78 1011-1111:1.6

BITS 3 - 0 select the phase lock loop bandwidth in Hertz.

Ctl_Mode, 0x04 (R/W)Bit7~BitBit5Bit4 Bit3 Bit2Bit1 Bit0Reserved Default:0 M/SOutput BITSClock HMRef: Active Reserved Pulsewidth Output 0:Registercontrol Reference control: Frequency: ofopmode/ref Selection: 0:50% 1:1.544MHz (Willalways 1:Manual 1:Controlledby 0:2.048MHz be0) 0:Automatic FR_Pulse_Width (readonly) Default:1 register Default:0

When bit 1 is reset (automatic reference and mode selection), Bits 3 - 0 of the Op_Mode register become read-only. The power-up default for Bit 1 = 1 for manual reference selection and default for Bit 4 = 0 for 50% duty cycle on M/S Output. When the device is in slave mode, it will lock to the M/S REF, independent of the values written to BITS 3 - 0 of the Op_mode register. The operational mode and reference selection written to Bits 3 - 0 while in slave mode will, however, take effect when the device is made the master. When bit 1 of the Ctl_Mode register is reset (automatic reference and mode selection) and the device is in master mode, BITS 3 - 0 of the Op_Mode register become read-only.



Register Descriptions and Operation continued

Op_Mode, 0x05 (R/W)Bit7~Bit5 Bit4 Bit3~Bit0Reserved MasterorSlaveMode FreeRun,Locked,orHoldOver: 1:Master 0000:FreeRunmode 0:Slave 0001:LockedonRef1 (ReadOnly) 0010:LockedonRef2 0011:LockedonRef3 0100:LockedonRef4 0101:LockedonRef5 0110:LockedonRef6 0111:LockedonRef7 1000:LockedonRef8 1001-1111:HoldOver

Max_Pullin_Range, 0x06 (R/W)Bit7~Bit0

Maximumpull-inrangein0.1ppmunit

This register should be set according to the values specified by the standards (GR-1244) appropriate for the particular stratum of operation. The power-up default value is 10 ppm. (= 4.6ppm aging + 4.6 ppm pullin + margin).

M/S REF_Activity, 0x07 (R) Bit7~Bit4 Bit3~Bit0 Reserved Crossreferenceactivity 0000:Nosignal 0001:8kHz 0100:12.96MHz 0101:19.44MHz 0110:25.92MHz 0111:38.88MHz 1000:51.84MHz 1001:77.76MHz 1010-1111:Reserved

Indicates signal presence and auto-detected frequency for the M/S REF input.

Ref_Activity, 0x08 (R)Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0ref8activity ref7activity ref6activity ref5activity ref4activity ref3activity ref2activity ref1activity1:on 1:on 1:on 1:on 1:on 1:on 1:on 1:on0:off 0:off 0:off 0:off 0:off 0:off 0:off 0:off

Each bit indicates the presence of a signal for that reference.




Ref_Pullin_Sts, 0x09 (R)Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0ref8sts ref7sts ref6sts ref5sts ref4sts ref3sts ref2sts ref1sts1:inrange 1:inrange 1:inrange 1:inrange 1:inrange 1:inrange 1:inrange 1:inrange0:outrange 0:outrange 0:outrange 0:outrange 0:outrange 0:outrange 0:outrange 0:outrange

Each bit indicates if the reference is within the frequency range specified by the value in the Max_Pullin register.

Ref_Qualified, 0x0a (R)Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0ref8qual: ref7qual: ref6qual: ref5qual: ref4qual: ref3qual: ref2qual: ref1qual:1:avail. 1:avail. 1:avail. 1:avail. 1:avail. 1:avail. 1:avail. 1:avail.0:notavail. 0:notavail. 0:notavail. 0:notavail. 0:notavail. 0:notavail. 0:notavail. 0:notavail.

This register contains the “anded” condition of the Ref_Activity and Ref_Pullin_Sts registers for each of the Ref1-8 inputs, qualified for 10 seconds. When a reference signal has been present for > 10 seconds and is within the pull-in range, its bit is set.

Ref_Mask, 0x0b (R/W)Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0ref8mask: ref7mask: ref6mask: ref5mask: ref4mask: ref3mask: ref2mask: ref1mask:1:avail. 1:avail. 1:avail. 1:avail. 1:avail. 1:avail. 1:avail. 1:avail.0:notavail. 0:notavail. 0:notavail. 0:notavail. 0:notavail. 0:notavail. 0:notavail. 0:notavail.Default:0 Default:0 Default:0 Default:0 Default:0 Default:0 Default:0 Default:0

Individual references may be marked as “available” or “not available” for selection in the automatic reference selection mode (bit 1 = 0 in the Ctl_Mode register). The reset default value is 0, “not available”. In manual reference selection, either hardware or register controlled, the reference masks have no effect, but do remain valid and are applied upon a transi-tion to automatic mode.

Ref_Available, 0x0c (R)Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0ref8avail: ref7avail: ref6avail: ref5avail: ref4avail: ref3avail: ref2avail: ref1avail:1:avail. 1:avail. 1:avail. 1:avail. 1:avail. 1:avail. 1:avail. 1:avail.0:notavail. 0:notavail. 0:notavail. 0:notavail. 0:notavail. 0:notavail. 0:notavail. 0:not

This register contains the “anded” condition of the Ref_Qualified and Ref_Mask registers.

Ref_Rev_Delay, 0x0d (R/W)Bit7~Bit0

Referencereversiondelaytime,0-255minutes.default=00000101,5minutes

In automatic reference selection mode, when a reference fails and later returns, it must be available for the time speci-fied in the Ref_Rev_Delay register before it can be switched back to as the active reference (if the new reference was marked as “revertive”).




Phase_Offset, 0x0e (R/W)Bit7~Bit0

The2’scomplementvalueofphaseoffsetbetweenMasterOutputmoduleandSlaveOutputmodule,rangesfrom-32nSto+31.75nS PositiveValue:MasterOutputrisingedgeleadsSlaveOutput NegativeValue:MasterOutputrisingedgelagsSlaveOutput

In slave mode, the slave’s outputs may be phase shifted -32nS to +31.75nS in .25nS increments, relative to M/S ac-cording to the contents of the Phase_Offset register, to compensate for the path length of the M/S to M/S connection.

If a phase offset is used, then the two SM3-8R devices would typically be written to the appropriate phase offset val-ues for the respective path lengths of each Master to Slave connection, to ensure that the same relative output signal phases will persist through master/slave switches.

Calibration, 0x0f (R/W)Bit7~Bit0

2’scomplementvalueoflocaloscillatordigitalcalibrationin0.05ppmresolution

To digitally calibrate the free running clock synthesized from the internal clock, this register is written with a value cor-responding to the known frequency offset of the oscillator from the nominal center frequency.

Fr_Pulse_Width, 0x10 (R/W) Bit7~Bit4 Bit3~Bit0Reserved PulsewidthforM/Sclockoutput, 1-15multiplesoftheSync_Clkclockperiod.

BITS 4 and 5 of the Ctl_Mode register determine if the M/S 8 kHz output is 50% duty cycle or pulsed (high going) out-puts. When they are pulsed, the Fr_Pulse_Width register determines the width. Width is the register value multiple of the Sync_Clk clock period. Valid values are 1 - 15.

Reset default is 0001. Writing to 0000 maps to 0001.

DPLL_Status, 0x11 (R)Bit7~Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reserved HoldOver HoldOver Locked LossofLock LossofSignal Build Available 1:Locked 1:LossofLock 1:Noactivity Complete 1:Avail.0: Notlocked 0:Nolossoflock onactive 1:Complete 0:Notavail. reference 0:Incomplete 0:Activeref- erencesignal present

Bit 0 indicates the presence of a signal on the selected reference.

Bit 1 indicates a loss of lock (LOL). Loss of lock will be asserted if lock is not achieved within the specified time for the stratum level of operation, or lock is lost after being established previously. LOL will not be asserted for automatic refer-ence switches.

Bit 2 indicates successful phase lock. It will typically be set in <700 seconds for Stratum 3 with a good reference. It will indicate “not locked” if lock is lost.

Bit 3 indicates if a Hold Over history is available.

Bit 4 indicates when a new Hold Over history has been sucessfully built and transferred to the active Hold Over history. See Detailed Description section under Interrupts and Reference Change in Autonomous Mode and Interrupts in Manual Mode




Intr_Event, 0x12 (R)Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0Lossof Lossof Activerefer- DPLLMode M/SRef M/SRef Anyrefer- Anyrefer-Lock Signal encechange status Changefrom Changefrom erencechange erencechange change noactivityto activitytono fromnot fromavailable activity activity availableto abletonot available available

Interrupt state = 1. When an enabled interrupt occurs, the SPI_INT pin is asserted, active low. All interrupts are cleared and the SPI_INT pin pulled high when the register is read. Reset default is 0. See Detailed Description section under Interrupts and Reference Change in Autonomous Mode and Interrupts in Manual Mode

Intr_Enable, 0x13 (R/W)Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0EnableInter- EnableInter- EnableInter- EnableInter- EnableInter- EnableInter- EnableInter- EnableInter-ruptevent7: ruptevent6: ruptevent5: ruptevent4: ruptevent3: ruptevent2: ruptevent1: ruptevent0:1:Enable 1:Enable 1:Enable 1:Enable 1:Enable 1:Enable 1:Enable 1:Enable0:Disable 0:Disable 0:Disable 0:Disable 0:Disable 0:Disable 0:Disable 0:DisableDefault:0 Default:0 Default:0 Default:0 Default:0 Default:0 Default:0 Default:0

Enables or disables the corresponding interrupts from asserting the SPI_INT pin. Interrupt events still appear in the Intr_Event register independent of their “enable” state. Reset default is interrupts disabled.

Ref(1-8)_Frq_Offset, 0x14 ~ 0x1b (R)Bit7~Bit0

2’scomplementvalueoffrequencyoffsetbetweenreferenceandcalibratedlocaloscillator,0.2ppmresolution

These registers indicate the frequency offset, in 0.2ppm resolution, between each reference and the local calibrated oscillator. 0x14 - 0x1b correspond to Ref1 - Ref8.

Ref(1-8)_Frq_Priority, 0x1c ~ 0x23 (R/W)Bit7~Bit4 Bit3 Bit2~Bit0Frequency Revertivity Priority0000:None 1:revertive 000:Highest0001:8kHz 0:non-revertive 111:Lowest0010:1.544MHz Default:0, Default:00011:2.048MHz nonrevertive0100:12.96MHz0101:19.44MHz0110:25.92MHz0111:38.88MHz1000:51.84MHz1001:77.76MHz1010-1111:Reserved

BITS 2 - 0 indicate the priority of each reference for use in automatic reference selection mode (bit 1 of the Ctl_Mode register =0). In manual reference selection mode (bit 1 of the Ctl_Mode register = 1), these BITS are read-only and will contain either the reset default or values written when last in automatic reference selection mode. For equal priority values, lower reference numbers have higher priority. Bit 3 specifies if the reference is revertive or non-revertive in automatic reference selection mode. When a reference fails, the next highest priority “available” (signal present, non-masked, and acceptable frequency offset) reference will be selected. When a reference returns, it will be switched to only if it is of higher priority and the current active reference is marked “Revertive”.BITS 7 - 4 indicate the auto-detected frequency for each reference. Invalid frequencies may result in erroneous device operation. If there is no activity on a reference, bits 7-4will be = 0000. Bits 7-4 are read only. 0x1c - 0x23 correspond to Ref1 - Ref8.



FreeRun_Priority, 0x24 (R/W)Bit7-Bit5 Bit4 Bit3 Bit2-Bit0 Enable/ Revertivity Priority Disable 1:Enable 000:Highest Reserved 1:Enable 0:Disable 111:Lowest 0:Disable Default:0 Default:0 Default:0 non-revertive

Free Run may be treated like a reference. When it is enabled, Free Run will be entered when all references of higher priority are lost or masked. If or when a higher priority reference returns, it is switched to if Free Run is set as “re-vertive”. When disabled, Free Run will be entered only if manually selected or all references fail without an available Hold Over history. For equal priority value, Free Run will be treated as lower priority.

History_Policy, 0x25 (R/W) Bit7-Bit1 Bit0 ReferenceSwitchHoldOver HisoryPolicy Reserved 0:Rebuild 1:Continue

Bit 0 determines if Hold Over is retained or rebuilt when a reference switch occurs. See Application Notes, HoldoverHistory Accumulation and Management section.

History_Cmd, 0x26 (R/W) Bit7-Bit2 Bit1-0 HoldOverHistroyCommands 01:Saveactivehistorytobackuphistory Reserved 10:Restoreactivehistoryfrombackup 11:Flushtheactivehistoryandaccumulationregister 00:Nocommand-usetowriteBit4tochangepolicy

Bits 0-1 are written to save a holdover history to the backup history, restore the active holdover history from the

backup, or flush the active history. The default value of the register is 00. The last command is latched and

may be read by the application. A flush does not affect the backup history. See Application Notes, HoldoverHistory Accumulation and Management section.

HoldOver_Time, 0x27 (R) Bit7-Bit0IndicatesthetimesinceenteringtheHoldOverstate.from0-255,onebitperhour.Zeroinnon-HoldOverstateandstopsat255.

Cfgdata, 0x30 (R/W) Bit7-Bit0Configurationdatawriteregister.

Configuration data is written to this register. Internal use only.

Cfgctr_Lo, 0x31 (R) Bit7-Bit0Configurationdatawritecounterlowbyte.

Low order byte of configuration data write counter. Internal use only.




Cfgctr_Hi, 0x32 (R) Bit7-Bit0Configurationdatawritecounterhighbyte.

High order byte of configuration data write counter. Internal use only.

Chksum, 0x33 (R/W) Bit7-Bit1 Bit0 ConfigurationDataChecksum pass/failindicator Reserved 0:Fail 1:Pass

Checksum verification register for configuration data. Internal use only.

EE_Mode, 0x36 (R/W) Bit7-Bit1 Bit0 EEPROMWriteEnable Reserved 0:Disable 1:Enable

EEPROM write enable register.

EE_Cmd, 0x37 (R/W)Bit7 Bit6-Bit2 Bit1-Bit0EEPROMread/write EEPROMread/writecommandbits:readybit: 00=ResetFIFO0=NotReady Reserved 01=WriteCommand 1=Ready 10=ReadCommand

EEPROM read/write command register.

EE_Page_Num, 0x38 (R/W) Bit7-Bit0EEPROMread/writepagenumber,0x00to0x9f(0-159)

EEPROM read/write page number register. EEPROM consist of 160 pages.

EE_FIFO_Port, 0x39 (R/W) Bit7-Bit0EEPROMread/writeFIFOdata.

EEPROM read/write FIFO port register. EEPROM data is written to/read from this location.




Performance Definitions Jitter and Wander–Jitterandwanderaredefinedrespectivelyas“theshort-termandlong-termvariationsofthesignificantinstantsofadigitalsignalfromtheiridealpositionsintime”.Theyarethereforethephaseorpositionintimemodulationsofadigitalsignalrelativetotheiridealpositions.Thesephasemodulationscaninturnbecharacterizedintermsoftheiramplitudeandfrequency.Jitterisdefinedasthosephasevariationsatratesabove10Hz,andwanderasthosevariationsatratesbelow10Hz. Fractional frequency offset and drift–Thefractionalfrequencyoffsetofaclockistheratioofthefrequencyerror(fromthenominalordesiredfrequency)tothedesiredfrequency.Itistypicallyexpressedas(npartsin10X),or(nx10-X).Driftisthemeasureofaclock’sfrequencyoffsetovertime.Itisexpressedthesamewayasoffset. Time Interval Error (TIE)–TIEisameasureofwanderandisdefinedasthevariationinthetimedelayofagivensignalrelativetoanidealsignaloveraparticulartimeperiod.Itistypicallymeasuredinns.TIEissettozeroatthestartofameasurement,andthusrepresentsthephasechangesincethebeginningofthemeasurement. Maximum Time Interval Error (MTIE)–MTIEisameasurementofwanderthatfindsthepeak-to-peakvariationsinthetimedelayofasignalforagivenwindowoftime,calledtheobservationinterval(t).Thereforeitisthelargestpeak-to-peakTIEinanyobservationintervaloflengtht withintheentiremeasurementwindowofTIEdata.MTIEisthereforeausefulmeasureofphasetransients,maximumwanderandfrequencyoffsets.MTIEincreasesmonotonicallywithincreasingobservationinterval. Time Deviation (TDEV)–TDEVisameasurementofwanderthatcharacterizesthespectralcontentofphasenoise.TDEV(tistheRMSoffilteredTIE,wherethebandpassfilteriscenteredonafrequencyof0.42/t.

SM3-8R Performance Input Jitter Tolerance–Inputjittertoleranceistheamountofjitteratitsinputaclockcantoleratebeforegeneratinganindicationofimproperoperation.GR-1244andITU-813requirementsspecifyjitteramplitudev.s.jitterfrequencyforjittertolerance.TheSM3-8Rdeviceprovidesjittertolerancethatmeetsthespecifiedrequirements. Input Wander Tolerance–Inputwandertoleranceistheamountofwanderatitsinputaclockcantoleratebeforegeneratinganindicationofimproperoperation.GR-1244andITU-813requirementsspecifyinputwanderTDEVv.s.integrationtimeasshownbelow.

IntegrationTime,(seconds) TDEV(ns)0.05≤τ <10 10010<τ<1000 31.6xτ 0.5

1000≤τ N/A

TheSM3-8Rdeviceprovideswandertolerancethatmeetstheserequirements. Phase Transient Tolerance–GR-1244specifiesmaximumreferenceinputphasetransientsthataclocksystemmusttoleratewithoutgeneratinganindicationofimproperoperation.ThephasetransienttoleranceisspecifiedinMTIE(nS)v.s.observationtimefrom.001to100seconds,asshownbelow.

ObservationtimeS(Seconds) MTIE(ns)0.001326≤S<0.0164 61,000xS0.0164<S<1.97 925+4600xS1.97≤S 10,000

TheSM3-8RwilltolerateallreferenceinputtransientswithintheGR-1244specification. Free-run Frequency Accuracy–Theabilityofaclocktoproduceafrequencyascloseaspossibletothenominalfrequencyintheabsenceofareference. Hold Over Frequency Stability–Ameasureofaclock’sperformancewhileinHoldOvermodeover24hours,subjectedtothespecifiedtemperaturevariations.

Performance Specifications



Performance Specifications continued

Wander Generation Characteristics – MTIE

Wander Generation Characteristics – TDEV

Wander Generation–Wandergenerationistheprocesswherebywanderappearsattheoutputofaclockintheabsenceofinputwander.TheSM3-8Rwandergenerationcharacteristics,MTIEandTDEV,areshownbelow,alongwiththerequirementsmasks(bandwidth=0.098Hz):



Phase Transients–Aphasetransientisanunusualsteporchangeinthephase-timeofasignaloverarelativelyshorttimeperiod.Thismaybeduetoswitchingbetweenequipment,referenceswitching,diagnostics,entryorexitto/fromHoldOver,orinputreferencetransients.TheSM3-8Rperformanceforreferenceswitchesisshownbelow:

Phase Transients – MITE


Wander Transfer–Wandertransferisthedegreetowhichinputwanderisattenuated(oramplified)frominputtooutputofaclock.TheGR-1244requirementsforwandertransferlimitsareshownbelow.

Integrationtime,τ (seconds) Stratum3TDEV(nanoseconds)τ <0.05 N/A0.05≤τ <0.1 1020xτ0.1≤ τ <1.44 1021.44≤τ<10 10210≤τ<300 32.2xτ 0.5

300≤τ≤1000 32.2xτ 0.5

1000<τ N/A

TheSM3-8R,whenconfiguredfortheappropriateStratum3bandwidthfrequency,meetstheStratum3requirements, Jitter Generation–Jittergenerationistheprocesswherebyjitterappearsattheoutputofaclockintheabsenceofinputjitter.Thedevicejittergenerationperformanceisasshownbelow:

Jitter 19.44MHz 77.76MHzBroadband 8psTypical 8psTypical(10Hz-2MHz)SONETBand (12kHz-2MHz) (12kHz-20MHz) 1psTypical <1psTypical

Jitter Transfer–Jittertransferisthedegreetowhichinputjitterisattenuated(oramplified)frominputtooutputofaclock.Itisafunctionoftheselectedbandwidth.TheSM3-8Rjittertransfercharacteristicsareshownbelow:




Capture range and Lock range–Capturerangeandlockrangearethemaximumfrequencyerrorsonthereferenceinputwithinwhichthephaselockedloopisabletoachievelockandholdlock,respectively.TheSM3-8RStratum3performanceisshownbelow:

Characteristic SM3-8R RequirementCapturerange ±25.5ppmmaximum GR-1244-CORE,Sec3.4Holdrange ±25.5ppmmaximum GR-1244-CORE,Sec3.4

Thisistheminimumcapability,andguaranteestheabilitytocaptureandlockwithareferencethatisoffsetthemaximumallowedinonedirectioninthepresenceofaclockthatisoffsetthemaximumintheoppositedirection(4.6ppm+4.6ppm=9.2ppm).

Master/Slave Skew and Reference switch settling time–Master/SlaveSkewandReferenceswitchsettlingtimeperformanceareshownbelow:

Characteristic SM3-8R RequirementMaster/Slavephaseskew <2nS N/AReferenceswitchsettlingtime Stratum3:<100sec.upto20ppm Stratum3:<100sec.up frequencyoffset to+/-4.6ppmfrequencyoffset

SM3-8R Initialization: Power-up:1.Ifpossible,alwaysstartupinmastermode.Afterthemoduleispoweredup,holdtheresetpinlowfor10ms.Wait1200msandreadthecontentsofregister0x33.Ifitreads1thenthemodulecameupproperly.Ifitreads0thenresetthemoduleandre-readregister0x33after1200ms.Thecontentsof0x33mustread1beforecontinuing.

2.Remaininthedefaultfree-runmodefor10secondsthenreadthevalueofbit1ofregister0x11orpin2,theLOLalarmoutput.IftheLOLalarmisset,theresetpinmustbepulledlowasin1above.Inthefree-runmodetheLOLalarmshouldneverbeset.Thisindicatesthemoduleisinaninvalidstate.IfthereisnoLOLalarminfree-runthemoduleisready.

Operation:Onpoweruporafteraresetalltheregistersareloadedwiththeirdefaultvalues.ThedefaultvaluesofsomeimportantregistersaregivenbelowassumingthemoduleoperatesasaMaster

Address(Hex) Register Name Value(Binary MSB first) Notes0x03 Bandwidth_PBO 00000111 Bandwidth=0.098Hz0x04 Ctl_Mode 0000r010 r-ReadOnly0x05 Op_Mode 00010000 IndicatesFreeRunmode0x06 Max_Pullin_Range 011001000x0b Ref_Mask 000000000x0d Ref_Rev_Delay 000001010x0e Phase_Offset 000000000x0f Calibration 000000000x11 DPLL_Status 00000000 IndicatesNoActiveReference0x13 Intr_Enable 00000000 IndicatesInterruptsaredisabled0x1c-0x23 Ref(1-8)_Frq_Priority xxxx0000 Frequenciesareautodetected0x33 Chksum xxxxxxx1 Bit0shouldbehightoindicatethat datahasbeenloaded correctlyfromtheEEPROM.



I.TheunitstartsupinFreeRunandoperatesinManualmode.Herearethestepsthatneedtobetakentolocktheunittoa referenceinManualmode.

1. Applysignaltothereferenceinputs. 2. Settheappropriatepullinrangebywritingtoaddress0x06. 3. Avalueof0001xxxx,dependingonwhich(Ref1-8)referencetolockto,shouldbewrittentoaddress0x05. 4. EnableReferencemaskforappropriatereferencesbywritinga1tothereferencebitinaddress0x0b. 5. EnableallInterruptsbywriting11111111toaddress0x13.

II.Tolocktheunittoareferenceinautonomous(automatic)modeafterpoweruporreset,thefollowingstepsshouldbetaken.YoucanalsoswitchfromManualtoAutonomousmodedirectly.Whendoingso,pleaseensurethattheappropriatereferencesareavailablebycheckingREF_AVAILABLEregister(address:0x0c).

1. Clearbit1ofCTL_MODEregister(address:0x04).Thisputsthemoduleinautonomousmode. 2. Applysignaltothereferenceinputs 3. Settheappropriatepullinrangebywritingtoaddress0x06 4. EnableReferencemaskforappropriatereferencesbywritinga1tothereferencebitinaddress0x0b. 5. SetpriorityandrevertivityfortheinputreferencesbywritingtotheappropriateRef_Frq_Priorityregisters(bits3-0). 6. EnableallInterruptsbywriting11111111toaddress0x13. 7. Settheunittooperateinautonomousmodebyclearingbit1ofaddress0x04

III.SlaveModeOperation:

1. AsaSlave,themoduleoperatesinAutonomousmode. 2. TheBandwidthisset,bydefault,to1.6Hz(Bandwidth_PBOregister(Address0x03):00001011). 3. NotethatBit4oftheOP_MODEregister(Address0x05)iscleared. 4. ThevaluesinBits3-0ofthisregisterhavenoeffectontheoperationoftheSlavemodule. 5. FortheSlavemoduletotracktheMasteraccurately,anappropriatePhaseOffsetvalueshouldbewrittento PHASE_OFFSETregister(Address0x0e)isusedtocompensateforthepathdelay. 6. ThemodulewilllocktotheCrossReferenceInput(XREF)fromthemaster.

IVRESETParameters:

1. Theresetpinshouldbeheldlowforaminimumof10millisecondstoensureacompleteresetoccurs. 2. TheSPIinterfaceshouldnotbeaccessedforaminimumof1200msaftertheresetpinisde-asserted.

Switching Master/Slave designations:

ThefollowingstepsneedtobetakenbeforemakingMastermoduleaSlaveandviceversa. 1. CopythevalueinthePHASE_OFFSETregister(Address0x0e)oftheSlavetotheMastermodule’sPHASE_OFFSET regsiter(Address0x0e). 2. ReadthecontentsofBits3-0oftheMaster’sOP_MODEregister(Address0x05)andcopyitintoBits3-0oftheSlave’s OP_MODEregister(Address0x05). 3. ItisrecommendedthatthecontentsofREF(1-8)_FRQ_PRIORITYregisters(Address0x1c-0x23)andREF_MASK register(Address0x0b)fromMasterbecopiedtoSlavetoensureseamlessMaster/Slaveswitches.Master/Slave switchesshouldbeperformedwithminimaldelaybetweenswitchingthestatesofeachofthetwodevices.



Application Notes

Acceptableoutputfrequenciesare:12.96MHz,19.44MHz,25.92MHz,38.88MHz,51.84MHzor77.76MHz.Thedevicewillautodetecttheoutputfrequency. Reference Inputs–Theapplicationmaysupplyupto8referenceinputs,appliedatinputpinsRef1 - 8.Theymayeachbe8kHz,1.544MHz,2.048MHz,12.96MHz,19.44MHz,25.92MHz,38.88MHz,51.84MHzor77.76MHz.Thedeviceauto-detectsthereferencefrequencies,andtheymaybereadfromtheRef(1-8)_Frq_Priorityregistersinregistercontrolmode,asdescribedinthecontrolmodesectionsthatfollow. Referenceswitchesareperformedinahitlessmanner.However,iftheapplicationexternallychangesthefrequencyofaparticularreference,thedevicerequires20mstoauto-detectthenewfrequency.Manualswitchestoafrequencychangedreferenceshouldnotbemadeduringthisinterval.Automaticreferenceselectionmodeaccountsfortheauto-detectioninthereferencequalification. Referenceswouldtypically(butneednotbe)connectedindecreasingorderofusagepriority.ForexampleifredundantBITSclocksareavailable,theywouldtypicallybeassignedtoRef1 andRef2,withothertransmissionderivedsignalsfollowingthereafter. Master/Slave operation–Forsomeapplications,reliabilityrequirementsmaydemandthattheclocksystembeduplicated.TheSM3-8Rdevicewillsupportthemaster/slaveduplicatedconfigurationforsuchapplications.Tofacilitateit’suse,thedeviceincludesthenecessarysignalcrosscouplingandcontrolfunctions.Redundancyforreliabilityimpliestwomajorconsiderations:1)Maintainingseparatefailuregroupssuchthatafailureinonegroupdoesnotaffectit’smate,and2)Physicalandlogicalpartitioningforrepair,suchthatafailedcomponentcanbereplacedwhilethemateremainsinservice,ifsodesired.Systemdesignneedstoaccounttomeetsystemlevelgoals.

Master / Slave ConfigurationFigure 8

STC3500

SM3-8R

8 kHz

M/S REF

REF 8

REF 1

2

SM3-8R1

M/S REF

8 kHz

Synchronized clock output

Synchronized clock output

REF1

REF8

REF1

REF8

M/S_OUT

OUTPUT1

BITS_CLK

OUTPUT1

M/S_OUT

BITS_CLK

BITS c lock output

BITS clock output



Application Notes continued

Master/Slave Configuration–Apairofdevicesareinterconnectedbycross-couplingtheirrespectiveM/S Outputs orOutput1totheotherdevice’sM/S REFinput(SeeFigure8).Additionally,thereferenceinputsforeachdevicewouldtypicallybecorrespondinglythesame,sothatwhenaMaster/Slaveswitchoccurs,synchronizationwouldcontinuewiththesamereference.Thereferencesmaybedrivenbythesamesignaldirectlyorviaseparatedrivers,astheredundancyofthatpartofthesystemrequires.Distributionpathlengthsarenotcriticalhere,asaphasebuild-outwilloccurwhenadeviceswitchesfromslavetomaster. ThepathlengthsofthetwoM/SOutputtoM/S REFsignalsisofinterest,however.Theyneednotbethesame.However,toaccommodatepathlengthdelays,theSM3-8Rprovidesaprogrammablephaseskewfeature,whichallowstheapplicationtooffsettheoutputclockfromthecross-referencesignalby-32nsto+31.75ns.Thisoffsetmaythereforebeprogrammedtoexactlycompensatefortheactualpathlengthdelayassociatedwiththeparticularapplication’scross-referencetraces.Theoffsetmaybefurtheradjustedtoaccommodateanyoutputclockdistributionpathdelaydifferences.PhaseoffsetisprogrammedbywritingtothePhase_Offsetregister,andistypicallyaone-timedeviceinitializationfunction.(SeeregisterdescriptionandRegisterAccessControlsections).Thus,master/slaveswitcheswiththeSM3-8Rdevicesmaybeaccomplishedwithnear-zerophasehits. ForapplicationsthatuseHardwareControlonly(i.e.phaseoffsetprogrammingisnotavailable),itisdesirabletokeepthecrosscouplepathlengthsataminimumandrelativelyequalinlength,asthepathlengthwillappearasaphasehitintheslaveclockoutputwhenamaster/slaveswitchoccursinaHardwareControlconfiguration. Master/Slave Operation and Control–TheMaster/Slavestateisalwaysmanuallycontrolledbytheapplication.MasterorslavestateofadeviceisdeterminedbytheMASTER SELECT pin.Choosingthemaster/slavestatesisafunctionoftheapplication,basedontheconfigurationoftherestofthesystemandpotentialdetectedfaultconditions. WhenoperatinginHardwareControlorRegisterAccessManualControlmode,itisimportanttosettheslavereferenceselectionthesameasthemastertoensureuseofthesamereferencewhen/iftheslavebecomesmaster.InRegisterAccessManualControlmode,theRef_Maskregistershouldalsobewrittentothesamevalueforbothdevices. Master/slaveswitchesshouldbeperformedwithminimaldelaybetweenswitchingthestatesofeachofthetwodevices.Thiscanbeeasilyaccomplished,forexample,bycontrollingthemaster/slavestatewithasinglesignal,coupledtooneofthedevicesthroughaninverter. InthecaseofRegisterAccessAutomaticControlmode,wherereferenceselectionisautomatic,itisnecessarytoreadtheoperationalmodeBITS3-0)fromthemaster’sOp_Moderegisterandwriteittotheslave’sOp_Moderegister.Themaster’sreferenceselectionwillthenbeusedbytheslavewhenitbecomesmaster.Inadditiontohavingthereferencespopulatedthesame,andinthesameorderforbothdevices,itisdesireabletowritethereferencefrequencyandpriorityregistersRef(1-8)_Frq_PriorityandtheRef_Maskregisterstothesamevaluesforbothdevicestoensureseamlessmaster/slaveswitches. Reset–Deviceresetisaninitializationtimefunction,whichresetsinternallogicandregistervalues.Aresetisperformedautomaticallywhenthedeviceispoweredup.Registersreturntotheirdefaultvalues,asnotedintheregisterdescriptions.Devicemodeandfunctionalityfollowingaresetaredeterminedbythestateofthevarioushardwarecontrolpins. Holdover History Accumulation and Maintenance -- Holdoverhistoryaccumulationandmaintenancemaybecontrolledingreaterdetailifregisterbusaccesstothedeviceisprovided.Holdoverhistoryaccumulationandcontrolencompassesthreedeviceinternalregisters,threebusaccessregistersforcontrolandaccess,andtwostatusbitsintheDPLL_Statusregister.

Oncelockhasbeenachieved,holdoverhistoryiscompiledintheaccumulationregister.ItistransferredtotheActiveholdoverhistorywhenitisready(typicallyinabout15minutes).The“HoldoverAvailable”bitandoutputpinaresetto“1”.Fromthenon,theActiveholdoverhistoryiscontinuallyupdatedandkeptinsyncwiththeholdoverhistoryaccumulationregister.(SeeFigure11).

Hold Over History Accumulation Register

ActiveHold Over History

BackupHold Over History




Hold Over History access and Control RegistersTable 5

Register Register Name Description0x25 History_Policy SetspolicyforHoldOverhistoryaccumulation:“Rebuild”or“Continue”0x26 History_Cmd Save,restore,andflushcommandsforHoldOverhistory0x27 Holdover_Time IndicatesthetimesinceenteringtheHoldOverstate0x11 DPLL_Status Bits3and4:HoldOverAvailable”and“HoldOverBuildComplete”

Build HistoryHold Control = 0

Hold Available = 0

Acquire ReferenceHold Control = 0

Hold Available = 0

Locked, History Complete

Hold Control =1Hold Available = 1

Acquire ReferenceHold Control = 0

Hold Available = 1

Build HistoryHold Control = 0

Hold Available = 1

Reference Switch

Reference Switch

Reference Switch

Reference Switch

Reference Switch

Reference Lock(with "Continue" set)

Reference Lock(with "Rebuild" set)

Reference Lock

Flush

Flush

FlushHistory Build Complete

History Build Complete,

Replace Active Hold Over History

History Restored from backup,re-start the building procedure.

Hold Over History and Status StatesFigure 9




Boundary Scan IEEE1149.1-2001 (Limited Testability Support) - ThismoduleexposesaboundaryscanchainwhichcontainsoneormoreboundaryscantestableIEEE1149.1-2001complaintdevices.TheexposedboundaryscanchainisIEEE1149.1-2001compliant,andsupportsalldocumentedtestingmodesofdevicescontainedwithinchain.Integrationofthismoduleintoanexistingboundaryscanchainwillrequirethefollowing. -Substitutionofmodulesfootprintwithprovidedtestabilitymodelschematic. -Modifiednetlistwillneedtobeloadedintoboundaryscantestvectorgenerationsoftware.TestabilityModelSchematicandBSDLfile(s)canbeobtaineddirectlyfromfactory.

Control Modes Thedevicecaninturnbeoperatedinamanualcontrolmode,orautomaticcontrolandreferenceselectionmode. Reset maybepulledlowforaminimumof100nSduringchipstart-up(oranyotherdesiredtime)toinitializethefulldevicestate.However,power-upwillalsoperformareset,soinaminimalconfiguration,Reset maybetiedinputhigh. TheBITSclockoutputfrequencyisselectedbytheT1/E1pin.WhenT1/E1=1,theBITSfrequencyis1.544MHz,andwhenT1/E1=0,theBITSfrequencyis2.048MHz. MASTER SELECT-Determinesthemasterorslavemode.Setto“1”foramaster,and“0”foraslave.Master/slaveswitchesshouldbeperformedwithminimaldelaybetweenswitchingthestatesofeachofthetwodevices.Thiscanbeeasilyaccomplished,forexample,bycontrollingthemaster/slavestatewithasinglesignal,coupledtooneofthedevicesthroughaninverter. Forsimplexoperation,thedeviceshouldbeinMastermode-setMASTER SELECTto“1”.

Holdover History Accumulation and Maintenance continued –Wheneverholdoverisentered,itistheActiveHoldoverHistorythatisusedtodeterminetheholdoverfrequency.TheHistory_Cmdregisterallowstheapplicationtoissuethreeholdoverhistorycontrolcommands: 1)SavetheActiveHoldoverHistorytotheBackupHistory. 2)RestoreaBackupHistorytotheActive. 3)FlushtheactiveHistoryaswellastheaccumulationregister.TheBackuphistoryremainsintact. BoththeActiveandtheBackupholdoverhistoriesareloadedwiththecalibratedfreerunsynthesizercontroldataonreset/power-up. Theapplicationmightusethe“savetobackup”inasituationwhere,forexample,theprimaryreferenceisknowntobeofhigherqualitythananysecondaryreferences,inwhichcaseitmaybedesirabletosaveandthenrestoretheholdoverhistoryaccumulatedontheprimaryreferenceiftheprimaryreferenceislostandholdoverisentereduponlossofasecondaryreference.Userscanrestorethehistoryfrombackupanytime,evenwhileoperatinginHoldovermode.Thefrequencytransientwillbesmoothandcontinuous.Itistheresponsibilityofapplicationsoftwaretokeeptrackoftheageandviabilityoftheholdoverbackuphistory.Giventimeandtemperatureeffectsonoscillatoraging,theapplicationmaywishtoperiodicallyperforma“Save”oftheActivehistorytokeepthebackupcurrent. Whenswitchingtoanewreference,theactiveholdoverhistorywillremainintactandmarkedas“HoldoverAvailable”(ifitwasavailablebeforethereferenceswitch)untilanewhistoryisaccumulatedonthenewreference(Typically15minutesafterlockhasbeenachieved).Duringthenewhistoryaccumulation,the“HoldoverBuildComplete”bitisreset.Oncethenewhistoryaccumulationiscomplete,itistransferredtotheActiveHistoryandthe“HoldoverBuildComplete”bitisset.Theactivehistorywillthencontinuetobeupdatedtotrackthereference. TheHistory_Policyregisterallowstheapplicationtocontrolhowanewhistoryisbuilt.Whensetto“Rebuild”: 1)Historyaccumulationbeginswhenlockisachievedonthenewreference. 2)Theholdoverhistoryisrebuilt(takingabout15minutes).TheActiveHistoryremainsuntoucheduntilitisreplacedwhenthebuild iscomplete. Whenthepolicyissetto“Continue”: 1)Ifthereisno“Available”ActiveHistory,anewbuildoccurs,asunderthe“Rebuild”policy. 2)Ifthereisan“Available”ActiveHistory,itwillcontinue,theaccumulationregisterwillbeloadedfromtheActiveHistory,andthe“Build”processisessentiallycompletedimmediatelyfollowinglockonthenewreference. The“Continue”policymaybeusedbytheapplicationif,forexample,itisknownthatthereferenceswitchedtomaybetracedtothesamesourceandthereforelikelyhasnofrequencyoffsetfromthepriorreference.Inthatcase,the“Continue”policyavoidsthedelayofrebuildingtheholdoverhistory.Iftheswitchislikelytobebetweenreferenceswithknownorunknownfrequencyoffset,thenitispreferabletousethe“Rebuild”policy. ThetimesincetheholdoverstatewasenteredmaybereadfromtheHoldover_Timeregister.Valuesarefrom0to255hours,limitedat255,andresetto0whennotintheholdoverstate.



Mechanical DimensionsFigure 10

.070 [1.78mm]

.515 [13.08mm]

2.050 [52.07mm]

1.100 [27.94mm]

.075 [1.91mm]

.100 [2.54mm].018 [.46mm]

PIN 1

.150 [3.81mm]

1.250 [31.75mm]

0.000

0.100

1.200

1.300

0.00

0

0.30

0

0.40

0

0.50

0

0.60

0

0.70

0

0.80

0

0.90

0

1.00

0

1.10

0

1.20

0

1.30

0

1.40

0

1.50

0

1.60

0

1.70

0

1.80

0

2.10

0

HOLE/PAD SIZE (32 PLACES):

1. UNSOCKETED MODULE: 0.028" DIA. PLATED HOLE WITH 0.060" DIA. PAD.

2. SOCKETED MODULE: 0.038" DIA. PLATED HOLE WITH 0.070" DIA. PAD.

NOTE: For compatibllity with both the unsocketed and socketed modules, Connor-Winfield recommends using a 0.038" DIA. plated hole with 0.070" DIA. pad

PIN 1

TOP VIEW

KEEP OUT AREA

CUSTOMER COMPONENT

Footprint DimensionsFigure 11

Mechanical Specifications



Required External Components1. Placeseriesresistors(33ohms)onallreferenceinputs(Pins4-7&15-18).2. Placeseriesresistors(33ohms)onSPI_INandSPI_CLKinputs(Pins25,26).3. Placeone.01uFandone47-100uFcapacitorattheinputpowerpin(Pin27).4. One4.7uF(25V)capacitorisrequiredattheVPPpin(Pin14).5. One4.7uF(25V)capacitorisrequiredattheVPNpin(Pin19).

Optional Socket Mounting RecommendationsMatingsocketsmaybeusedifpermanentinstallationoftheSM3moduleisnotdesired.Twopossiblesourcesforthesesocketsinclude: 1. Samtec,“LowProfileSocketStrips”,SLSeries,PNSL-116-G-19.(http://www.samtec.com/) 2. Mill-Max,“Single-In-LineSockets”,315Series,PN315-xx-114-41-001.(http://www.mill-max.com/)

TheSM3-8Rrequirestwo16-pinsockets.TheoptionaldualfootprintconfigurationshowninFigure14requiresone14-pinandtwo16-pinsockets.

Mechanical Specifications continued

PCB Layout Recommendations1. Orientmodulesoairflowisparallelalongtheheaderstrips(pins).2. Placede-couplingand/orfiltercomponentsasclosetomodulepinsaspossible.3. DonotplaceanycomponentsdirectlybeneaththemoduleonthetopsideofthehostPCB.4. Ensurethatonlycleanandwell-regulatedpowerissuppliedtothemodule.5. Isolatepowerandgroundinputstothemodulefromnoisysources.6. Providepowerandgroundconnectionsthrougha0.050”widetrace(minimum)using1-oz.Cuorequivalentcopperfeature (i.e.internalplane,copperareafill,etc.).7. Keepmodulesignalsawayfromsensitiveornoisyanaloganddigitalcircuitry.8. Avoidsplitgroundplanesashigh-frequencyreturncurrentsmaybeaffected.9. Allowextraspacingbetweentracesofhigh-frequencyinputsandoutputs.10. Keepalltracesasshortaspossible-avoidmeanderingtracepaths.11. AvoidroutingsignalsdirectlybeneaththemoduleonthetopsideofthehostPCB.12. Ifpossible,provideacopperareadirectlybeneaththemoduleonthetopsideofthehostPCB.Connectthiscopperareatoground.13. ItisrecommendedthattheconnectionsoftheJTAG,VPPandVPNpinsberoutedtopads,preferablyinaSILpatternasshown inFigure13below.Itisrecommendedtouse0.1”centertocenterspacing.

1 8

VP

P

VP

N

GN

D

TC

K

TD

I

TD

O

TM

S

RC

K

Figure 13



Optional SM3/SM3-8R Dual Footprint

AdualfootprintconfigurationmaybeusedwhendesigningahostcircuitboardcontainingtheConnorWinfieldSM3orSM3-8Rmodules.ThesmallerSM3containsasubsetofthesignalpinsfoundonthelargerSM3-8RinlocationswhichallowforasimpledualfootprintarrangementliketheoneshowninFigure14.

ThemodulesshowninFigure1arearrangedinaleft-justifiedfashion.Noticethatrightjustifiedorcenterjustified(withanadditionalcolumnofSM3pins)arrangementsarealsopossible,dependingonthedesigner’spreference.

Placementofexternalcomponents 1. Placeseriesresistors(33ohms)onallreferenceinput(SM3Pins4-7,SM3-8RPins4-7&15-18). 2. Placeseriesresistors(33ohms)onSPI_INandSPI_CLKinputs(SM3Pins21,22,SM3-8RPins25&26). 3. Placeone.01uFandone47-100uFcapacitorattheinputpowerpin(SM3Pin23,SM3-8RPin27). 4. One4.7uF(25V)capacitorisrequiredattheVPPpin(SM3&SM3-8RPin14). 5. One4.7uF(25V)capacitorisrequiredattheVPNpin(SM3Pin15,SM3-8RPin19).

BesuretoconsultConnorWinfield’srespectivedatasheetsforadditionalmechanical,electrical,footprintandkeep-outinformation.

Figure 14

Mechanical Specifications continued

SM3

SM3-8R

1

14 15

LOS

LOL

M/S REF

REF1

REF2

REF3

REF4

TDI

TMS

TRST

BITS_CLK

M/S_OUT

OUTPUT1

VPP

REF5

REF6

MASTER SELECT

SPI_INT

SPI_OUT

RESET

SPI_ENBL

Vcc

SPI_IN

SPI_CLK

GND

TCK

TDO

HOLD_GOOD

T1/E1

VPN

REF7

REF8

2

3

4

5

6

7

8

9

10

11

12

13 16

17

18

19

20

21

22

23

24

25

26

27

28

15

1617

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

0.850"

1.100"

(TOP VIEW)



Ordering Information SM3-8R-XXX.XXM

ReplaceXXX.XXwithoneofthefollowingavailablefrequencies,012.96MHz,019.44MHz,025.92MHz,038.88MHz,051.84MHzor077.76MHz.

PleasecontactConnor-Winfieldforotherfrequenciesthatmaybeavailable.

SimilarProductsfromConnor-Winfield SM3G5-XXX.XXM-Stratum3modulewith4inputreferences. SM3G5-IT-XXX.XXM-IndustrialtemperatureratedStratum3modulewith4inputreferences. SM3EG5-XXX.XXM-Stratum3Emodulewith8inputreferences.

2111 Comprehensive Drive

Aurora, Illinois 60505

Phone: 630-851-4722

Fax: 630- 851- 5040

www.conwin.com

Revision RevisionDate Note00 02/17/04 FinalReleaseDataSheet01 08/23/04 CorrectedTypos02 10/15/07 AddInitializationinfo,Pg.22-2303 11/07/08 AddedInputPulseWidthSpectoTable104 07/27/10 PinDescriptionUpdates05 01/26/11 SerialBusTimingupdatestodrawings

sm3-8r 8 reference stratum 3 module · 17 ref8 reference input 8 – 8 khz to 77.76 mhz auto...

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