December 2012

Sixth Semester B.E. Degree Examination

Microprocessors

Note: 1. Answer any FIVE full questions, selecting at least two questions from each part.

PART - A

1. a. With neat block diagram, explain how 8086 CPU supports pipelined architecture.(10 Marks) Ans:

Memory Interface

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BIU C-BUS

_

6

5 Instruction B - BUS 4 Stream

ES

Byte

3

CS

Queue

2

SS

1

DS

IP

Control

System

EU A - BUS

AH AL

BH BL ARITHMETIC

CH CL LOGIC UNIT

DH DL

SP

BP

SI OPERANDS

DI

FLAGS

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1. b.

Ans:

1. c.

Ans:

December 2012 Microprocessors The 8086 microprocessor consists of two independent units: 1. The Bus Interface unit, and 2. The Execution unit. The word independent implies that these two units can function parallel to each other. In other

words they may be considered as two stages of the instruction pipeline. i) The Bus Interface Unit :

The BIU primarily interacts with the system bus. It performs almost all the activities relating to

fetch cycle such as:

Calculating the physical address of the next

instruction. Fetching the instruction. Reading or writing data memory or I/O port from memory or Input/Output. Instruction Queue: The instruction queue is used to store the instruction “bytes” fetched. Please

note two points here; that it is (1) A byte (2) Queue. This is used to store information in byte form,

with the underlying queue data structure. The advantages of this queue would only be if the next

expected instruction is fetched in advance, thus, allowing a pipeline of fetch and execute cycles. ii) Execution Unit (EU): Execution unit performs all the ALU operations. The execution unit of

8086 is of 16 bits. It also contains the control unit, which instructs bus interface unit about

which memory location to access, and what to do with the data control unit also performs

decoding and execution of the instructions. Explain signi_cance of special bit indicators available in 8086. (05 Marks) The special bit indicators are W-Bit: If an instruction can operate on either a byte or a word, the op code includes a W-bit

which indicates whether a byte (W = 0) or a word (W = 1) is being accessed. D-bit: For double operand instructions, one of the operands must be a register speci_ed by a

REG _eld. For these instructions the D-bit is used to indicate whether the register speci_ed by

REG is the source operand (D = 0) or the destination operand (D = 1). S-bit: An 8-bit 2‟s complement number can be extended to a 16-bit 2‟s complement number by

letting all of the bits in the high-order byte equal the MSB in the low order byte. This is referred to as sign extension. The s-bit appears with the W-bit in the immediate to

register/memory add, subtract, and compare instructions and is assigned as follows: 8-bit operation - S : W = 00 16-bit operation with a 16-bit immediate operand -S : W = 01 16-bit operation with a sign extended 8-bit immediate operand -S : W = 11 V-bit: Used by shift and rotate instructions to determine the number of shifts Z-bit : Used by the REP instruction If the opcode of MOV instruction is 100010 then nd machine code for MOV[BX + 24h], AL.

(05 Marks) 1000 1000 0100 0111 0010 0100 h

8 8 4 7 2 4

Microprocessors December 2012 2. a. With respect to 8086 CPU explain the following:

i) LDS BX, [LOC] ii) DAS iii) LOOP iv) DB V) Length. (10 Marks) Ans:- i) LDS, BX, [LOC]

BX (LOC))

DS ((LOC)+2)

ii) DAS

(AL) Difference in AL adjusted

to packed BCD

format

iii) LOOP Format LOOP OPR

Test condition

(CX)

iv) DB Define byte

Array DB 12h

v) Length Returns the number of units assigned to a variable

Eg- FEES DW 100DUP (0)

MOV CX, LENGTH FEES; CX 100

2. b. Bring out the difference between

MOV AX, BX and MOV AX, [BX]. (02 Marks)

Ans: In MOV AX, BX, the content of BX register is copied into AX.

In MOV AX, [BX], the content of memory location pointed by BX is copied into AX.

2. c. WALP to pack the two unpacked BCD numbers stored in the locations LOC and LOC + 1. (05 Marks)

Ans:

MOV CL, 04H

RRC [LOC + 1], CL

MOV AL, [LOC]

OR AL, [LOC + 1] 2. d. Replace the following program segment by its single equivalent

instruction: NEG BL ADD AL, BL

CMC. (03 Marks)

Ans: SUB AL, BL

3. a. Using table translation method WALP to _nd equivalent seven segment code for given BCD

digit. (08 Marks)

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December 2012 Microprocessors

Ans: a

f

b

g

e

d

c

Fig. (a) Seven-Segment display unit

Decimal Digit Display Unpacked BCD format g f e d c b a code in Hex

form

0

00000000

0

1 1 1 1 1

1 3F

1 00000001 0 0 0 0 1 1 0 06

2

00000010 1

0 1 1 0 1 1 5B

3

00000011

1

0 0 1 1 1

1 4F

4 00000100 1 1 0 0 1 1 0 66

5

00000101

1

1 0 1 1 0

1 6D

6

00000110

1

1 1 1 1 0

1 7D

7

00000111 0

0 0 0 1 1 1 07

8

00001000

1

1 1 1 1 1

1 7F

9

00001001

1

1 0 1 1 1

1 6F

Fig. (b) Seven segment code equivalent for BCD digits Model small data

bcdnum db 5

table db 3fh, 6h, 5bh, 4fh, 66h, 6dh, 7dh, 7h, 7Fh, 6Fh

code

Mov ax, @ data Mov ds, ax Mov al, bcdnum Lea bx, table Xlat table Mov ah, 4ch int 21h end

3. b. WALP to read a string from key board and check whether it is a palindrome or not. If palindrome display PAL else NPAL on monitor. (12 Marks)

Ans: _ model small

_ data

msg 1 db 10, 13; „Enter the string‟;, $‟

msg 2 db 10, 13, „PAL‟, $‟

msg 3 db 10, 13‟ „NPAL‟, „$‟

3- Micro processors december 2012.indd 42 26/01/2014 0

Microprocessors December 2012

array db 80h

count db 00

strg db 80h dup

(?) _ code

mov ax, @ data

mov ds, ax

lea dx, msg

1 mov ah,

09h int 21h

lea dx, array

mov ah, oah

int 21h mov

cx, 0

mov cl,

count mov

si, 0 mov di,

cx dec di

shr cx, 1

bk 1: mov al, strg [si]

cmp.al, strg [di]

jnz skp 1

inc si,

dec di

loop di

lea dx, msg

2 jmp skp 2

skp1: lea dx, msg

3 skp2: mov ah,

09h int 21h

mov ah,

4ch int 21h

end 4. a. What is an interrupt? Discuss the interrupt classi_cation in 8086. (07 Marks) Ans: The action that prompts the execution of one of these routines is called an interrupt and the routine

that is executed is called an interrupt routine. There are 2 general classes of interrupts and associated routines. There are the internal interrupts

that are initiated by the state of the CPU or by an instruction and the external interrupts that are

caused by a signal being sent to the CPU from elsewhere in the computer system. Regardless of the type of interrupt, the actions that result from an interrupt are the same and are

known as the interrupt sequence.

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December 2012 Microprocessors

The type associated with a division error interrupt is 0. Therefore, if a division by 0 is attempted,

the computer will push the current contents of the PSW, CS, and IP onto the stack, fill the IP

and CS registers from address 00000 and 00002. The type 1 interrupt is the single-step trap and is the only interrupt controlled by the TF flag. If

the TF flag is enabled, then an interrupt will occur at the end of the next instruction that will

cause a branch to the location indicated by the contents of 00004 through 00007. The type 2 interrupt is the non- maskable external interrupt. It is the only external interrupt that

can occur regardless of the IF flag setting.

If the information to be printed is the same for all breakpoints, then the 1-byte INT instruction can be

employed, but if the information is to vary, then a type needs to be included in the instruction.

The INTO instruction has type 4 and causes an interrupt if and only if the OF flag is set to 1. It is

often placed just after an arithmetic, instruction so that special processing will be done if the

instruction causes an overflow. 4. b. Explain microprocessor’s response for an INTR interrupt. (06 Marks)

Ans:

MAIN LINE INTERRUPT

PROGRAM SERVICE

PUSH FLAGS PROCEDURE

CLEAR IF

CLEAR TF PUSH REGISTERS

PUSH CS

PUSH IP

FETCH ISR ADDRESS

POP IP

POP CS

POP REGISTERS 1 RET

POP FLAGS

Fig. 8086 interrupt response

The 8086 responds, to the interrupt by stepping through the following series of major actions

1. It decrements the stack pointer by 2 and pushes the _ag register on the

stack.

2. It disables the 8086 INTR interrupt input by clearing the interrupt _ag (IF) in the _ag register.

3. It resets the trap _ag (TF) in the _ag register.

4. It decrements the stack pointer by 2 and pushes the current code segment register contents on the stack.

5. It decrements the stack pointer by 2 and pushes the current instruction pointer contents on the stack.

6. It does an indirect far jump to the start of the procedure you wrote to respond to the interrupt.

4. c. What do you mean by an IVT? Explain IVT of 8086 microprocessor. (07 Marks)

Ans: The interrupt vector table (IVT) is located in the _rst 1024 bytes of memory at addresses 000000H-

0003FFH. It contains 256 different four-byte interrupt vectors. An interrupt vector contains the address (segment and offset) of the interrupt service procedure.

Microprocessors December 2012

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Fig. Interrupt vecotr table

5. a.

Ans:

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5. b.

Ans:

December 2012 Microprocessors

PART - B

Differentiate between memory mapped I/O and I/O mapped I/O schemes, (04 Marks)

Memory mapped I/O I/O mapped I/O

1. Memory mapped I/O is mapped into same address 1. I/O mapped I/O (also known as port mapped I/O)

space as program memory. uses a separate, dedicated address space.

2. It is accessed in the same way. 2. Accessed via a dedicated set of microprocessor

instructions.

3. Less complex and less number of pins. 3. More complex and more number of pins.

4. Microprocess as that Don‟t support port mapped 4.Microprocessors that support port mapped I/O

I/O (and hence require the use of memory include the intel × 86.

mapped I/O).

With neat diagram write an 8086 program for 4x4 matrix keyboard interface and display

key value on monitor. (10 Marks)

+5V

OUTPUT

01 C D E F

PORT

D

0 8 9 A B

D1 4 5 6 7

D2

0 1 2 3

D3

10K_

INPUT

02

PORT

D7

D6

D5

D4

D3

D2

D

1

D0

DATA SEGMENT WORD PUBLIC TABLE DB 77H, 7BH, 7DH, 7EH, 0B7H, 0BBH, 0BDH,

0BEH 007H, 0DBH, ODDH, 0DEH, 0E7H, OEBH, 0EDH,

0EEH DATA ENDS, STACK_SEG SEGMENT DW 30 DUP (0) TOP_STACK LABEL WORD STACK_SEG ENDS

Microprocessors

CODE SEGMENT WORD PUBLIC

December 2012

ASSUME CS : CODE, DS:DATA, SS : STACK,

SEG START : MOV AX, STACK _ SEG MOV SS, AX

MOV SP, 0FFSET TOP_STACK

MOV AX, DATA

MOV DS, AX

MOV DX, 0FFFFH

MOV AL, 10001011B

OUT DX, AL

CALL KEYBRD

NOP

KEY BRD PROC NEAR

PUSH F

PUSH BX

PUSH CX

PUSH DX

MOV AL, 00

MOV DX, 0FFF9H

OUT DX, AL

MOV DX, 0FFFBH

WAIT_OPEN IN AL, DX

AND AL, 0FH

CMP AL, 0FH

JNE WAIT_OPEN

WAIT_PRESS IN AL, DX

AND AL, 0FH

CMP AL, 0FH

JE WAIT_PRESS

MOV CX, 16EAH

DELAY: LOOP DELAY

IN AL,DX

AND AL, 0FH

CMP AL, 0FH

JE WAIT_PRESS

MOV AL, 0FEH

MOV CL, AL

NEXT_ROW: MOV DX, 0FFF9H

OUT DX, AL

KYBRD

Zero To

All Rows

Read Columns

No

All keys

open?

Yes

Read Columns

key

pressed?

Yes

WAIT

20ms

Read Columns

No

key

pressed?

Yes

Output Zero to

One Row

Read Columns

No key

Found?

Yes

Convert To Hex

RETURN

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DETECT

DE BOUNCE ENCODE

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Microprocessors

MOV DX, 0FFFBH

IN AL, DX

AND AL, 0FH

CMP AL, 0FH

JNE ENCODE

ROL CL, 01

MOV AL, CL

JMP NEXT_ROW

ENCODE: MOV BX, 000FH

IN AL, DX

TRY_NEXT: CMP AL, TABLE [BX]

JE DONE

DEC BX

JNS TRY_NEXT

MOV AH, 01

JMP EXIT

DONE : MOV AL, BL

MOV AH, 00

EXIT: POP DX,

POP CX

POP BX

POP F

RET

KEYBRD ENDP

CODE ENDS

END

5. c. WALP to rotate the stepper motor for 270° in antic lock wise direction. (06 Marks)

Ans:- _ Model small

_ data

Pa equ 09800h

Pb equ 09801h

cwr equ 09803h

_

code

MOV ax, @ data

MOV ds, ax

MOV dx, cwr

MOV al, 80h

out dx, al

MOV cx, 150

MOV al, 088h

bk: MOV dx, pa

out dx, al

Microprocessors December 2012

ror al, 01h call delay loop bk MOV ah, 4ch int 21h delay proc near push cx push bx MOV Cx, 0FFFFh l 1 : MOV bx, 0FFH l 2 : dec bx jnz l 2 loop l 1 pop bx pop cx ret delay end p end

6. a. Explain data types for 8087 NDP.

Ans:- Data type Bytes Approximate Range (decimal)

Word integer 2 –32, 768 to 32, 767

Short integer 4 –2 × 109 to 2 × 10

9

Long integer 8 – 9 × 1018

to 9 × 1018

Packed BCD 10 –1018

+ 1 to 1018

– 1

Short real 4 ± 1 × 10–38

to ± 3 × 10–38

Long real 8 ± 10–308

to ± 10308

Temporary real 10 ± 10–4932 to ± 104932

6. b. Represent 20.5937510 into short real form.

Ans: 010000011 0100100110 . . 0 = 41A4C00016

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(10 Marks)

Format

S Magnitude 15 0

S Magnitude 31 0

S Magnitude 63 0

S 0 D

17 D

16 D

1

D6

79 78 72 0

S E F

31 30 23 22 0

S E F

63 62 52 51 0

S E F

73 78 64 63 0

(04 Marks)

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December 2012 Microprocessors 6. c. Explain the following with respect to 8087 coprocessor:

i) FLD src ii) FADD iii) FLDPI. (06 Marks) Ans: FLD Src : Decrements stack, converts the content of src into temp real and stores

on to stack. FADD : (DST) (DST) + (src)

FLDPI : Places PI values on stack 7. a. Write a note on:

Minimum mode con_guration of 8086. (10 Marks) Ans:

Clock

(8284 A)

CLK BHE

RESET

READY

MN/MX +5V Address

ALE Latches Address bus

BHE (3 82828)

A19-A16

AD15-AD0

8086 Transceivers

Data bus

(2 82865)

DEN Optional

DT/R

M/IO

WR

RD

HOLD

HLDE Control bus

INTR

INTR

READY

RESET

Fig. Minimum mode system

Microprocessors December 2012

Pin de_nitions for the minimum mode

Pin Symbol In/Out Description

_____ 3-State

24 INTA 0 - 3 Indicates recognition of an interrupt request. Consists of two

negative going pulses in two cansecutive bus cycles

25 ALE 0 Indicates an address is available on the address pins

_____

26 DEN 0 - 3 Used to inform the transceivers that the CPU is ready to send

_ or receive data.

27 DT/R 0 - 3 Indicates to the set of transceivers whether they are to transmit

__ (1) or receiver (0) data

281

M/IO 0 - 3 Distinguishes a memory transfer from an I/O transfer. For a

___ memory transfer it is1.

29 WR 0 - 3 When 0, it indicates a write operation is being performed. It

is used in conjunction with pins 28 (M/IO ) and 32 (RD ) to

specify the type of transfer.

30 HLDA 0 Outputs a bus grant to a requesting master pins with tristate

gates are put in high impedance state while HLDA = 1

31 HOLD 1 Receives bus requests from bus master. The 8086/8088 will not

gain control of the bus until this signal is dropped.

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7. b. PCI bus. (05 Marks)

Ans: PCI Bus

Dynamic RAM

Microprocessor

System BWS

Cache

100 MHz

Resident local bus

PCI Bus Video

Disk

Controller

Controller

100 MHz

PCI Bus

ISA Bus Printer FAX/

Controller Interface MODEM

8 MHz

ISA Bus

PCI is the most common bus found in computers today due to plug-and-play

characteristics and ability to function with 64-bit data bus.

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APCI interface contains a series of registers, located in a small memory device, that

contain information about the board.

The information in this registers allow the computer to automatically con_gure the PCI

Card (plug-and play P11 P feature). The microprocessor connects to the PCI bus through an integrated circuit called a PCI bridge thus making the PCI bus independent of processor type and architecture.

PCI functions with either a 32-bit or 64-bit address and data bus. The address and data buses are multiplexed to reduce the size of the edge

connector. 32-bit and 64-bit cards Newest version run at 66MHz (twice the older 33 MHz version)

7. c. Flow chart to generate USB data. (05 Marks) Ans:

Start

Idle

Send Data

Clear count

Get Bit

Bit = 0 Bit ?

Bit = 1

Invert

Output

Output

Output = 1

Output = 0 Increment

Count

Count

Count ! = 6

Count = 6

Send Zero

Bit

Clear count

Done No

Yes

Fig. The data stream and the flow chart used to generate USB data

8. a. With neat block diagram, explain memory organization in 80386 processor. (08 Marks)

Microprocessors

December 2012

Ans:

Bank 3 Bank 2 Bank 1 Bank 0

1G × 8 1G × 8 1G × 8 1G × 8

16 bits

16 bits

32 bits The physical memory system of the 80386DX is 4G bytes in size and is addressed as such. If

virtual addressing is used, 64T bytes are mapped into the 4G bytes of physical space by the

memory management unit and descriptors. The memory is divided into four 8-bit-wide memory banks, each containing upto 1G byte of memory. This 32-bit wide memory organization allows bytes, words, or double words of memory

data to be accessed directly. ____

The 2 memory banks in the 8086, 80286 and 80386SX system are accessed via BLE (A0 on the 8086 and 80286) and BHE. In the 80386DX, the memory banks are accessed via four bank enable signals, BE3 BE0 . This arrangement allows a single byte to be accessed when one bank enable signal is activated by the

microprocessor. It also allows a word to be addressed when two bank enable signals are activated. In most

cases, a word is addressed in banks 0 and 1, or in banks 2 and 3. Memory location 00000000H is in bank 0,

location 00000001H is in bank 1, location 00000002H is in bank 2, and location 00000003H is in bank 3.

8. b. Explain the following terms for 80486 processor.

i) AHOLD ii) BREQ _______

(06 Marks)

iii) FLUSH

Ans: i) AHOLD : Puts address bus in high impedance state. Used by another bus master to gain access for a cache

in validation.

ii) BREQ : Internal bus request.

_______

iii) FLUSH : Active low signal erases the contents of 8KB internal cache.

8. c. Explain branch prediction logic and cache structure of Pentium processor. (06 Marks)

Ans: i) Branch prediction logic: The pentium microprocessor uses a branch prediction logic to reduce the time

required for a branch caused by internal delays. These delays are minimized because when a branch

instruction (short or near only) is encountered, the microprocessor begins prefetch instruction at the

branch address. The instructions are loaded into the instruction cache, so when the branch occurs, the

instructions are present and allow the branch to execute in one clocking period. If for any reason the

branch prediction logic errs, the branch requires an extra 3 clocking periods to execute. In most cases, the

branch prediction is correct and no delay ensues.

ii) Cache structure: The cache in the pentium has been changed from the one found in the

80486 microprocessor. The pentium contains two 8k-byte data cache memories instead of

one as 80486. There is an 8k-byte instruction cache. The instruction cache stores only

instructions, while the data cache stores data used by instructions.

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