sinone chip sc91f8311 · 4 block diagram 1t 8051 core 8kb program rom (flash) 512b ram timer0...

SC91F8311

High Sensitive Capacitive Touch Keys ADC/LCD 8K Flash MCU

SinOne Chip

CONTENT

Content ................................................................................................................................... 1

1 General Description ............................................................................................................ 4

2 Features ............................................................................................................................... 4

3 Pin Definition ....................................................................................................................... 5

3.1 Pin configuration ..................................................................................................................................... 5

3.2 Pin Definition ............................................................................................................................................ 6

4 Block Diagram ..................................................................................................................... 8

5 Flash ROM & SRAM ............................................................................................................ 9

5.1 Flash ROM ................................................................................................................................................ 9

5.2 Code Option Flash Area ........................................................................................................................ 10

5.3 SRAM ....................................................................................................................................................... 10

6 Special Function Registers (SFR) ................................................................................... 13

6.1 SFR Table................................................................................................................................................ 13

6.2 SFR Description ..................................................................................................................................... 13

7 Power, Reset & CLock ...................................................................................................... 16

7.1 Power ...................................................................................................................................................... 16

7.2 Power on reset ....................................................................................................................................... 16

7.3 Reset Mode ............................................................................................................................................. 16

7.4 Clock ....................................................................................................................................................... 18

7.5 32k Crystal and Base Timer .................................................................................................................. 18

7.6 STOP ....................................................................................................................................................... 20

8 Instruction Set ................................................................................................................... 20

8.1 CPU .......................................................................................................................................................... 20

8.2 Addressing Mode ................................................................................................................................... 20

8.3 Instruction Set ........................................................................................................................................ 20

9 Interrupt ............................................................................................................................. 22

9.1 Interrupt Source & Vector ..................................................................................................................... 22

of 65 V 1.3 SinOne Microelectronics Co., Ltd. http: //www.socmcu.com

SinOne Chip SC91F8311

9.2 Interrupt Diagram ................................................................................................................................... 24

9.3 Interrupt Priority ..................................................................................................................................... 24

9.4 Interrupt Handling .................................................................................................................................. 24

9.5 SFR Registers for Interrupt ................................................................................................................... 25

10 Timer0/Timer1 ................................................................................................................. 26

10.1 Timer SFR ............................................................................................................................................. 27

10.2 Timer0 Mode ......................................................................................................................................... 29

10.3 Timer1 Mode ......................................................................................................................................... 31

11 PWM ................................................................................................................................. 32

11.1 PWM Diagram ....................................................................................................................................... 33

11.2 PWM SFR .............................................................................................................................................. 34

11.3 PWM Waveform and Application ........................................................................................................ 36

11.4 The implementation for Two complementary PWM with dead zone .............................................. 37

12 GP I/O ............................................................................................................................... 41

12.1 GPIO Structure ..................................................................................................................................... 41

12.2 I/O SFR .................................................................................................................................................. 43

12.3 I/O port multiplex ................................................................................................................................. 44

13 High Sensitive Touch Key Sensor ................................................................................. 45

14 UART ................................................................................................................................ 45

14.1 UART SFR ............................................................................................................................................. 46

14.2 UART Mode Description ...................................................................................................................... 47

15 Softwar LCD Driver ......................................................................................................... 49

15.1 Software LCD SFR ............................................................................................................................... 49

15.2 Software LCD Driver Usage Instructions And Notes ....................................................................... 50

16 Analog Digital Converter (ADC) ..................................................................................... 54

16.1 ADC SFR ............................................................................................................................................... 54

16.2 ADC Conversion Steps ........................................................................................................................ 56



16.3 ADC Measuring VDD Voltage.............................................................................................................. 56

17 IAP Operation .................................................................................................................. 56

17.1 IAP SFR ................................................................................................................................................. 57

17.2 256B IAP Operation Process and Demo Program ............................................................................ 59

17.3 8K Range IAP Application Notes ........................................................................................................ 59

18 Electrical Characteristics ............................................................................................... 60

18.1 Absolute Maximum Ratings ................................................................................................................ 60

18.2 Recommended Operating Conditions ............................................................................................... 60

18.3 DC Electrical Characteristics .............................................................................................................. 60

18.4 AC Electrical Characteristics (VDD = 2.5V ~ 5.5V, TA = 25℃) ......................................................... 61

18.5 ADC Electrical Characteristics (TA = 25℃) ....................................................................................... 61

19 Application Circuit .......................................................................................................... 62

20 Ordering Information ...................................................................................................... 63

21 Package Information ....................................................................................................... 64

22 Datasheet Change Notice ............................................................................................... 65



1 General Description The SC91F8311 is an enhanced ultra-fast industrial class 1T 8051 Flash microcontroller which also built-in capacitive touch key function. The instruction set is fully compatible with standard 8051 products. The device is integrated with 8-channel touch key circuit. Other features include 8KB Flash ROM (256B used as EEPROM), 512B SRAM, up to 13 GP I/O, all I/O can be used as LCD COM or SEG port in terms of software, two 16-bit timers/counters, 1 independent baud rate UART, 5-channel high-precision 12-bit ADC, 3-channel external interrupt (INT1~3 can be set to Double-Edge triggered); 2-channel 8-bit PWMs, PWM0 output is selectable, which could be switched to 2 different I/O port, internal 1% precision 16/8MHz oscillator, internal 32k oscillator and other resources.

To improve reliability and simplify circuit, the SC91F8311 also features with four optional LVR, precisely tuned 2.4V ADC voltage reference, internal VDD voltage detection circuit, WDT and other high-reliability power supply circuit. The SC91F8311 has excellent anti-jamming performance (EMI, CS, etc.), which could be widely used for the applications like smart appliances, smart home and comsumer products, such as Air Conditioners, Washing Machines, Microwave Ovens, Induction Cooker, Range Hood, Disinfecting Cabinet, Rice Cookers, Electric Pressure Cooker, Toaster, etc.

2 Features Operating voltage: 2.4V~5.5V

Operating temperature: -40 ~ 85℃

Package: SOP16 CPU core: Ultra fast 1T 8051 Memory: 8KB Flash ROM (MOVC prohibits addressing 0000~00FF), 256B can be used for IAP

512B SRAM System Clock:

Built-in 16MHz Oscillator IC system clock can be set to 16/8MHz by the programmer to select

Frequency deviation: no more than ±1％@ (4.5V~5.5V) & (-20~85℃)

Low voltage reset (LVR):

Four Options: 3.65V、3.50V、2.75V、2.60V

Default: configured by user on programmer Flash programming: 4 wire serial programming interface Interrupt (INT):

10 interrupt sources: TIMER0, TIMER1, INT1~3, ADC, PWM, UART, TKS, X32K

INT1~3 can be set to Positive-edge triggered、Negative-edge triggered or Double-

edge triggered two-level interrupt priority

Digital peripherals: 8-channel touch key circuit 13 GP I/O, 4 Modes (P1/P2 are ports for heavy current driver) 16 bit WDT with configurable clock divider ratio

2 standard 80C51 16bit timers: TIMER0、TIMER1

2-channel 8 bit PWM with variable frequency and duty cycle, PWM0 output can be switched to 2 different I/O port

1-channel UART with built-in baud rate generator 1 Base Timer from internal 32k oscillator, for power comsuption saving purpose with

timely wake-up function LCD function, all I/O can output 1/2 VDD, 1/3 VDD, 2/3 VDD voltage, and used as

LCD COM or SEG Analog peripherals:

5 channel 12-bit ADC 1) Built-in precious tuned 2.4V reference voltage 2) Internal reference voltage: VDD and Internal 2.4V 3) AIN0 Internally connected to 1/3 VDD, used for measuring VDD voltage with

internal 2.4V reference voltage 4) AIN1~3, AIN7 can measure external input signal

Power saving mode: STOP MODE

INT1~3, internal 32k OSC or external RSTN interrupt can activate STOP MODE



3 Pin Definition 3.1 Pin configuration

SC

91

F8

31

1

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

VDD

CMOD

VSS

ENB / RSTN / P11

CLK / RXD / P12

TXD / INT1 / P13

DIO / PWM0 / INT2 / P14

CEN / AIN7 / INT3 / P15

P25 / TK13 / AIN2

P24 / TK12 / AIN1

P20 / T0 / TK8

P03 / TK3

P02 / TK2

P01 / TK1 / PWM1A

P00 / TK0 / PWM0A

P26 / TK14 / AIN3



3.2 Pin Definition Pin No Pin Name Pin

Type

Function Description

1 VDD Power 2.4V – 5.5V

2 CMOD I Touch Key sensitivity regulating capacitor

3 VSS Power Ground

4 P1.1/RSTN/ENB I/O 1) P1.1:

GPIO P1.1 (heavy current)

2) RSTN:

RESET pin (Default), low enabled. User circuit can not

be forced to Low while power on (when power-on is initializing,

the default RST can be modified by setting SFRs (RSTCFG)

and set the PIN as an IO.

3) Flash programming pin ENB

5 P1.2/RXD/CLK I/O 1) P1.2:


2) RXD:

UART RXD

3) Flash programming pin CLK

6 P1.3/INT1/TXD I/O 1) P1.3:


2) INT1:

External interrupt 1

3) TXD:

UART TXD

7 P1.4/INT2/PWM0/

DIO

I/O 1) P1.4:


2) INT2:


3) PWM0:

PWM0 output

4) Flash programming pin DIO

8 P1.5/INT3/AIN7/C

EN

I/O 1) P1.5:


2) INT3:


3) AIN7:

ADC input channel 7

4) Flash programming pin CEN

9 P2.6/TK14/AIN3 I/O 1) P2.6:


2) TK14:

Touch key channel 14

3) AIN3:

ADC input channel 3

10 P2.5/TK13/AIN2 I/O 1) P2.5:


2) TK13:


3) AIN2:

ADC input channel 2

11 P2.4/TK12/AIN1 I/O 1) P2.4:


2) TK12:




3) AIN1:

ADC input channel 1

12 P2.0 /T0/TK8 I/O 1) P2.0:


2) T0:

External input of Timer0

3) TK8:

Touch key channel 8

13 P0.3/TK3 I/O 1) P0.3:

GPIO P0.3

2) TK3:

Touch key channel 3

14 P0.2/TK2 I/O 1) P0.2:

GPIO P0.2

2) TK2:

Touch key channel 2

15 P0.1/TK1/PWM1A I/O 1) P0.1:

GPIO P0.1

2) TK1:

Touch key channel 1

3) PWM1A:

PWM1 A output

16 P0.0/TK0/PWM0A I/O 1) P0.0:

GPIO P0.0

2) TK0:

Touch key channel 0

3) PWM0A:

PWM0 A output



4 Block Diagram

1T 8051 CORE

8KB

Program

ROM

(Flash)

512B

RAM

TIMER0

Interrupt Controller

ADC

WAKECNT

Controller

TIMER1

I/O

EEPROMLVD

LVR

Controller

Clock

Controller

clock

reset

inte

rru

pt

2.4V

REG

PWM

WDT

BandGap

Voltage

Reference

LDO

&

Power Manager

ADC

Controller

Touch Key

Controller

LCD

Bias Voltage

Generator

Touch Key

Sensor

UART

+

BaudRate

Generator

IO PADS

16MHz

IRC

IRC

Regulator

IRC

Voltage

Reference

32K IRC

SC91F8311 BLOCK DIAGRAM



5 Flash ROM & SRAM The architecture of Flash ROM and SRAM is as follows:

RAM(Indirect addresses)

0000h

1FFFh

SFR(Direct addresses)

RAM(Direct and Indirect

addresses)00h

7Fh

80h

FFhFlash ROM

For Program

Flash ROM and SRAM

EEPROM1F00h

External RAM(MOVX/DPTR addresses)

0000h

00FFh

5.1 Flash ROM The SC91F8311 has 8KB Flash ROM with the address 0000H ~ 1FFFH. The 256 Bytes Flash of the address 1F00H ~ 1FFFH can be used as EEPROM (for in-application programming, see the IAP chapter for details). The Flash ROM has about 100,000 erase lifecycle with SinOneChip Programmer (SOC PRO51/PRO52 and DPT51/DPT52). Note the 256 Bytes Flash ROM with address 0000H ~ 00FFH can not be addressed by interval MOVC command. The 8KB Flash ROM can also be functioned as blank checking (BLANK), programming (PROGRAM), verifying (VERIFY) and erasing (ERASE), but not for reading (READ). The Flash ROM is programmed by the following pins: Pin4 (ENB), Pin8 (CEN), Pin5 (CLK), Pin7 (DIO), VDD, VSS. The connection diagram is as below:

Jumper

User

Application

circult

SOC

Pro51/Pro52MCU

VDD

ENB

CEN

CLK

DIO

GND

Connection diagram of MCU with

Programmer in ICP Mode



5.2 Code Option Flash Area The SC91F8311 has an individual Flash area for user initial data storage. This area is called as Code

Option area, which can be programmed by SOC Programmer. During chipset reset initialization, the code option will be loaded into SFR as the initial setting data.

IFB Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0

IFB1 - - - DISLVR LVRS[3:0]

IFB2 - - - - IAPS - - -

IFB3 - - - ENWDT - Vrefs IRCFS[1:0]

IFB1 Symbol Description

4 DISLVR LVR enable 0: LVR enabled 1: LVR disabled

3~0 LVRS [3:0] LVR voltage selection 1011: 3.65V 1010: 3.50V 0110: 2.75V 0101: 2.60V The above voltage values are based on normal temperature. The

actual value can vary with temperature (about ±0.1V@-40~85℃). The

LVR valtage will drop a little at higher temperature, and will raise at lower temperature.


3 IAPS IAP range selection 0: IAP performs within 1F00H~1FFFH 1: IAP performs within All 8K FLASH ROM


4 ENWDT WDT enable 0: WDT disabled 1: WDT enabled (However, in the implementation of the IAP, the WDT will stop counting)

2 Vrefs ADC reference voltage selection 0: internal VDD 1: 2.4V tuned internally

0 IRCFS[1:0] System clock selection 00:16MHz 01: 8MHz 10: reserved 11: reserved

5.3 SRAM The SC91F8311 provides 512bytes RAM (including internal RAM and external RAM) for random data

storage. The addresses for the internal RAM are 00H~FFH, The high 128B (address 80H~FFH) are indirect addressable only, the low 128B SRAM are directly and indirectly addressable.

The Special Function Registers (SFR) address is 80H~FFH. The difference between SFR and high 128B SRAM is SFR can be addressed directly, while the high 128B SRAM is indirect addressable only.

The addresses for the external RAM are 00H~FFH, can be addressed only by MOVX.

Internal 256B SRAM: There are three sections for the internal low 128B SRAM: 1) Working registers 0~3, address 00H~1FH. The

current used registers are decided by the combination of the RS0 and RS1 from the register PSW which shows the status for the regristers. It could accelerate the operating speed by using these registers. 2) Bit addressable memory 20H~2FH, can be used as normal RAM or bit addressable memory. The bit address is 00H~7FH when used as bit addressable memory, which is defined by bit instead of Byte. 3) User RAM area and Stack RAM. After the SC91F8311 reset, the stack area 07H is selected by the Stack Pointer. Users can configure the initial



value during program initialization. The initial value is recommended to be set at the unit E0H ~ FFH unit.

High 128B RAM

（Indirect addresses）

00H

7FH

Internal 256B RAM Structure diagram

Low 128B RAM

（Direct and Indirect addresses）

FFH

80H

SFR

（Direct addresses）

FFH

80H

LOW 128B internal SRAM:



7F 7E 7D 7C 7B 7A 79 78 2FH

77 76 75 74 73 72 71 70 2EH

6F 6E 6D 6C 6B 6A 69 68 2DH

67 66 65 64 63 62 61 60 2CH

5F 5E 5D 5C 5B 5A 59 58 2BH

57 56 55 54 53 52 51 50 2AH

4F 4E 4D 4C 4B 4A 49 48 29H

47 46 45 44 43 42 41 40 28H

3F 3E 3D 3C 3B 3A 39 38 27H

37 36 35 34 33 32 31 30 26H

2F 2E 2D 2C 2B 2A 29 28 25H

27 26 25 24 23 22 21 20 24H

1F 1E 1D 1C 1B 1A 19 18 23H

17 16 15 14 13 12 11 10 22H

0F 0E 0D 0C 0B 0A 09 08 21H

07 06 05 04 03 02 01 00 20H

SRAM

BANK0

BANK1

BANK2

BANK3

Bit addressable RAM

Direct RAM

00H

07H08H

0FH10H

17H18H

1FH20H

2FH30H

7FH

Low 128B RAM

(Direct and Indirect addresses)

External 256B SRAM: The external 256B SRAM can be accessed by the traditional external RAM. User can use MOVX A, @Ri or

MOVX @Ri, A to access the external 256B RAM, or use MOVX A, @DPTR or MOVX @DPTR, A to access the external 256B RAM.



6 Special Function Registers (SFR) 6.1 SFR Table The SC91F8311 uses Special Function Registers (SFRs) to control and monitor peripherals and their Modes. The SFRs within the register address 80h~FFh are only accessable for by direct addressing. Some of the SFRs are bit addressable, which are those SFRs with addresses ended in 0 or 8. All SFRs can ONLY be addressed DIRECTLY.

The list of he SFRs is as follows.

0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F

F8h PWMCR PWMPRD PWMDTY1 PWMDTY0 PWMCFG - - -

F0h B - - - - - RSTCFG -

E8h - - IAPKEY IAPADH IAPADL IAPDAT IAPCTL -

E0h ACC - - - - - - -

D8h - - - - - - - -

D0h PSW - - - - - - -

C8h - WDTCR X32CTL - - - - -

C0h - - - - ADCCFG ADCCR ADCVH ADCVL

B8h IP - - - - - - -

B0h - - - - EXIE EXIP - -

A8h IE - - - - - - LCDVOS

A0h P2 P2CFG1 P2CFG0 P0LCDVO P1LCDVO P2LCDVO - -

98h SCON SBUF BAUDGL BAUDGH - - - -

90h P1 P1CFG1 P1CFG0 P1IT - - - -

88h TCON TMOD TL0 TL1 TH0 TH1 TMCON -

80h P0 SP DPL DPH - P0CFG0 - PCON

Bit

addressable Not bit addressable

note: 1.The blank SFR registers shows in the table means there is not such register, which is not recommended to use. 2.The “C3H”, “F7h”, “FEH” and “FFH” SFR are special function registers for system configuration. Using them may cause some abnormal. Clear or other types of operations to these 4 registers are forbidden during system initialization.

6.2 SFR Description

symbol address

description 7 6 5 4 3 2 1 0 reset value

P0 80H P0 data - - - - P0.3 P0.2 P0.1 P0.0 xxxx1111b

SP 81H Stack Pointer SP[7:0] 00000111b

DPL 82H DPTR Low DPL[7:0] 00000000b

DPH 83H DPTR High DPH[7:0] 00000000b

P0CFG0 85H P0 configuration0 P03M[1:0] P02M[1:0] P01M[1:0] P00M[1:0] 10101010b

PCON 87H Power control - - - - - - STOP - xxxxxx0xb

TCON 88H Timer control TF1 TR1 TF0 TR0 - - - - 0000xxxxb

TMOD 89H timer mode GATE1 C/T1 M11 M01 GATE0 C/T0 M10 M00 00000000b

TL0 8AH Timer 0 low TL0[7:0] 00000000b

TL1 8BH Time 1 low TL1[7:0] 00000000b

TH0 8CH Timer 0 high TH0[7:0] 00000000b

TH1 8DH Timer 1 high TH1[7:0] 00000000b

TMCON 8EH Timer CLK Selection - - - - - - T1FD T0FD xxxxxx00b

P1 90H P1 data - - P1.5 P1.4 P1.3 P1.2 P1.1 - xx11111xb



P1CFG1 91H P1 configuration1 - - P15M[1:0] P14M[1:0] xxxx1010b

P1CFG0 92H P1 configuration0 P13M[1:0] P12M[1:0] P11M[1:0] - 101010xxb

P1IT 93H INT1~3 interrupt edge type - - INT3ES[1:0] INT2ES[1:0] INT1ES[1:0] xx000000b

SCON 98H Serial port control register SM0 - SM2 REN TB8 RB8 TI RI 0x000000b

SBUF 99H Serial port data buffer register SBUF[7:0] 00000000b

BAUDGL 9AH Baud rate generator L register BAUDG[7:0] 00000000b

BAUDGH 9BH Baud rate generator H register ENBAUDG - BAUDG[13:8] 0x000100b

P2 A0H P2 data - P2.6 P2.5 P2.4 - - - P2.0 x111xxx1b

P2CFG1 A1H P2 Configuration - 1 - P26M[1:0] P25M[1:0] P24M[1:0] xx101010b

P2CFG0 A2H P2 Configuration - 0 - - - P20M[1:0] xxxxxx10b

P0LCDVO A3H P0 LCD voltage output register - - - - P03VO P02VO P01VO P00VO xxxx0000b

P1LCDVO A4H P1 LCD voltage output register - - P15VO P14VO P13VO P12VO P11VO - xx00000xb

P2LCDVO A5H P2 LCD voltage output register - P26VO P25VO P24VO - - - P20VO x000xxx0b

IE A8H Interrupt priority EA EADC EPWM EUART ET1 E32K ET0 ETK 00000000b

LCDVOS AFH LCD voltage output selection - - - - VOIRS[1:0] - VOS xxxx00x0b

EXIE B4H External INT enable - - - - EINT3 EINT2 EINT1 - xxxx000xb

EXIP B5H External INT priority - - - - IPEX3 IPEX2 IPEX1 - xxxx000xb

IP B8H Interrupt priority - IPADC IPPWM IPUART IPT1 IP32K- IPT0 IPTK x0000000b

ADCCFG C4H P1/P2 ADC Configuration P15AIN7 - - - P26AIN3 P25AIN2- P24AIN1 VREFS 0xxx000nb

ADCCR C5H ADC control

ADCEN ADCS LOWSP EOC/

ADCIF

- ADCIS[2:0] 0000x000b

ADCVH C6H ADC converter result ADCV[11:

4]

ADCV[11:4] xxxxxxxxb

ADCVL C7H ADC converter result ADCV[3: 0] ADCV[3:0] - - - - xxxxxxxxb

WDTCR C9H WDT control ENWDT - - CLRWDT - - WDTCKS[1:0] nxx0xx00b

X32CTL CAH 32k BaseTimer control CLKS ENX32 ENCNT X32IF - X32IFS[2:0] 0000x000b

PSW D0H PSW CY AC F0 RS1 RS0 OV - P 000000x0b

ACC E0H ACC ACC[7:0] 00000000b

IAPKEY EAH IAP protection IAPKEY[7:0] 00000000b

IAPADH EBH IAP address high 5 bit - - - IAPADR[12:8] xxx11111b

IAPADL ECH IAP address low 8 bit IAPADR[7:0] 11111111b

IAPDAT EDH IAP data IAPDAT[7:0] 11111111b

IAPCTL EEH IAP control - - - - PAYTIMES[1:0] CMD[1:0] xxxx0000b

B F0H B B[7:0] 00000000b

RSTCFG F6H Reset configuration

Set the LVR and the reset

function

- - DISRST DISLVR LVRS[3:0]

xxnnnnnnb

PWMCR F8H PWM control ENPWM PWMIF PWM1OS PWM0OS DTY18 ENPWM1O DTY08 ENPWM0O 00000000b

PWMPRD F9H PWM period PWMPRD[7:0] 11111111b

PWMDTY1 FAH PWM1 duty PWMDTY1[7:0] 00000000b

PWMDTY0 FBH PWM0 duty PWMDTY0[7:0] 00000000b

PWMCFG FCH PWM configuration - - INV1 INV0 - PWMCKS[2:0] xx00x000b

8051 CPU Core SFR: ACC, B, PSW, SP, DPL, DPH

1. ACC(E0h) ACC stands for Accumulator register. “A” is used as instruction Mnemonics.

2. B registers (F0h)

The B register is used during multiply and divide operations. For other instructions it can be treated as another scratch pad register.

3. SP (81H) The Stack Pointer Register is 8 bits wide. It is incremented before data is stored during PUSH, CALL

executions and it is decremented after data is out of stack during POP, RET, RETI executions. The stack may reside anywhere in on-chip internal RAM (00H-FFH). On reset, the Stack Pointer is initialized to 07H causing the stack to begin at 08H. 4. PSW (D0h) Program status words



bit No 7 6 5 4 3 2 1 0

SYMBOL CY AC F0 RS1 RS0 OV - P

Reset 0 0 0 0 0 0 x 0

Bit No Symbol Description

7 CY Carry flag: Set for an arithmetic operation which results in a carry being generated from the ALU. It is also used as the accumulator for the operations.

6 AC Auxiliary carry: Set when the previous operation resulted in a carry from the high order nibble.

5 F0 User flag 0: The General purpose flag that can be set or cleared by the user.

4~3 RS1、RS0 Register bank select bits:

RS1 RS0 Register Bank & Address

0 0 BANK 0 (00H~07H)

0 1 BANK 1 (08H~0FH)

1 0 BANK 2 (10H~17H)

1 1 BANK 3 (18H~1FH)

2 OV Overflow flag: Set when a carry was generated from the seventh bit but not from the 8th bit as a result of the previous operation, or vice-versa.

0 P Parity flag: Set/cleared by hardware to indicate odd/even number of “1” in the ACC.

1 reserved reserved

5. DPTR (82H、83H)

DPTR is the 16-bit data pointer of 8051.



7 Power, Reset & CLock 7.1 Power

The core power circuit of SC91F8311 contains BG, LDO, POR and LVD/LVR circuit, which can ensure the chipset to work stable at the voltage of 2.4~5.5V. SC91F8311 is also integrated with a precisely tuned 2.4V Voltage, which can also be used as ADC reference voltage. Detail configuration info can be found in the ADC session.

7.2 Power on reset SC91F8311 power-on reset process can be divided into the following stages:

Reset stage Loading information stage Normal operating stage

Reset stage The device will always be in reset mode unless the supplied voltage value is higher than a certain value,

and then CPU starts valid Clock. The Reset duration depends on the speed of the external power supply increasing. The reset process won’t complete until the external power supply reaches to a higher value than the optional value of the LVR voltage.

Loading information stage During Reset, user’s settings will be loaded subject to the SFR, in order to work properly.

Normal operating stage Finishing information loading, the device begins to read the instruction code from Flash and enter into the

normal operation stage. LVR voltage value is the value written to the Code Option.

7.3 Reset Mode The SC91F8311 has 4 reset modes: ① External Reset, ②Low Voltage Reset, ③Power on Reset, ④WDT

Reset.

7.3.1 Exernal Reset The SC91F8311 should be reset if user put the reset pulse into RST Pin from external. The RSTN/P1.1 is used for RST Pin as default. User can modify RSTN to P1.1 by writing the SFR

RSTCFG.

7.3.2 Low Voltage reset The SC91F8311 features a Low Voltage Reset (LVR) Circuit. The LVR voltage has four options, the default

value is written to MCU by programmer. RSTCFG (F6h) Reset Configuration Register (R/W)

Bit No 7 6 5 4 3 2 1 0

SYMBOL - - DISRST DISLVR LVRS[3: 0]

R/W - - R/W R/W R/W

Reset x x 0 n n n n n

Bit No SYMBOL Description

7~6 reserved reserved

5 DISRST IO/RST Control 0: P1.1 used as reset pin 1: P1.1 used as GPIO

4 DISLVR LVR enable 0: LVR ON 1: LVR Off

3~0 LVRS [3: 0] LVR Voltage selection 1011: 3.65V 1010: 3.50V 0110: 2.75V 0101: 2.60V



SC91F8311 Reset diagram is as follow:

SFR

2.60V

3.50V

POR

(Power-Up Reset)

RESET

WatchDogTimer

Overflow

SC91F8311 Reset

LVD

Code option

De-Bounce (~2uS)

RSTN

pinDe-Bounce

2.75V

3.65V

7.3.3 Power on reset The device will automatically be reset when the supply voltage exceeds the POR voltage.

7.3.4 WDT reset The SC91F8311 has a 16-bit WDT. The clock source is the internal 16MHz RC Oscillator. The diagram is shown as below:

16-bit CounterFosc

Fosc / 64

Fosc / 16

Fosc / 8

Fosc / 2

Overflow

WDTCR[1:0] (WDTCKS[1:0])

WDTCR[7] (ENWDT)

WDTCR[4] (CLRWDT)ClearUp

Reset

WDT diagram

WDTCR (C9h) WDT control (R/W)

Bit No 7 6 5 4 3 2 1 0

SYMBOL ENWDT - - CLRWDT - - WDTCKS[1: 0]

R/W R/W - - R/W - - R/W

Reset 0 x x 0 x x 0 0


7 ENWDT WDT Control 1: WDT ON 0: WDT OFF

4 CLRWDT Clear WDT (Write “1”) 1 : WDT Timer Reset



1,0 WDTCKS [1: 0] WDT clock Source Selection

WDTCKS.1 WDTCKS.0 WDT Clock WDT Overflow Time @16MHz

0 0 Fosc/64 262.144ms

0 1 Fosc/16 65.536ms

1 0 Fosc/8 32.768ms

1 1 Fosc/2 8.192ms

7.3.5 Reset Initial State When the device is in reset state, most registers will return to their initial state. WDT is turned off, and port

registers is set to FFh.The initial value of the program counter is 0000h, and initial value of the stack pointer SP is 07h. “Warm” reset such as WDT, LVR and software reset won’t affect the SRAM’s value which always maintains as the same value as the value before reset. The data saved in SRAM will lose when power drops below a certain value when RAM cannot store data.

The reset Value of SFR:

SFR name reset value SFR name reset value

ACC 00000000b P1IT xx000000b

B 00000000b SCON 0x000000b

PSW 000000x0b SBUF 00000000b

SP 00000111b BAUDGL 00000000b

DPL 00000000b BAUDGH 0x000100b

DPH 00000000b P0LCDVO xxxx0000b

PCON xxxxxx0xb P1LCDVO xx00000xb

IE 00000000b P2LCDVO x000xxx0b

IP x0000000b LCDVOS xxxx00x0b

P0 xxxx1111b ADCCFG 00000000b

P1 xx11111xb ADCCR 0000x000b

P2 x111xxx1b ADCVH xxxxxxxxb

P0CFG0 10101010b ADCVL xxxxxxxxb

P1CFG0 101010xxb WDTCR nxx0xx00b

P1CFG1 xxxx1010b X32CTL 0000x000b

P2CFG0 xxxxxx10b IAPKEY 00000000b

P2CFG1 xx101010b IAPADH xxx11111b

TCON 0000xxxxb IAPADL 11111111b

TMOD 00000000b IAPDAT 11111111b

TH0 00000000b IAPCTL xxxx0000b

TL0 00000000b RSTCFG xxnnnnnnb

TH1 00000000b PWMCR 00000000b

TL1 00000000b PWMPRD 11111111b

TMCON xxxxxx00b PWMDTY1 00000000b

EXIE xxxx000xb PWMDTY0 00000000b

EXIP xxxx000xb PWMCFG xx00x000b

7.4 Clock The SC91F8311 is integrated with an oscillation frquency adjustable high precision IRC as system clock,

which is precisely tuned to 16MHz @ 5V/25℃ by default as factory setting. User can change the system clock

frequency to 16M/8MHz with programmer. The above tuning process is to remove the affects on the precision from the deviation during chipset manufacturing. The IRC value will drift, which is subject to the operating temperature and the operating voltage. The deviation is less than ±1% at operating voltage (4.5V~5.5V) drift

and temperature (-20~85℃) drift.

7.5 32k Crystal and Base Timer The SC91F8311 is integrated an internal 32.768 kHz oscillation circuit. The Oscillator connects to a 17-

bit Base Timer inside, which can activate CPU from STOP mode and generate Interrupt. The Base Timer can



be used for timing accuracy, but won’t participate in system clock, so that the chipset can run real-time clock in STOP mode with very low power consumption. This oscillator will never work with system clock.

The diagram for the 32k Base Timer internal oscillator options is as follow:

32K Base Timer Diagram

Internal 32K IRC

Oscillation

source

selector

switch

Basetimer

CounterX32KIF

CLKS ENCNT

The relevant SFR register is as follow:

X32CTL (CAh) 32K BaseTimer Control Register (R/W)

Bit No 7 6 5 4 3 2 1 0

Symbol CLKS ENX32 ENCNT X32IF - X32IFS[2:0]

R/W R/W R/W R/W R/W - R/W

Reset 0 0 0 0 x 0 0 0


7 CLKS Base timer clock source selection 0: internal 32k IRC 1: reserved

6 ENX32 32k OSC Startup 0: 32kHz IRC disabled 1: 32kHz IRC enabled (only works when the USEX32 of IFB set to 1) Note: It may take about 10ms~25ms for the 32kHz Crystal Oscillator to start when the ENX32 set to 1. When the ENX32 set to 0, the internal Base Timer will be cleared to 0. So, the first Base Timer interrupt may slow down a bit. However, the following interrupts will be very accurate as long as the ENX32 fixed as 1.

5 ENCNT Enable 32k Base Timer Counter 0: Disable Counter 1: Enable Counter

4 X32IF 32k Base Timer interrupt Flag When CPU receives Base Timer interrupt, the flag will be removed by hardware automatically. User can also use software to clear the flag.

2~0 X32IFS[2:0] 32k Interrupt Frequency Selection

000：Every 15.625ms to produce a interrupt



011：Every 125ms to produce a interrupt

100：Every 0.625 seconds to produce a interrupt

101：Every 0. 5 seconds to produce a interrupt

110：Every 1 seconds to produce a interrupt

111：Every 2 seconds to produce a interrupt

Note: There will be ± 20% deviation on break time when using the



internal 32k RC oscillator.

3 reserved reserved

Note: The IE[2] and the X32CTL[6] (ENX32) must be set to 0 before changing the X32IFS[1:0];

otherwise it may cause crash.

7.6 STOP The SC91F8311 provides a special SFR PCON. CPU will enter STOP mode if user write “1” to PCON.1. In

STOP mode, MCU can be waked up by INT1~INT3 or external reset.

PCON (87h) Power control register (write only)

Bit No 7 6 5 4 3 2 1 0

SYMBOL - - - - - - STOP -

R/W - - - - - - write only -

Reset x x x x x x 0 x


1 STOP STOP mode control 0: operating mode 1: STOP mode, internal oscillator stop

8 Instruction Set 8.1 CPU

The SC91F8311 CPU is an ultra-fast 1T standard 8051 CORE; the instruction is fully compatible with the traditional 8051 microcontroller core.

8.2 Addressing Mode The SC91F8311 1T 8051 CPU instruction addressing modes: ① immediately addressing ② directly

addressing ③ indirect addressing ④ register addressing ⑤ relative addressing ⑥Indexed Addressing ⑦ bit

addressing.

8.3 Instruction Set Instruction set table

Op code Description Byte Cycle

Arithmetic operations ADD A, Rn Add register to accumulator 1 1

ADD A, direct Add direct byte to accumulator 2 2

ADD A, @Ri Add indirect RAM to accumulator 1 2

ADD A, #data Add immediate data to accumulator 2 2

ADDC A, Rn Add register to accumulator with carry flag 1 1

ADDC A, direct Add direct byte to A with carry flag 2 2

ADDC A, @Ri Add indirect RAM to A with carry flag 1 2

ADDC A, #data Add immediate data to A with carry flag 2 2

SUBB A, Rn Subtract register from A with borrow 1 1

SUBB A, direct Subtract direct byte from A with borrow 2 2

SUBB A, @Ri Subtract indirect RAM from A with borrow 1 2

SUBB A, #data Subtract immediate data from A with borrow 2 2

INC A Increment accumulator 1 1

INC Rn Increment register 1 2

INC direct Increment direct byte 2 3

INC @Ri Increment indirect RAM 1 3

DEC A Decrement accumulator 1 1

DEC Rn Decrement register 1 2

DEC direct Decrement direct byte 1 3

DEC @Ri Decrement indirect RAM 2 3

INC DPTR Increment data pointer 1 1

MUL AB Multiply A and B 1 2



DIV AB Divide A by B 1 6

DA A Decimal adjust accumulator 1 3

Logic Operations

ANL A, Rn AND register to accumulator 1 1

ANL A, direct AND direct byte to accumulator 2 2

ANL A, @Ri AND indirect RAM to accumulator 1 2

ANL A, #data AND immediate data to accumulator 2 2

ANL direct, A AND accumulator to direct byte 2 3

ANL direct, #data AND immediate data to direct byte 3 3

ORL A, Rn OR register to accumulator 1 1

ORL A, direct OR direct byte to accumulator 2 2

ORL A, @Ri OR indirect RAM to accumulator 1 2

ORL A, #data OR immediate data to accumulator 2 2

ORL direct, A OR accumulator to direct byte 2 3

ORL direct, #data OR immediate data to direct byte 3 3

XRL A, Rn Exclusive OR register to accumulator 1 1

XRL A, direct Exclusive OR direct byte to accumulator 2 2

XRL A, @Ri Exclusive OR indirect RAM to accumulator 1 2

XRL A, #data Exclusive OR immediate data to accumulator 2 2

XRL direct, A Exclusive OR accumulator to direct byte 2 3

XRL direct, #data Exclusive OR immediate data to direct byte 3 3

CLR A Clear accumulator 1 1

CPL A Complement accumulator 1 1

RL A Rotate accumulator left 1 1

RLC A Rotate accumulator left through carry 1 1

RR A Rotate accumulator right 1 1

RRC A Rotate accumulator right through carry 1 1

SWAP A Swap nibbles within the accumulator 1 1

Boolean Manipulation

CLR C Clear carry flag 1 1

CLR bit Clear direct bit 2 3

SETB C Set carry flag 1 1

SETB bit Set direct bit 2 3

CPL C Complement carry flag 1 1

CPL bit Complement direct bit 2 3

ANL C, bit AND direct bit to carry flag 2 2

ANL C,/bit AND complement of direct bit to carry 2 2

ORL C,bit OR direct bit to carry flag 2 2

ORL C,/bit OR complement of direct bit to carry 2 2

MOV C, bit Move direct bit to carry flag 2 2

MOV bit, C Move carry flag to direct bit 2 3

JC rel Jump if carry flag is set 2 3

JNC rel Jump if carry flag is not set 2 3

JB bit, rel Jump if direct bit is set 3 5

JNB bit, rel Jump if direct bit is not set 3 5

JBC bit, rel Jump if direct bit is set and clear bit 3 5

Data Transfers

MOV A, Rn Move register to accumulator 1 1

MOV A, direct Move direct byte to accumulator 2 2

MOV A, @Ri Move indirect RAM to accumulator 1 2

MOV A, #data Move immediate data to accumulator 2 2

MOV Rn, A Move accumulator to register 1 1

MOV Rn, direct Move direct byte to register 2 3

MOV Rn, #data Move immediate data to register 2 2

MOV direct, A Move accumulator to direct byte 2 2

MOV direct, Rn Move register to direct byte 2 2

MOV direct1,direct2 Move direct byte to direct byte 3 3

MOV direct, @Ri Move indirect RAM to direct byte 2 3

MOV direct, #data Move immediate data to direct byte 3 3

MOV @Ri, A Move accumulator to indirect RAM 1 2

MOV @Ri, direct Move direct byte to indirect RAM 2 3

MOV @Ri, #data Move immediate data to indirect RAM 2 2

MOV DPTR,#data16 Load data pointer with a 16-bit constant 3 3



MOVC A,@A+DPTR Move code byte relative to DPTR to A 1 5

MOVC A,@A+PC Move code byte relative to PC to A 1 4

MOVX A,@Ri Move external RAM (8-bit address) to A 1 3

MOVX @Ri,A Move external RAM (16-bit address) to A 1 4

MOVX A,@DPTR Move A to external RAM (8-bit address) 1 2

MOVX @DPTR,A Move A to external RAM (16-bit address) 1 3

PUSH direct Push direct byte onto stack 2 3

POP direct Pop direct byte from stack 2 2

XCH A, Rn Exchange register with accumulator 1 2

XCH A, direct Exchange direct byte with accumulator 2 3

XCH A, @Ri Exchange indirect RAM with accumulator 1 3

XCHD A, @Ri Exchange low-order nibble indirect RAM with A 1 3

Program Branches

ACALL address11 Absolute subroutine call 2 4

LCALL address16 Long subroutine call 3 4

RET Return from subroutine 1 4

RETI Return from interrupt 1 4

AJMP address11 Absolute jump 2 3

LJMP address16 Long jump 3 4

SJMP rel Short jump (relative address) 2 3

JMP @A+DPTR Jump indirect relative to the DPTR 1 5

JZ rel Jump if accumulator is zero 2 4

JNZ rel Jump if accumulator is not zero 2 4

CJNE A, direct, rel Compare direct byte to A and jump if not equal 3 5

CJNE A, #data, rel Compare immediate to A and jump if not equal 3 4

CJNE Rn, #data, rel Compare immediate to reg. and jump if not equal 3 4

CJNE @Ri, #data, rel Compare immediate to Ri and jump if not equal 3 5

DJNZ Rn, rel Decrement register and jump if not zero 2 4

DJNZ direct, rel Decrement direct byte and jump if not zero 3 5

NOP No operation 1 1

MOVC instruction in SC91F8311 prohibit addressing ROM addressed 0000~00FFH.

9 Interrupt The SC91F8311 provides total 10 interrupt sources: Timer0, Timer1, PWM, ADC, UART, TK, X32K, INT1,

INT2, INT3. Each interrupt source can be individually enable and disable by setting or clearing the corresponding bit in the register IE & EXIE. The IE register also contains global interrupt enable bit, EA, which can enable/disable all the interrupts at once. Each interrupt has its own interrupt flag, interrupt vector, interrupt enable bit and interrupt priority.

9.1 Interrupt Source & Vector The following table shows the SC91F8311 interrupt source, interrupt vector, and the relevant control list:

Interrupt source

Interrupt timing

Interrupt flag

Enable bit

Interrupt priority

vector address

Polling priority

Interrupt No

(C51)

Clearing flag

Wake up STOP

TK Touch Key complete

TKSTA[0] TKIF

IE[0] (ETK)

IP[0] 0003H 1(high) 0 H/W Auto No

Timer0 Timer0

overflow TCON[5]

(TF0) IE[1] (ET0)

IP[1] 000BH 2 1 H/W Auto No

X32K

32k Base Timer

overflow

X32CTL[4] (X32IF)

IE[2] (E32K)

IP[2] 0013H 3 2 H/W Auto Yes

Timer1 Timer1

overflow

TCON[7] (TF1)

IE[3] (ET1)

IP[3] 001BH 4 3 H/W Auto No

UART

Transfer/ Receive

complete

SCON[1:0] (TI/RI)

IE[4] IP[4] 0023H 5 4 User

Software No

PWM PWM

overflow PWMCR[7] (PWMIF)

IE[5] (EPWM)

IP[5] 002BH 6 5 User

Software No

ADC ADC

complete ADCCR[4]

(EOC/ADCIF) IE[6]

(EADC) IP[6] 0033H 7 6

User Software

No



INT1 N-edge P-edge

Double edge Hidden EXIE[1] EXIP[1] 0043H 8 8 H/W Auto Yes

INT2 N-edge P-edge

Double edge Hidden EXIE[2] EXIP[2] 004BH 9 9 H/W Auto Yes

INT3 N-edge P-edge

Double edge Hidden EXIE[3] EXIP[3] 0053H 10(low) 10 H/W Auto Yes

In EA=1 and IE [1], the separate interrupt state is as below: The Timer0/1 interrupt occurs when they overflow. The flag (TF0 and TF1) is set to 1, which will be be

cleared by hardware automatically. The PWM interrupt occurs when PWM counter overflows (the number for the counter is over PWMPRD).

The flag PWMIF is set to 1, which must be cleared by user with software. The X32K interrupt occurs when the customized 32k base timer overflows. The flag X32IF is set to 1,

which will be cleared by hardware automatically. The ADC interrupt occurs after ADC conversion completes. The flag is EOC/ADCIF (ADCCR.4). The

EOC will be cleared to 0 by hardware when ADCS starts. When ADCS completes, the EOC will be set to 1 by hardware, which must be cleared by user with software. External INTx(x=1~3): External interrupt INT1~3 have separate interrupt vectors. When the external interrupt port interrupt condition occurs, the external interrupt occurred. Three external interrupt flag is hidden, hardware will automatically clear and does not require user to clear. External INT1~INT3 default for negative edge triggered external interrupt, if the user need double-edge or positive edge triggered interrupt, can be achieved by setting SFRs (P1IT). Users can set the priority of each interrupt by SFR registers EXIP. INT1~3 also can wake up the STOP of the SC91F8311.



9.2 Interrupt Diagram Interrupt diagram:

IE[7] (EA)

Interrupt to 0Bh IE[1] (ET0)

TCON[5] (TF0)

IE[7] (EA)

Interrupt to 1Bh IE[3] (ET1)

TCON[7] (TF1)

IE[7] (EA)

Interrupt to 23h

IE[5] (EPWMI)

PWMCR[6] (PWMIF)

IE[7] (EA)

Interrupt to 33h IE[6] (EADC)

ADCCR[6] (EOC)

Timer-0

Timer-1

UART

ADC

SC91F8311 INT structure

IE[7] (EA)

Interrupt to 43h EXIE[1] (EX1I)

Hidden FLAG (INT1IF)

IE[7] (EA)

Interrupt to 4Bh EXIE[2] (EX2I)


IE[7] (EA)

Interrupt to 53h EXIE[3] (EX3I)


Int-1

Int-2

Int-3

IE[7] (EA)

Interrupt to 13h IE[2] (E32K)

X32CTL[4](X32IF)

X32K

IE[7] (EA)

Interrupt to 2Bh

IE[4] (EUART)

SCON[1:0] (TI/RI)

PWM

IE[7] (EA)

Interrupt to 03h IE[0](ETKSI)

TKSSTA[0] (TKSIF)

TK

9.3 Interrupt Priority There are two interrupt levels for the SC91F8311. These interrupt source requests can be individually

programmed either as the high priority interrupt or the lower priority interrupt, so that the nesting for two-level interrupts can be achieved. The interrupt with lower priority can be interrupted by the interrupt request from the interrupt with high priority. However, it won’t be interrupted by another interrupt request from the interrupt with the same priority, and will remain executing until finish. And it won’t respond to a new interrupt request until it returns to main program by receiving a return instruction RETI and executes another instruction.

The sequence for interrupt inquery is the same as the C51 inquery number sequence from small to large, which means the interrupt with smaller inquery number will be responded with higher priority.

9.4 Interrupt Handling When an interrupt occurs, the main program is interrupted. CPU will perform the following operation: ① complete the instruction being executed; ② Push on the PC to stack; ③ Long Call to the interrupt vector;



④ executing the corresponding interrupt service routine; ⑤ complete the interrupt service routine and RETI; ⑥ POP the PC from stack, and return the program before the interrupt. In this process, the system does not immediately interrupt the other with the same priority, but the flag will

be retained. System will perform the retained interrupt request after completing the interrupt handling in the current.

9.5 SFR Registers for Interrupt IE (A8h) intterupt enable register (R/W)

Bit No 7 6 5 4 3 2 1 0

Symbol EA EADC EPWM EUART ET1 E32K ET0 ETK

R/W R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0


7 EA All interrupt enable bit 0: Disable all interrupt 1: Enable all interrupt

6 EADC ADC interrupt enable bit 0: Disable ADC interrupt 1: Enable ADC interrupt

5 EPWM PWM interrupt enable bit 0: Disable PWM interrupt 1: Enable PWM interrupt

4 EUART UART interrupt enable bit 0: Disable UART interrupt 1: Enable UART interrupt

3 ET1 Timer1 interrupt enable bit 0: Disable timer1 interrupt 1: Enable timer1 interrupt

2 E32K 32k Base Timer interrupt enable bit 0: Disable 32k interrupt 1: Enable 32k interrupt

1 ET0 Timer0 interrupt enable bit 0: Disable timer0 interrupt 1: Enable timer0 interrupt

0 ETK Touck key interrupt enable bit 0: Disable Touch key interrupt 1: Enable Touch key interrupt

IP (B8h) interrupt priority (R/W)

Bit No 7 6 5 4 3 2 1 0

Symbol - IPADC IPPWM IPUART IPT1 IP32K IPT0 IPTK

R/W - R/W R/W R/W R/W R/W R/W R/W

Reset x 0 0 0 0 0 0 0


6 IPADC ADC interrupt priority 0: ADC low priority 1: ADC high priority

5 IPPWM PWM interrupt priority 0: PWM low priority 1: PWM high priority

4 IPUART UART interrupt priority 0: UART low priority 1: UART high priority

3 IPT1 Timer1 interrupt priority



0: Timer1 low priority 1: Timer1 high priority

2 IP32K 32k Base Timer interrupt priority 0: 32k low priority 1: 32k high priority

1 IPT0 Timer0 interrupt priority 0: Timer0 low priority 1: Timer0 high priority

0 IPTK Touch key interrupt priority 0: Touch key low priority 1: Touch key priority

7 reserved reserved

EXIE (B4h) External interrupt enable (R/W)

Bit No 7 6 5 4 3 2 1 0

Symbol - - - - EINT3 EINT2 EINT1 -

R/W - - - - R/W R/W R/W -

Reset x x x x 0 0 0 x


3~1 EINTx (x=1~3)

External interrupt enable 0: disable INTx(x=1~3) 1: enable INTx(x=1~3)

7~4,0 reserved reserved

EXIP (B5h) External interrupt priority (R/W)

Bit No 7 6 5 4 3 2 1 0

Symbol - - - - IPEX3 IPEX2 IPEX1 -

R/W - - - - R/W R/W R/W -

Reset x x x x 0 0 0 x


3~1 IPEXn (n=1~3)

EXT INT priority selection 0: INTn(n=1~3) priority low 1: INTn(n=1~3) priority high

7~4,0 reserved reserved

P1IT (93h) INT1~3 edge type (R/W)

Bit No 7 6 5 4 3 2 1 0

Symbol - - INT3ES[1: 0] INT2ES[1: 0] INT1ES[1: 0]

R/W - - R/W R/W R/W R/W R/W R/W

Reset x x 0 0 0 0 0 0


5~0 INTnES[1: 0] INTn (n=1,2,3) Edge Selction 00: N-edge 01: reserved 10: double edge 11: P-edge


10 Timer0/Timer1 The SC91F8311 has two 16-bit Timer/Counter, called as T0 and T1, which can be configured as timer or

counter by the control bit “C/Tx” in the “TMOD” SFR. They are actually up counters with different counting sources. The counting source for Timer comes from system clock or the clock’s frequency, while the counting source for Counter is the input pulse from external pin. GATEx and TRx are the counting switch for T0 and T1 in Timer/Counter mode. Only when GATEx=0 and TRx=1 at the same time, T0 and T1 will start to count.



In the Counter mode, every input pulse from P2.0/T0 will add 1 to the value of T0. In the Timer mode, the counting source for T0 and T1 can be selected as Fosc/12 or Fosc/4 by TMCON

SFR. T0 has 4 operating modes, while T1 has 3 operating modes only (without Mode 3):

① Mode 0: 13-bit up Timer/Counter

② Mode 1: 16-bit up Timer/Counter

③ Mode 2: Auto-reload up 8-bit Timer/Counter

④ Mode 3: Two 8-bit up Timer/Counters

10.1 Timer SFR

Symbol Addres

s Description 7 6 5 4 3 2 1 0 Reset

TCON 88H Timer control TF1 TR1 TF0 TR0 - - - - 0000xxxxb

TMOD 89H Timer Mode GATE1 C/T1 M11 M01 GATE0 C/T0 M10 M00 00000000b

TL0 8AH Timer0 Low 00000000b

TL1 8BH Timer1 Low 00000000b

TH0 8CH Timer0 high 00000000b

TH1 8DH Timer1 high 00000000b

TMCON 8EH Timer clock selection - - - - - - T1FD T0FD xxxxxx00b

TCON (88h) Timer Control Register (R/W)

Bit No 7 6 5 4 3 2 1 0

Symbol TF1 TR1 TF0 TR0 - - - -

R/W R/W R/W R/W R/W - - - -

Reset 0 0 0 0 x x x x


7 TF1 Timer1 overflow flag. 0: Timer1 no overflow, can be cleared by software 1: Timer1 overflow, set by hardware;

6 TR1 Timer1 start/stop Control bits 0: Stop timer1 1: Start timer1

5 TF0 Timer0 overflow flag. 0: Timer0 no overflow, can be cleared by software 1: Timer0 overflow, set by hardware;

4 TR0 Timer0 start/stop Control bits 0: Stop timer0 1: Start timer0


TMOD (89h) Timer Mode Control Register (R/W)

Bit No 7 6 5 4 3 2 1 0

Symbol GATE1 C/T1 M11 M01 GATE0 C/T0 M10 M00


Reset 0 0 0 0 0 0 0 0

T1 T0


7 GATE1 Timer1 Gate control bits 0: Timer1 is enabled whenever TR1 control bit is set 1: Timer1 is disable

6 C/T1 Timer1 Timer/Counter mode selected bits



0: Timer Mode, Timer CLK source is from system CLK 1: Reserved

5,4 M11,M01 Timer1 Mode Selected bits 00: Mode0, 13bit up timer/Counter, bit7~5 of TL1 is ignored 01: Mode1, 16bit up Timer/Counter 10: Mode2, 8bit auto-reload up Timer/Counter 11: Reserved

3 GATE0 Timer0 Gate control bits 0: Timer0 is enabled whenever TR0 control bit is set 1: Timer0 is disable

2 C/T0 Timer0 Timer/Counter mode selected bits 0: Timer Mode, Timer CLK source is from system CLK 1: Counter Mode, Counter CLK source is from external pin P2.0

1,0 M10,M00 Timer0 Mode Selected bits 00: Mode0, 13bit up timer/Counter, bit7~5 of TL1 is ignored 01: Mode1, 16bit up Timer/Counter 10: Mode2, 8bit auto-reload up Timer/Counter 11: Mode3, two 8 bit up timer

T0 operating mode is set by TMOD[0]~TMOD[3] in TMOD registers. T1 operating mode is set by

TMOD[4]~TMOD[7]. Tx function for Timer/Counter is configured by the control bit “C/Tx” from TMOD SFR. M0x and M1x are

used to configure Tx operating mode. T0 and T1 will only start when GATEx=0 and TRx=1 at the same time.

TMCON (8Eh) Timer Clock Selection Register (R/W)

Bit No 7 6 5 4 3 2 1 0

Symbol - - - - - - T1FD T0FD

R/W - - - - - - R/W R/W

Reset x x x x x x 0 0


1 T1FD Timer1 Clock source selected bit 0: Timer1 clock source is from Fosc/12 1: Timer1 clock source is from Fosc/4

0 T0FD Timer0 Clock source selected bit 0: Timer0 clock source is from Fosc/12 1: Timer0 clock source is from Fosc/4


IE (A8h) Interrupt enable control Register (R/W)

Bit No 7 6 5 4 3 2 1 0



Reset 0 0 0 0 0 0 0 0


3 ET1 Timer1interrupt enable control 0: Disable Timer1 interrupt 1: Enable Timer1 interrupt

1 ET0 Timer0 interrupt enable control 0: Disable Timer0 interrupt 1: Enable Timer0 interrupt

IP (B8h) Interrupt Priority Register (R/W)

Bit No 7 6 5 4 3 2 1 0



Reset x 0 0 0 0 0 0 0




3 IPT1 Timer1interrupt priority 0: Timer 1 interrupt priority low 1: Timer 1 interrupt priority high

1 IPT0 Timer0 interrupt priority 0: Timer0 interrupt priority low 1: Timer0 interrupt priority high

10.2 Timer0 Mode T0 can work in 4 different modes by setting M10, M00 (TMOD[1], TMOD[0]) in TMOD. Mode 0: 13-bit Timer/Counter Timer0 operate as 13-bit timer/counters in mode0. The TH0 register holds the high 8bits of the 13-bit

timer/counter, TL0 holds the 5 low bits TL0.4~TL0.0. The three upper bits(TL0.7~TL0.5) of TL0 are indeterminate and should be ignored when reading. As the 13-bit timer register increments and overflow, the timer0 overflow flag is set and an interrupt will occur if Timer0 interrupt is enabled.

The CT0 bit selects the timer/counter’s clock source. If CT0=1, high-to-low transitions at the Timer input pin(T0) will increase the timer/counter Data register. Else if CT0=0, selects the system clock to increase the timer/counter Data register. Setting the TR0 bit anables the timer when GATE0=0.

1/4 system clock or 1/12 system clock can be selected as Timer0 clock source by configuring T0FD bit in TMCON register.

Mode 0: 13-bit up Timer/Counter

T0=P2.0

Fosc/12 T0FD=0

/4 T0FD=1 TMOD.2=0

TMOD.2=1

TL0

5 bit

TH0

8 bit

TCON.4

TMOD.3

TCON.5

T0 interrupt

Request

(C/T0)

(C/T0)

(GATE0)

(TR0)

(TF0)

Mode1: 16-bit Timer/Counter Mode1 operation is the same as Mode 0, except that the Timer/Counter register use all 16 bits. The

Timer/Counter are enabled and configured in Mode1 in the same manner as for Mode 0.



Fosc/12 T0FD=0

/4 T0FD=1 TMOD.2=0

TMOD.2=1

TL0

8 bit

TH0

8 bit

TCON.4

TMOD.3

TCON.5

Mode 1: 16-bit up Timer/Counter

T0 interrupt

Request

T0=P2.0

(C/T0)

(C/T0)

(GATE0)

(TR0)

(TF0)

Mode 2: 8-bit auto-reload Timer/Counter Mode 2 configures timer0 to operate as 8-bit timer/counters with automatic reload of the start value. TL0

holds the count and TH0 holds the reload value. When the counter in TL0 overflows from 0xFF to TH0, the timer overflow flag TF0 is set and the counter in TL0 is reloaded from TH0. If Timer0 interrupt are enabled, an interrupt will occur when the TF0 flag is set. The reload value in TH0 is not changed. TL0 must be initialized to the desired value before enabling the timer for the first count to be correct.

Except the Auto-reload function, both timer/counters are enable and configures in Mode2 is the same as in Mode 0 & Mode 1.

As timer, the frequency proportion from the timer clock souce divided by system clock Fosc can be configured by setting TMCON.0 (T0FD) register.

Fosc/12 T0FD=0

/4 T0FD=1 TMOD.2=0

TMOD.2=1

TCON.4

TMOD.3

Mode 2: Auto-Reload 8-bit up Timer/Counter

T0=P2.0

(C/T0)

(C/T0)

(GATE0)

(TR0)

TL0

8 bit

TH0

8 bit

TCON.5

T0 interrupt

Request

Set

(TF0)

Mode 3: Two 8-bit Timer/Counters (Timer0 only) In Mode 3, Timer0 is configured as two separate 8-bit timer/counters held in TL0 and TH0. TL0 is

controlled using the timer0 control/status bits in TCON and TMOD: TR0, CT0, GATE0 and TF0. TL0 can use either the system clock or an external input signal as it’s time base.

The TH0 is restricted to a timer function sourced by the system clock. TH0 is enabled using the Timer1 control bit TR1. TH0 sets the timer1 overflow flag TF1 on overflow and thus controls the timer 1 interrupt.

In Mode 3, TH0 timer occupies the interrupt resource of T1 timer and the TCON register as well. The 16-bit T1 counter will stops counting, ie. "TR1=0". Using TH0 as timer, TR1 should be set to 1.



Fosc

T0=P2.0

/12 T0FD=0

/4 T0FD=1 TMOD.2=0

TMOD.2=1

TL0

8 bit

TCON.4

TMOD.3

TCON.5

Mode 3： two 8bit Timer/Counters

T0 interrupt

request

TH0

8 bitTCON.7

T1 interrupt

requestTCON.6

(C/T0)

(C/T0)

(TR1)

(TR0)

(GATE0)

(TF0)

(TF1)

10.3 Timer1 Mode T1 can work in 3 different modes by setting M11, M01 (TMOD[5], TMOD[4]) in TMOD. Mode 0: 13-bit Timer/Counter Timer1 operate as 13-bit timer/counters in mode0. The TH1 register holds the high 8bits of the 13-bit

timer/counter, TL1 holds the 5 low bits TL1.4~TL1.0. The three upper bits(TL1.7~TL1.5) of TL1 are indeterminate and should be ignored when reading. As the 13-bit timer register increments and overflow, the timer1 overflow flag is set and an interrupt will occur if Timer1 interrupt is enabled.

The CT1 bit selects the timer/counter’s clock source. if CT1=0, selects the system clock to increase the timer/counter Data register.

Setting the TR1 bit enables the timer when GATE1=0. Setting TR1 to 1 will not force timer to reset, which means, if TR1 is set to 1, the timer register will start counting from the last value when TR1 is cleared to 0. Therefore, the initial value for the timer register should be configured before enabling timer.

1/4 system clock or 1/12 system clock can be selected as Timer0 clock source by configuring T1FD bit in TMCON register.

Fosc/12 T1FD=0

/4 T1FD=1 TMOD.6=0

TL1

5 bit

TH1

8 bit

TCON.6

TMOD.7

TCON.7

Mode 0:13-bit up Timer/Counter

T1 interrupt

Request

(C/T1)

(GATE1)

(TR1)

(TF1)

Mode1: 16-bit Timer/Counter Mode1 operation is the same as Mode 0, except that the Timer/Counter register use all 16 bits. The

Timer/Counter are enabled and configured in Mode1 in the same manner as for Mode 0.



Fosc/12 T1FD=0

/4 T1FD=1 TMOD.6=0

TL1

8 bit

TH1

8 bit

TCON.6

TMOD.7

TCON.7

Mode 1:16-bit up Timer/Counter

T1 interrupt

Request

(C/T1)

(GATE1)

(TR1)

(TF1)

Mode 2: 8-bit auto-reload Timer/Counter Mode 2 configures timer1 to operate as 8-bit timer/counters with automatic reload of the start value. TL1

holds the count and TH1 holds the reload value. When the counter in TL1 overflows from 0xFF to TH1, the timer overflow flag TF1 is set and the counter in TL1 is reloaded from TH1. If Timer1 interrupt are enabled, an interrupt will occur when the TF1 flag is set. The reload value in TH1 is not changed. TL1 must be initialized to the desired value before enabling the timer for the first count to be correct.

Except the Auto-reload function, both timer/counters are enable and configures in Mode2 is the same as in Mode 0 & Mode 1.

As timer, the frequency proportion from the timer clock souce divided by system clock Fosc can be configured by setting TMCON.4 (T1FD) register.

Fosc/12 T1FD=0

/4 T1FD=1 TMOD.6=0

TCON.6

TMOD.7

Mode 2：8-bit Auto-reload up Timer/Counter

(C/T1)

(GATE1)

(TR1)

TL1

8 bit

TH1

8 bit

TCON.7

T1 interrupt

Request

Set

(TF1)

11 PWM The SC91F8311 provides a separate counter, it can support two PWM outputs: PWM0 and PWM1. PWM Features: ① 8-bit PWM Modules ② PWM0 and PWM1 have the same period, but the duty cycle can be independently set ③ Selectable output polarity

④ Provide interrupt function on period overflow ⑤ PWM0 output can switch to 2 different IO port

Note: Switching output from GPIO to PWM, GPIO will not automatically switch to the strong push-pull for

PWM. Instead it will keep the previous setting. If strong push-pull PWM needed, user has to set GPIO to the strong push-pull mode before switching.



The PWM Modules can provide the pulse width modulation waveform with the period and the duty being controlled individually. The PWMCR register controls the relevant setting for PWM0 and PWM1. The PWMCFG register controls the counter clock source for PWM counter and the output level as well. The PWMPRD register controls the period cycle of the PWM0 and PWM1. The PWMDTY0 and the PWMDTY1 register controls the duty in the waveform of the PWM0 and PWM1 separately.

11.1 PWM Diagram

PWMDTY0

Buffer

Comparator

PWMDTY1

Buffer

Comparator

PWMPRD

Buffer

Comparator

Counter

Reload

PWMIF

/1

/2

.

.

.

/256

CKSFosc

ENPWM

Period Module

PWM0 PWM1

Q R

S

R Q

S

INV0

DTY08 DTY18

SC91F8311 PWM Modules

PWM1OS

P0.1P0.0

INV1

ENPWM1OENPWM0O

P1.4

PWM0OS

Reload

Reload



11.2 PWM SFR PWMCR (F8h)PWM Control Register (R/W)

Bit No 7 6 5 4 3 2 1 0

Symbol ENPWM PWMIF PWM1OS

PWM0OS DTY18 ENPWM1O DTY08 ENPWM0O


Reset 0 0 0 0 0 0 0 0


7 ENPWM PWM Module Enable 1: PWM Module ON 0: PWM Module Off

6 PWMIF PWM Interrupt Flag 0: PWM period counter not overflow 1: Set by hardware to indicate that the PWM period counter overflow, must be cleared by software

5 PWM1OS PWM1 output selection 0: Reserved 1: PWM1 to P0.1

4 PWM0OS PWM0 output selection 0: PWM0 to P1.4 1: PWM0 to P0.0

3 DTY18 Force PWM1 as HIGH 1: PWM1 output always high 0: PWM1 output is controlled by PWMPRD and PWMDTY1

2 ENPWM1O PWM1 output enable 1: enable PWM1 output to P0.1 0: PWM1 output disable

1 DTY08 Force PWM0 as HIGH 1: PWM0 output always high 0: PWM0 output is controlled by PWMPRD and PWMDTY0

0 ENPWM0O PWM0 output enable 1: enable PWM0 output to P1.4/P0.0 0: PWM0 output disable

SFR PWMPRD[7:0] is the controller to set the shared cycle for 2-channel PWM. Reaching to the preset

value of the PWMPRD[7:0], the PWM counter will hop to 00h when next PWM CLK comes, which means the cycle of PWM1 and PWM0 is (PWMPRD[7:0] + 1) *PWM clock.

PWMPRD (F9h) PWM period control Register (R/W)

Bit No 7 6 5 4 3 2 1 0

Symbol PWMPRD[7: 0]


Reset 0 0 0 0 0 0 0 0


7~0 PWMPRD[7: 0] PWM output period cycle=(PWMPRD[7: 0]+1)*PWM CLK

The counting time for PWM counter can be controlled by PWMCFG[2:0] to choose pre-scalar selector,

which means to configure the frequency proportion from the PWM counter clock souce divided by system clock Fosc. PWM1 and PWM0 can also be selected by INV1 and INV0 in PWMCFG[5:4] to define PWM output inverse or not.

PWMCFG (FCh) PWM configuration Register (R/W)

Bit No 7 6 5 4 3 2 1 0

Symbol - - INV1 INV0 - CKS[2: 0]

R/W - - R/W R/W - R/W



Reset x x 0 0 x 0 0 0


5 INV1 INVerse PWM1 Output 1: Inverse the PWM1 output 0: Don’t Inverse the PWM1 output

4 INV0 INVerse PWM0 Output 1: Inverse the PWM0 output 0: Don’t Inverse the PWM0 output

2~0 CKS[2: 0] PWM Clock Source Selection 000: Fosc 001: Fosc/2 010: Fosc/4 011: Fosc/8 100: Fosc/32 101: Fosc/64 110: Fosc/128 111: Fosc/256

7,6,3 reserved reserved

PWMDTY1 (FAh) PWM1 Duty Control Register (R/W)

Bit No 7 6 5 4 3 2 1 0

Symbol PWMDTY1[7: 0]


Reset 0 0 0 0 0 0 0 0


7~0 PWMDTY1[7: 0] PWM1 Duty = (PWMDTY1[7: 0])* PWM CLK

PWMDTY0 (FBh) PWM0 Duty Control Register (R/W)

Bit No 7 6 5 4 3 2 1 0

Symbol PWMDTY0[7: 0]


Reset 0 0 0 0 0 0 0 0


7~0 PWMDTY0[7: 0] PWM0 Duty = (PWMDTY0[7: 0])* PWM CLK

IE (A8h) Interrupt enable control Register (R/W)

Bit No 7 6 5 4 3 2 1 0



Reset 0 0 0 0 0 0 0 0


5 EPWM PWM interrupt enable 0: Disable PWM interrupt 1: Enable PWM interrupt

IP (B8h) Interrupt Priority Register (R/W)

Bit No 7 6 5 4 3 2 1 0



Reset x 0 0 0 0 0 0 0


5 IPPWM PWM interrupt priority



0: PWM interrupt priority is Low 1: PWM interrupt priority is High

Note: 1. ENPWM bit is used to Enable/Disable the PWM Modules. 2. ENPWMxO bits are used to selecting the PWM output share with GPIO. 3. EPWM (IE.5) bit is used to enable/disable PWM interrupt. 4. PWM interrupt can be used as an 8-bit timer if you don’t use it as PWM. 5. It is the same interrupt Vector for PWM0 and PWM1 interrupt.

11.3 PWM Waveform and Application The SFR parameter affects the PWM waveform as follows:

①DTYX8

period1

DTYX8

DTYX8=1

DTYX8=0

PWMX

Output

period2 period3 period4 period5 period6

DTYX8 and PWM output

When the PWMx is outputting waveform, if DTYx8 (PWMCR.1 / PWMCR.3) change, PWMx waveform will change immediately.

②CHANGE DUTY

Change Duty

Change step

PWM：

Initial Value：PWMDTYX=n

(PWMPRD=t)

Step1：PWMDTYX=m

Step2：PWMDTYX=k

PWM

Period：

n n n m m m k k k

t+1 t+1 t+1 t+1 t+1 t+1 t+1 t+1 t+1

Step1 Step2

When the PWMx is outputting waveform, user can change the duty by changing the PWMDTYx register.

However, the duty cycle will not change immediately until the next PWM cycle.

③CHANGE PERIOD



Change Period

Initial Value：PWMDTYX=h

(PWMPRD=n)

step1：set PWMPRD=m

step2：set PWMPRD=kStep

PWM：

PWM

Period：n+1 n+1 m+1n+1 m+1 m+1 k+1 k+1 k+1

Step1 Step2

h h h h h h h h h

When the PWMx is outputting waveform, user can change the period by changing the PWMPRD register.

However, the period cycle will not change immediately until the next PWM cycle.

④REALTIONSHIP BETWEEN PERIODS WITH DUTY

PWMDTYX=00H

PWMDTYX=01H

PWMDTYX=PWMPRD

PWMDTYX≥PWMPRD+1

Low

High

Low

High

Low

High

Period=PWMPRD+1

1 2 3... Period

PWMDTYX=02H

PWM CLK

High

Low

Period & Duty

When INVx=0, you can get the waveform of PWM as shown above. The waveform of PWMx will change

immediately if you change the INVx bit.

11.4 THE IMPLEMENTATION FOR TWO COMPLEMENTARY PWM WITH DEAD ZONE

High power motor or the backend of frequency transformer is managed by H-bridge which is composed by high-power tubes, IGBT and other components. Upper half and lower half-bridge could not be turned on at the same time. However, there are some junction capacitances within the power components (such as IGBT), which might cause the delay when turning on/off of the devices, so that in some cases, power components might be demaged since some certain half-bridge components is not shut down as expected.

In order to ensure H bridge or the upper/lower half pipe of half H bridge will not be turned on at the same time due to the switching speed problem, a time interval is needed when toggled, which is called PWM output DEAD ZONE.



SC91F8311 can output complementary PWM waveform with dead zone by two independent PWM0 and

PWM1. The following example is to demonstrating how to implement. Assuming we need to output two 200kHz

frequency with 50% duty cycle complementary PWM square waves, and we also need to produce a dead zone no less than 5nS. The other conditions are, 16MHz operating frequency, VDD is 5v, VIH for peripheral M is 0.7VDD, VIL is 0.3VDD.

PWM1

PWM0

R=100Ω

C=330pF

PWM1_IN

PWM0_IN

Add RC delay circuit to PWM0 output port

GND

M

SC91F8311

① Output two complementary PWM square waves at 200kHz with 1:2 duty cycle:

void PWMinit (void) { PWMCFG = 0x20; // PWM0 output to P0.0, PWM1 inverted output to P0.1

// Select the PWM clock source is fosc = 16MHz PWMPRD = 79; // PWM period T = (79 + 1) * (1 / 16M) = 5us, 200kHz PWMDTY0 = 40; // PWM0 Duty is set to 1: 2 PWMDTY1 = 40; // PWM1 Duty is set to 1: 2 PWMCR = 0xB5; // Open the PWM power supply, enable PWM1 and PWM0 output }

PWM0 and PWM1 output waveform

Period T=5us

PWM0

PWM1

②Modify PWMDTY0 to adjust PWM0 Duty, in order to produce the back dead zone delay t1



PWMDTY0 = 39; // PWM0 Duty set to 39:80 to produce the back dead zone delay

PWM clock source is 16MHz, each duty is adjustable:

nsM

5.6216

1

PWMDTY0 changes from 40 to 39, high time of PWM0 output reduced 62.5ns.


Period T=5us

PWM0

PWM1

back dead zone delay

t1=62.5nS

③Add RC circuit on PWM0, where R = 100Ω, C = 330pF

There are:

nspF 33330100

Rising edge delay:

VV 57.05

5Vln=tup

nsns 6.392.133=

Falling edge delay:

V53.0

5Vlntdown

nsns 6.392.133

Now, the back dead time delay changes to:

nsnsnstdown 9.226.395.62t1




Period T=5us

PWM0

PWM1

PWM1_IN

back dead zone delay

t1-tdown=22.9nS

former dead zone delay

tup=39.6nS

ton=0.7VDD

toff=0.3VDD

PWM0_IN

In this way we can get two complementary PWM square waves with former dead zone with ~39.6ns and

back dead zone with ~22.9ns delay.

Dead zone delay values

The larger the dead zone delay is; the more reliable system will be. However, this might cause output waveform distortion and reduced efficiency. Smaller dead zone delay could provide higher efficiency but reduce the system reliability. Generally dead zone delay should be limited within 10ns for normal power components. It could also be adjusted based on the tube features.



12 GP I/O SC91F8311 provides up to 13 GPIO ports, 13 I/O multiplexed with other functions. The sinking current

driving capability of P1.1~P1.5, P2.0, P2.4~P2.7 is twice than that of others I/O, can be used as LED or digital tube COM driver. The same as the standard 8051 I/O port, the SC91F8311 I/O port is a bidirectional I/O port with a strong push-pull output. There are four I/O modes: quasi-bidirectional I/O mode, the strong push-pull output mode, high impedance input, only the N-type open-drain output mode.

Quasi-bidirectional I/O stucture: Setting to "0", the I/O port has strong (>15mA) push low (Sinking) capability, which should be regarded as "Output". However, setting to "1", the I/O port will only have strong pull-up capability (two clock cycles) for a while, and then change and keep the I/O port as a high output in a weak pull-up condition. At the same time, external input signal is allowed to override the weak pull-up. In simple terms, writing "0" stands for strong "Output", while "1" stands for "Input".

Strong push-pull output stucture: When special strong push-pull output needed, the PxCFGn register can be configured to let the I/O port output strong "1" with strong currenting driving capability, rather than the “1" which is allowed to be override.

The high impedance input only structure: in high resistance state, for input only. N-type open-drain output structure: the internal pull-up resistors within the chipset disconnected. External

pull-up resistors are needed.

12.1 GPIO Structure 1. Quasi-Bi mode

Quasi-Bi I/O has 3 pull-up MOS to adapt to different needs: weak pull-up, very weak pull-up and strong pull-up.

Weak pull-up MOS: When Data register and pin are set 1, this pull-up provides the basic drive current that quasi- bidirectional ports output high. External circuit pull the output-high pin to low, weak pull-up will be off and very weak pull-up will keep on. In order to pull this pin low intensity, external circuit must have sufficient sink current capability to drop the voltage of port below the threshold voltage.

Very weak pull-up MOS: Provide weak pull-up current to pull the pin high when port latch is 1 when the port is floating.

Strong pull-up Mos: When the port latch transition from 0 to 1, strong pull-up is used to speed up the quasi-bi port conversion from logic 0 to logic 1 in almost 2 machine cycles. Quasi-bi model port structure diagram is shown below.

VDD VDD VDD

Input

Output

register

PORT

P

N

P P

StrongVery

WeakWeak

2 Clocks

Delay

Quasi-bi mode

(Standard 8051 I/O)

2. Strong Push-Pull Mode

The pull-low structure in push-pull mode is same as Quasi-Bi mode, but the port provides a continuous



strong pull-up (>15mA) when the port latch is 1. Push-Pull mode port structure diagram is shown as below:

VDD

Input

Output

register

PORT

N

Strong Push-Pull

Mode

P

3. High impedance input

High impedance input mode diagram is shown as below:

Input

PAD

PxyM[1:0]==10(Pure Input)

High impedance input Mode

4. Open Drain Mode This mode does not output a high capacity. If you need high output, the user must pull-up resistor. The

applied voltage on Pin can not exceed the VDD +0.3 V. Open drain mode diagram is shown as below:



Input

Output

register

PADN

PxyM[1:0]==11(N-type Open Drain)

Open Drain Mode

12.2 I/O SFR P0CFG0 (85h) P0 configuration0 (R/W)

Bit No 7 6 5 4 3 2 1 0

Symbol P03M[1: 0] P02M[1: 0] P01M[1: 0] P00M[1: 0]


Reset value 1 0 1 0 1 0 1 0

P1CFG1 (91h) P1 configuration1 (R/W)

Bit No 7 6 5 4 3 2 1 0

Symbol - - P15M[1: 0] P14M[1: 0]

R/W - - - - R/W R/W R/W R/W

Reset value x x x x 1 0 1 0

P1CFG0 (92h) P1 configuration0 (R/W)

Bit No 7 6 5 4 3 2 1 0

Symbol P13M[1: 0] P12M[1: 0] P11M[1: 0] -

R/W R/W R/W R/W R/W R/W R/W - -

Reset value 1 0 1 0 1 0 x x

P2CFG1 (A1h) P2 configuration1 (R/W)

Bit No 7 6 5 4 3 2 1 0

Symbol - P26M[1: 0] P25M[1: 0] P24M[1: 0]

R/W - - R/W R/W R/W R/W R/W R/W

Reset value x x 1 0 1 0 1 0

P2CFG0 (A2h) P2 configuration0 (R/W)

Bit No 7 6 5 4 3 2 1 0

Symbol - - - P20M[1: 0]

R/W - - - - - - R/W R/W

Reset value x x x x x x 1 0


3~0 P0xM[1:0]

（x=0~3）

P0 Mode setting 00: P0 as Quasi-bi mode 01: P0 as strong push pull mode 10: P0 as high impedance input mode (default value) 11: P0 as N type open drain mode

5~1 P1xM[1:0]

（x=1~5）

P1 Mode setting 00: P1 as Quasi-bi mode 01: P1 as strong push pull mode 10: P1 as high impedance input mode (default value)



11: P1 as N type open drain mode

6~4,0 P2xM[1:0]

（x=0,4~6）

P2 Mode setting 00: P2 as Quasi-bi mode 01: P2 as strong push pull mode 10: P2 as high impedance input mode (default value) 11: P2 as N type open drain mode

P0 (80h) P0 Data Register (R/W)

Bit No 7 6 5 4 3 2 1 0

Symbol - - - - P0.3 P0.2 P0.1 P0.0

R/W - - - - R/W R/W R/W R/W

Reset x x x x 1 1 1 1

P1 (90h) P1 Data Register (R/W)

Bit No 7 6 5 4 3 2 1 0

Symbol - - P1.5 P1.4 P1.3 P1.2 P1.1 -

R/W - - R/W R/W R/W R/W R/W -

Reset x x 1 1 1 1 1 x

P2 (A0h) P2 Data Register (R/W)

Bit No 7 6 5 4 3 2 1 0

Symbol - P2.6 P2.5 P2.4 - - - P2.0

R/W - R/W R/W R/W - - - R/W

Reset x 1 1 1 x x x 1


3~0 P0.x

（x=0~3）

P0 Data

5~1 P1.x

（x=1~5）

P1 Data

6~4,0 P2.x (x=0,4~6)

P2 Data

12.3 I/O PORT MULTIPLEX (Omission)



13 High Sensitive Touch Key Sensor The SC91F8311 is integrated with 8-channel high sensitive capacitive touch key sensor circurt, which can

achieve touch key function without physically touch the key, proximity sensing and other functions. The library for the high sensitive touch key is provided.

The main features:

① Achieve touch key function without physically touch the key. The distance between finger and key could be up to 6.5mm;

② Up to 8-channel high sensitive touch keys; ③ Integrated with various anti-jamming circuits: high anti-interference capacity, operates in EFT 4KV

condition; ④ Touch key function normally not affected by the thickness of the medium used as touch pad High sensitive capacitive touch circuit diagram:

High reliability

Power Circuit

Cmod

Cx (0~15)

VCC

Super anti-

jamming circuit

High-precision capacitance

amplification measurement

circuit

14 UART The SC91F8311 builts in a hardware UART serial port communication circuit with baud rate generator,

which can be easily used in connection with other devices or equipment, such as WIFI or other chipsets.

The UART port has partial useful features of any standard UART port: ① Traditional UART communication mode 1 and 3; ② Build in baud rate generator. The clock source is Fosc/4; ③ Interrupt can be generated after transfer and receive complete;



14.1 UART SFR SCON (98h) Serial Port Control Register (R/W)

Bit No 7 6 5 4 3 2 1 0

Symbol SM0 - SM2 REN TB8 RB8 TI RI

R/W R/W - R/W R/W R/W R/W R/W R/W

Reset 0 x 0 0 0 0 0 0


7 SM0 Serial communication mode control bit 0 0: Mode 1, which is 10-bit full-duplex asynchronous communication, consisting of one start bit, eight data bits and one stop bit, and the communication baud rate is variable; 1: Mode 3, which is 11-bit full-duplex asynchronous communication consisting of one start bit, eight data bits, a programmable 9th bit and one stop bit, and the communication baud rate is variable;

5 SM2 Serial communication mode control bit 1 (This control bit is only valid for mode 3) 0: To generate an interrupt request RI when receiveing a full set of data frames; 1: To generate an interrupt request RI when receiveing a full set of data frames and RB8 is set to 1.

4 REN Receive enable control bit 0: Data receiving not allowed; 1: Data receiving allowed

3 TB8 Transfer the ninth data, valid for Mode 3 ONLY

2 RB8 Receive the ninth data, valid for Mode 3 ONLY

1 TI Transfer Interrupt Flag bit 0: Cleared by software 1: Set by hardware, execute when transfer stop bit

0 RI Receive Interrupt Flag bit 0: Cleared by software 1: Set by hardware, transmission stop bit execution

SBUF (99h) Serial Port Data Buffer Register (R/W)

Bit No 7 6 5 4 3 2 1 0

Symbol SBUF[7:0]


Reset 0 0 0 0 0 0 0 0


7~0 SBUF[7:0] Serial port data buffer register SBUF contains two registers: a transmit shift register and a receive latch register. The data wrote to SBUF will be sent to the transmit shift register, and trigger the sending process; It will return the content the latch register received when reading SBUF.

BAUDGL (9Ah) Baud Rate Generator L Register (R/W)

Bit No 7 6 5 4 3 2 1 0

Symbol BAUDG[7:0]


Reset 0 0 0 0 0 0 0 0


7~0 BAUDG[7:0] Baud Rate Generator timer low 8 bit



BAUDGH (9Bh) Baud Rate Generator H Register (R/W)

Bit No 7 6 5 4 3 2 1 0

Symbol ENBAUDG - BAUDG[13:8]

R/W R/W - R/W R/W R/W R/W R/W R/W

Reset 0 x 0 0 0 1 0 0


7 ENBAUDG Baud rate generator Enable 1: Baud rate generator Disabled 0: Baud rate generator Enabled

5~0 BAUDG[13:8] The High Six Bits for Baud Rate Generator Timer

The formula for the serial communication baud rate:

14.2 UART MODE DESCRIPTION The UART of SC91F8311 can work in two modes: Mode 1 and Mode 3. Mode 1 is 10-bit variable bauds

full-duplex asynchronous communication; Mode 3 is 11-bit variable bauds full-duplex asynchronous communication. The UART mode list and descriptions are as below:

MODE SM0 SM2 Type Frame Length

Start Bit Stop Bit The 9th Bit

Data Baud Rate

Mode 1 0 - Asynchronous 10-bit 0 1 - Can be set

Mode 3 1 0/1 Asynchronous 11-bit 0 1 0/1 Can be set

UART Mode 1: 10-bit communication, 8-bit data, variable baud rate, asynchronous full-duplex.

Mode 1 provides 10-bit full-duplex asynchronous communications, consisting of one start bit (0), eight data bits (bit0 to be the first) and one stop bit (1). When receiving data, the 8 data bits will be stored in the SBUF register.

Any writing data to SBUF action will trigger data transmission which started from the time of system clock when the counter of the braud rate generator appears the next jump. Therefore, Fosc/4 is synchronized with the data transmission time, while not synchronized with the SBUF writing operation. Data Transmission Timing Chart:

Mode 1: Data Transmission Timing Chart

Shift CLK

TxD

D0 D1 D2 D3 D4 D5 D6 D7

TI

Write to SBUF

Start Stop

Data Receiving is only allowed when REN is set to 1. Detecting the RXD pin falling edge, the serial port starts receiving serial communication data. System clock has been keeping on sampling the RXD voltage level until starting to receive 8-bit data and load to SBUF register when RXD is confirmed to be a reliable 0 and the



start bit is confirmed to be valid as well. Meeting both two conditions: “RI=0” and “Received-Stop-Bit=1”, RI will beset to 1 and data receiving completed. Otherwise, the received data will be lost, and the chipset will restart the RXD voltage level detection. RI value should be cleared by software in order to receive data one again. Data Receiving Timing Chart:

Mode 1: Data Receiving Timing Chart

Shift CLK

RxD

D0 D1 D2 D3 D4 D5 D6 D7

RI

Start Stop

Bit Sample

UART Mode 3: 11-bit, 9-bit data, variable baud rate, asynchronous full-duplex.

Mode 3 provides 11-bit full-duplex asynchronous communications, consisting of one start bit (0), nine data bits (bit0 to be the first) and one stop bit (1). When receiving data, 8 data bits will be stored in the SBUF register, and the 9th data bit will be stored in RB8 register. During data transmission, the 9th data bit TB8 register can be written to 0 or 1. For example, the parity bit P of the PSW, or the data/address flag bit used for multi machine communication, can be written to TB8 register.

Any writing data to SBUF action will trigger data transmission and load TB8 to the 9th bit of the transmit shift register. Data transmission starts from the time of system clock when the counter of the braud rate generator appears the next jump. Therefore, Fosc/4 is synchronized with the data transmission time, while not synchronized with the SBUF writing operation. The start bit of the data to be transferred shifts out from the TxD pin at first, and ends up at the 9th data bit. When the stop bit of the above data starting data transmission on TxD pin, TI flag is set to 1. Data Transmission Timing Chart:

Mode 3:Data Transmission Timing Chart

Shift CLK

TxD

D0 D1 D2 D3 D4 D5 D6 D7

TI

Write to SBUF

Start StopD8

Data Receiving is only allowed when REN is set to 1. Detecting the RXD pin falling edge, the serial port

starts receiving serial communication data. System clock has been keeping on sampling the RXD voltage level until starting to receive 9-bit data and load to SBUF register when RXD is confirmed to be a reliable 0 and the start bit is confirmed to be valid as well. Meeting both two conditions: “RI=0” and “Received-Stop-Bit=1”, RI will beset to 1 and data receiving completed. Otherwise, the received data will be lost, and the chipset will restart the RXD voltage level detection. RI value should be cleared by software in order to receive data one again.



Data Receiving Timing Chart:

Mode 3: Data Receiving Timing Chart

Shift CLK

RxD

D0 D1 D2 D3 D4 D5 D6 D7

RI

Start Stop

Bit Sample

D8

15 Softwar LCD Driver All the SC91F8311 I/Os can be used as LCD COM or SEG in terms of software (we called as Software

LCD Driver). Besides the functions as normal I/O, each I/O has two groups of selectable output voltage: 1/3VDD, 2/3VDD; 1/2VDD. Any I/O can be selected as LCD COM or SEG on preferrence.

15.1 SOFTWARE LCD SFR LCD Driver related SFR Register Description:

symbol address description 7 6 5 4 3 2 1 0 Reset value

P0LCDVO A3H Voltage Output on

P0 LCD Port - - - - P03VO P02VO P01VO P00VO xxxx0000


P1 LCD Port - - P15VO P14VO P13VO P12VO P11VO - xx00000x


P2 LCD Port - P26VO P25VO P24VO - - - P20VO x000xxx0

LCDVOS AFH LCD Voltage Output

Selection - - - - VOIRS[1:0] - VOS xxxx00x0

P0LCDVO (A3H) , the Register for the Voltage Output on P0 LCD Port (R/W)

Bit No 7 6 5 4 3 2 1 0

Symbol - - - - P03VO P02VO P01VO P00VO

R/W - - - - R/W R/W R/W R/W



Bit No 7 6 5 4 3 2 1 0

Symbol - - P15VO P14VO P13VO P12VO P11VO -

R/W - - R/W R/W R/W R/W R/W -

Reset x x 0 0 0 0 0 x


Bit No 7 6 5 4 3 2 1 0

Symbol - P26VO P25VO P24VO - - - P20VO

R/W - R/W R/W R/W - - - R/W

Reset x 0 0 0 x x x 0


7~0 PxyVO (x=0~2, y=0~7)

LCD voltage output port Pxy enable 0: Disable Pxy port LCD voltage output 1: Enable Pxy port LCD voltage output

LCDVOS (AFH) LCD Voltage Output Selection (R/W)



Bit No 7 6 5 4 3 2 1 0

Symbol - - - - VOIRS[1:0] - VOS

R/W - - - - R/W R/W - R/W

Reset x x x x 0 0 x 0


3~2 VOIRS[1:0] Selections of Dividing Resistor on LCD Voltage Output port (based on LCD display size) 00: Close the internal resistor (power save) 01: select internal 25K resistor 10: select internal 50K resistor 11: select internal 100K resistor

0 VOS Selections of Output Voltage on LCD Voltage Output: When PxyVO=1, I/O's LCD feature is on. The correlation at different settings for LCD voltage output is as below:

IO Pxy LCD voltage output

PxyM[10]=10, Px.y=0

PxyM[10]=10, Px.y=1

VOS=0 - 1/2VDD

VOS=1 1/3VDD 2/3VDD

NOTE: Px.y is the value of the bit y of the Px register for the Pxy port.

15.2 SOFTWARE LCD DRIVER USAGE INSTRUCTIONS AND NOTES The drive signal of the LCD SEG/COM is A.C. analog signal. The contrast ratio of the LCD display pixels

depends on the valid value of the voltage difference between COM voltage and the SEG voltage Vcom-Vseg at the current display point. When the voltage difference is greater than the saturation voltage of the LCD, display can be turned on at this point; otherwise the LCD display will be turned off. It requires each COM/SEG switching between gated and non-gated voltage within a scanning cycle based on needs. I/O should be set to high impedance input state when SC91F8311 operating with non-gated voltage (1/2VDD@1/2Bias; 1/3VDD, 2/3VDD@1/3Bias). When SC91F8311 operating with the gated voltage (VDD, VSS), I/O should be set to strong push-pull output state.

Switching from gated voltage to non-gated voltage, the I/O state should be set to high impedance input at first. For 1/3 Bias, the I/O’s output value should be set again. Finally, the I/O state should be set as LCD output port by configuring PXLCDVO.

Switching from non-gate voltage to gated voltage, the I/O should be set as GPIO output again by configuring PXLCDVO at first, and then the I/O’s output value should be set again. Finally, the I/O state should be set as strong push-pull output.

1/2 Bias LCD Applications COM Waveform Diagram for 1/2 Bias LCD:



COM0

COM1

COM2

COM3

1 Frame 1 Frame

VDD

1/2 VDD

VSS

VDD

1/2 VDD

VSS

VDD

1/2 VDD

VSS

VDD

1/2 VDD

VSS

The following table shows the correlation between the voltage level of COM/SEG and display for 1/2 Bias

LCD during a COM0~COM3 scanning cycle：

COM0 COM1 COM2 COM3 SEG On SEGn Off

VDD 1/2VDD 1/2VDD 1/2VDD VSS VDD

VSS 1/2VDD 1/2VDD 1/2VDD VDD VSS

1/2VDD VDD 1/2VDD 1/2VDD VSS VDD

1/2VDD VSS 1/2VDD 1/2VDD VDD VSS

1/2VDD 1/2VDD VDD 1/2VDD VSS VDD

1/2VDD 1/2VDD VSS 1/2VDD VDD VSS

1/2VDD 1/2VDD 1/2VDD VDD VSS VDD

1/2VDD 1/2VDD 1/2VDD VSS VDD VSS

Taking 1/2 Bias for an instance. The configuration procedure for selecting P00 as a COM port to output 3-level voltage is as below:

① Set LCDVOS=0x04; Select 1/2 Bias output and set the minimum internal dividing resistor; ② Output VDD: Set P0LCDVO=0x00, P0=0x01, and P0CFG0=0x01; ③ Output 1/2 VDD: Set P0CFG0=0x02, P0=0x01, and P0LCDVO=0x01; ④ Output VSS: Set P0LCDVO=0x00, P0=0x00, and P0CFG0=0x01.

1/3 Bias LCD Applications 1/3 Bias LCD gated and non-gated voltage:



COM

SEG

SELECT UNSELECT

SELECT UNSELECT

VDD

2/3 VDD

1/3 VDD

VSS

VDD

2/3 VDD

1/3 VDD

VSS

1/4 DUTY 1/3 BIAS

COM/SEG Waveform Diagram for 1/3 Bias applicaitions:



COM0

COM1

COM2

COM3

1 Frame 1 Frame

VDD

2/3 VDD

1/3 VDD

VSS

SEGn

VDD

2/3 VDD

1/3 VDD

VSS

VDD

2/3 VDD

1/3 VDD

VSS

VDD

2/3 VDD

1/3 VDD

VSS

VDD

2/3 VDD

1/3 VDD

VSS

The correlation table for 1/3 Bias D.C. voltage different options:

Item 1/3 Bias LCD

D.C. Dividing Voltage Level

VDD 2/3 VDD 1/3 VDD

VSS

The 1st half of the scanning cycle

COM Gated VDD

Non-gated 1/3 VDD

SEG Gated VSS

Non-gated 2/3 VDD

The 2nd half of the scanning cycle

COM Gated VSS

Non-gated 2/3 VDD

SEG Gated VDD



Non-gated 1/3 VDD

1/3 Bias, the configuration procedure for selecting P00 as a COM port to output 4-level voltage is as below:

① Set LCDVOS=0x05; Select 1/3 Bias output and set the minimum internal dividing resistor; ② Output VDD: Set P0LCDVO=0x00, P0=0x01 and P0CFG0=0x01; ③ Output 1/3 VDD: Set P0CFG0=0x02, P0=0x00 and P0LCDVO=0x01; ④ Output VSS: Set P0LCDVO=0x00, P0=0x00 and set P0CFG0=0x01; ⑤ Output 2/3 VDD: Set P0CFG0=0x02, P0=0x01 and P0LCDVO=0x01.

Note: The 1/2 VDD, 1/3 VDD and 2/3 VDD output by I/O are from the chipset internal VDD by dividing

output voltage (the value of the dividing resistor is the VOIRS selected by user). In the I/O multiplexing function situation, the other functions will NOT affect the voltage.

A standard software LCD program is available to help user easily configure LCD function.

16 Analog Digital Converter (ADC) SC91F8311 has a 12-bit SAR Analog to Digital Converter (ADC) which could achieve multiplexing

functions with I/O ports.

The general features:

① 12-bit resolution;

② 10 bits or more precision;

③ Internal channel AIN0 can be accessed by internal 1/3 VDD voltage dividing to measure VDD;

④ 4 external channels AIN1~3,7 used for external signal measurement;

⑤ Built-in precisely tuned 2.4V reference voltage;

⑥ Generating interrupt when measuring process completes

There are two options for ADC reference voltage:

① Internal VDD;

② Precisely tuned 2.4V voltage output by internal regulator.

16.1 ADC SFR ADCCFG (C4h) ADC Refrence Voltage Configuration Register (R/W)

Bit No 7 6 5 4 3 2 1 0

Symbol P15AIN7 - - - P26AIN3 P25AIN2 P24AIN1 VREFS

R/W R/W - - - R/W R/W R/W R/W

Reset 0 x x x 0 0 0 n


7,3~1 PyzAINx (x=1~3,7)

P2/P1 Port Configuration 0: P1xAinx are GPIO

1: P1xAinx are ADC Channel n input, will automatically disable the

internal pull-up resistor

0 VREFS reference voltage selection 0: internal VDD 1: internal precious tuned 2.4V

ADCCR (C5h) ADC Control Register (R/W)

Bit No 7 6 5 4 3 2 1 0

Symbol ADCEN ADCS LOWSP EOC/ ADCIF

- ADCIS[2:0]

R/W R/W Write1 R/W R/W - R/W R/W R/W

Reset 0 0 0 0 x 0 0 0




7 ADCEN Turn on ADC 0: Power off ADC Modules 1: Turn on ADC Modules

6 ADCS ADC Start Set this bit to convert ADC once time

5 LOWSP ADC Clocks Selection 0: select 2MHz as ADC Clock 1: reserved Total conversion time are 20 ADC clocks.

4 EOC /ADCIF End of Conversion / ADC Interrupt Flag 0: Conversion is not completed 1: Conversion has been completed

2~0 ADCIS[2:0] ADC Input Selector 000: 1/3 VDD, can be used to measure VDD 001: P2.4 as the input of ADC 010: P2.5 as the input of ADC 011: P2.6 as the input of ADC 100: reserved 101: reserved 110: reserved 111: P1.5 as the input of ADC

3 reserved reserved

ADCVH (C6h)ADC Data register High (High 8bit) (R/W)

Bit No 7 6 5 4 3 2 1 0

Symbol ADCV[11:4]


Reset x x x x x x x x

ADCVL (C7h) ADC Data register Low (Low 4bit) (R/W)

Bit No 7 6 5 4 3 2 1 0

Symbol ADCV[3:0] - - - -

R/W R/W R/W R/W R/W - - - -

Reset x x x x x x x x


7~0 ADCV[11:4] ADC Data high 8 bit

7~4 ADCV[3:0] ADC Data Low 4 bit

IE (A8h) Interrupt Enable Register (R/W)

Bit No 7 6 5 4 3 2 1 0



Reset 0 0 0 0 0 0 0 0

Bit No Symbol 说明

6 EADC ADC interrupt Enable 0: Disable ADC interrupt 1: Enable ADC interrupt

IP (B8h) Interrupt priority Register (R/W)

Bit No 7 6 5 4 3 2 1 0



Reset x 0 0 0 0 0 0 0




6 IPADC ADC interrupt Priority 0: ADC interrupt Priority is Low 1: ADC interrupt Priority is high

16.2 ADC Conversion Steps ADC Conversion Steps are as follows:

① Select the ADC input channel (set IO used as ADC input);

② Select the ADC reference voltage and ADC clock;

③ Enable the ADCEN;

④ Configure the ADCIS;

⑤ Set ADCS, the conversion start;

⑥ When EOC/ADCIF=1, If EADC=1, ADC interrupt occurs, user clear the EOC/ADCIF;

⑦ Read the ADC Data from ADCVH and ADCVL, ADCVH read first and then ADCVL;

⑧ Repeat the Steps from 5 to 7, user can complete conversion once a time. Note: Before setting IE[6] (EADC) or after the interruption service is executed , it is recommend to clear EOC/ADCIF, to avoid continuous ADC interrupt.

16.3 ADC Measuring VDD Voltage In addition to measure external voltage signal, SC91F8311 can also measure VDD voltage with the internal ADC

channel AIN0, which can be used as Power Voltage Detection circuit or Low Power Detection (LPD) use. To achieve VDD voltage measurement, the internal 2.4V should be set as ADC reference voltage, the AIN0 channel should be set as ADC input channel, and the LCDVOS (AFH) set to 0X05 (that is to use 1/3 VDD voltage dividing circuit). Then to perform the normal ADC conversion process to get ADCV, the exact value of VDD voltage could be calculated by the value ADCV.

As shown below, VDD voltage value VDD = 2.4 * ADCV * 3/4096, the value of ADCV is the ADC conversion result.

AIN0

Internal 2.4V ADC

reference voltage

VDD voltage detecting circuit

1/3 VDD

voltage

dividing circuit

12 bit ADC

converter

circuit

ADCV

conversion

result value ADCIFVDD

Set AFH register

LCDVOS=0x05

17 IAP Operation The IAP performing address range for SC91F8311 has two options: 1. Internal highest address 256B Flash (address 1F00H ~ 1FFFH) can perform In Application Programming (IAP),

that is, used as EEPROM. 2. The whole 8KB ROM can perform In Application Programming (IAP), mainly for remote update purpose.

The above options are selected as Code Option when Code Option be written to the chipset with programmer.

IFB Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0

IFB2 - - - - IAPS - - -



IAPS =0: Only 1F00H~1FFFH can perform IAP IAPS =1: All 8K FLASH ROM can perform IAP * Reminder: There will be some risks to perform IAP with all 8KB flash ROM option. Software should work together

with hardware in order to ensure safety. Be care of the selection.

17.1 IAP SFR IAP SFR Description:

symbol address description 7 6 5 4 3 2 1 0 Reset value

IAPKEY EAH IAP key IAPKEY[7: 0] 00000000b

IAPADH EBH IAP address high - - - IAPADR[12:8] xxx11111b

IAPADL ECH IAP address low IAPADR[7: 0] 11111111b

IAPDAT EDH IAP Data(write) IAPDAT[7: 0] 11111111b

IAPCTL EEH IAP command - - - - PAYTIMES

[1: 0] CMD[1: 0] xxxx0000b

IAPKEY (EAH) IAP key (R/W)

Bit No 7 6 5 4 3 2 1 0

Symbol IAPKEY[7: 0]


Reset 0 0 0 0 0 0 0 0


7~0 IAPKEY[7: 0] Enable IAP function and set IAP operating time limited

Write a value n means: ①enable IAP function; ②In n system clock,

the MCU does not receive IAP write command, then the IAP function will be re-closed;

IAPADH (EBH) IAP IAP Write Address High 5bit (R/W)

Bit No 7 6 5 4 3 2 1 0

Symbol - - - IAPADR[12:8]

R/W - - - R/W R/W R/W R/W R/W

Reset x x x 1 1 1 1 1


4~0 IAPADR[12:8] IAP write address high 5bit

IAPADL (ECH) IAP Write Address Low 8bit (R/W)

Bit No 7 6 5 4 3 2 1 0

Symbol IAPADR[7: 0]


Reset 1 1 1 1 1 1 1 1


7~0 IAPADR[7: 0] IAP write address low 8bit

IAPDAT (EDH) IAP Data (R/W)

Bit No 7 6 5 4 3 2 1 0

Symbol IAPDAT[7: 0]


Reset 1 1 1 1 1 1 1 1


7~0 IAPDAT IAP write data

IAPCTL (EEH) IAP control (R/W)



Bit No 7 6 5 4 3 2 1 0

Symbol - - - - PAYTIMES[1: 0] CMD[1: 0]

R/W - - - - R/W R/W R/W R/W



3~2 PAYTIMES[1: 0] In IAP function, CPU Hold Time setting 00: CPU HOLD TIME about 4ms@16/8MHz 01: CPU HOLD TIME about 2ms@16/8MHz 10: CPU HOLD TIME about 1ms@16/8MHz 11: reserved Note1: the CPU only hold PC; the other functional modules will continue to work. Interrupt flag will be saved, and will respond after the end of the Hold interrupt. If the same interrupt occurs several times, the system can retain and respond to the last. Note2: VDD at 2.7V~5.5V, set as 10 VDD at 2.4V~5.5V, set as 01 or 00

1~0 CMD[1: 0] IAP write command 00: reserved 01: reserved 10: write 11: reserved



17.2 256B IAP Operation Process and Demo Program The operation process of SC91F8311 IAP is shown as below: ① Write IAPDAT[7: 0] (prepare the data to write); ② write {IAPADR[11: 8], IAPADR[7: 0]} (prepare the address of IAP operation, IAPADR[11: 8] is always 1); ③ write IAPKEY[7: 0] to value n (Open IAP, please give writing command of IAP in n system Clocks);

④ write IAPCTL[3: 0] (setting CPU Hold time, write CMD[1: 0] to 1、0, CPU Hold and start to IAP

operation); ⑤ IAP writing completed, CPU continue others operations; Note: User can read the Data of IAP by using MOVC instruction.

SC91F8311 256B IAP Demo Program is shown as below:

#include ”intrins.h” unsigned char code *POINT=0x1f00; unsigned char DATA1,ADDR1;

IAP writing operation , C Demo program:

IAPDAT=DATA1; //send DATA1 to IAP Data register IAPADH=0x1f; //write high 5bit address IAPADL=ADDR1; //write low 8bit address ADDR1 IAPKEY=0xf0; //you can change this value

// Pay special attention to the value when you use interrupt IAPCTL=0x0a; // IAP command, 1 ms@16/8M _nop_(); // wait (need at least 1_nop_()) _nop_(); _nop_(); _nop_();

IAP reading operation, C Demo program:

DATA1=*(POINT+ADDR1); //read Data of ADDR1 to DATA1

IAP reading operation, Assembly Demoprogram: MOV DPTR, #1f00H; //DPTR initial value MOV A, ADDR1; //address to A MOVC A, @A+DPTR; //read the value of ADDR1 to A

17.3 8K Range IAP Application Notes There are some risks to perform IAP with all 8KB flash ROM option, which requires some protections during software

processing, in order to avoid user’s program be modified. Unless some must-have functions needed (such as remote programmer updates, etc.), this option is not recommended.



18 Electrical Characteristics 18.1 Absolute Maximum Ratings

Symbol Parameter Min Max UNIT

VDD/VSS Operating Voltage -0.3 5.5 V

Voltage ON any Pin

Input/Output Voltage -0.3 VDD+0.3 V

TA Operating Temperature -40 85 ℃

TSTG Storage Temperature -55 125 ℃

18.2 Recommended Operating Conditions Symbol Parameter Min Max UNIT

VDD Operating Voltage 2.4 5.5 V

TA Operating Temperature -40 85 ℃

18.3 DC Electrical Characteristics (VDD = 5V, TA =+ 25℃)

Symbol Parameter Min Type Max Unit condition

current

Iop1 operating current 1 - 8.0 10 mA IRC=16MHz

Iop2 operating current 2 - 5.0 7.0 mA IRC=8MHz

Ipd1 STOP current 1 (Power Down mode)

- 0.1 1.0 μA

Itk1 Touchkey current 1.6 2.4 mA IRC=16MHz

IO characteristics

VIH Input High Voltage 0.7VDD - VDD+0.5 V

VIL Input Low Voltage -0.5 - 0.3VDD V

VIH,RST Input High Voltage(RSTN Pin)

2.0 VDD V

VIL,RST Input Low Voltage (RSTN Pin)

-0.2 1.5 V

IOL1 Sink current P0 13 mA VPin=0.4V


IOL3 Sink current P1/P2

23 mA VPin=0.4V


43 mA VPin=0.8V

IOH1 Pull-up current (Quasi-Bi Mode) P0/P1/P2

60 μA Vpin=4.7V

IOH2 Pull-up current (Push- pull mode)P0/P1/P2

12 mA Vpin=4.3V


5.5 mA Vpin=4.7V

Internal Precious 2.4V

VDD24 internal 2.4V 2.37 2.4 2.45 V TA=-40~85℃

(VDD = 3.3V, TA = +25℃)

Symbol Parameter Min Type Max Unit condition

current

Iop3 operating current 3 8.0 10 mA IRC=16MHz

Iop4 operating current 4 4.6 5.8 mA IRC=8MHz

Ipd2 STOP current 2 (Power Down mode)

- 0.1 1 μA

Itk2 Touchkey current 1.25 1.80 mA IRC=16MHz

IO characteristics

VIH Input High Voltage 0.7VDD - VDD+0.5 V



VIL Input Low Voltage -0.5 - 0.3VDD V

VIH,RSTN Input High Voltage (RSTN Pin)

2.0 VDD V

VIL,RSTN Input Low Voltage (RSTN Pin)

-0.2 1.5 V




17 mA VPin=0.4V


30 mA VPin=0.8V

IOH4 Pull-up current (Quasi-Bi Mode) P0/P1/P2

40 μA Vpin=3.0V


3.7 mA Vpin=3.0V

Internal Precious 2.4V

VDD24 internal 2.4V 2.37 2.40 2.45 V TA=-40~85℃

18.4 AC Electrical Characteristics (VDD = 2.5V ~ 5.5V, TA = 25℃)

Symbol Parameter Min Max UNIT Symbol

Parameter

Tosc Oscillator start time 60 80 μs IRC=16MHz VDD=5V

Treset Reset pulse width 18 μs Low active

FIRC Frequency Stability(RC) 15.84 16 16.16 MHz VDD=4.5~5.5V

TA=-20~85 ℃

18.5 ADC Electrical Characteristics (TA = 25℃) Symbol Parameter Min Type Max Unit condition

VAD ADC supply Voltage 2.4 5.0 5.5 V

NR Resolution 12 bit GND≤VAIN≤VREF

VAIN ADC Input voltage GND VDD V

RAIN ADC Input Resistor 1 M VIN=5V

Rref Vref input resistor 13.5 K

ZAIN Recommended impedance of analog

voltage source

5 K

IADC1 ADC conversion current 1 0.55 0.75 mA ADC ON VDD=5V

IADC2 ADC conversion current 2 0.50 0.70 mA ADC ON VDD=3.3V

DNL Differential linearity error ±2 LSB VDD=5V VREF=5V

INL Integral linearity error ±3 LSB VDD=5V VREF=5V

EAD Total Absolute error ±3 LSB VDD=5V VREF=5V

TADC Total conversion Time 20 tAD



19 Application Circuit

L3

L4

L5

L6

VCC

L2

L1

P11/RSTN4

P12/RXD5

P13/INT1/TXD6

P14/INT2/PWM07

P15/INT3/AIN78

P26/TK14/AIN39

P25/TK13/AIN210

P24/TK12/AIN111

P20/TK8/T012

P03/TK313

P02/TK214

P01/TK1/PWM1A15

P00/TK0/PWM0A16

VDD1

CMOD2

VSS3

/CLK

/ENB

/DIO/CEN

U1

SC91F8311

Cadj103

C1

10uF/16V

R2

1K

R3

1K

R4 510R

R5 510R

R6 510R

R7 510R

R8 510R

C2104

ENBCLK

DIOCEN

GND

R1

1K

TK6

TK5

TK4

TK7

TK3

TK2

TK1

TK0

R9 510R

R10 510R

R11 510R

123456

J1

Progmramme Interface

VCC

GND

ENB

CLKDIO

CEN



20 Ordering Information PRODUCT NO PKG PACKING

SC91F8311M16U SOP16 TUBE



21 Package Information SOP16L (150mil) outline dimensions unit: mm

L

e1

~ ~~£c

Detail F

LE

c

See Detail F

e1

S

Seating Plane

D

A1

A2

A

D y

e

1 8

916

b

E HE

Symbol mm

Min Nom Min

A - - 1.75

A1 0.05 - 0.225

A2 1.30 1.40 1.50

b 0.39 - 0.48

C 0.21 - 0.26

D 9.70 9.90 10.10

E 3.70 3.90 4.10

HE 5.80 6.00 6.20

e 1.27(BSC)

L 0.50 - 0.80

LE 1.05(BSC)

0 - 8



22 Datasheet Change Notice Version content Date

V1.3 Change IRC frequency to 16M/8M Jan, 2017

V1.2 Correct the value of IO port characteristics in electrical characteristics section

Dec, 2016

V1.1 Correct the description of the SRAM section Oct, 2016

V1.0 Original Apr, 2016

sinone chip sc91f8311 · 4 block diagram 1t 8051 core 8kb program rom (flash) 512b ram timer0...

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