singlecycle-22017/02/14 · single-cycle datapath for arithmetic and logical instructions executing...

2/14/17

1

SamiraKhanUniversityofVirginia

Feb14,2017

IntrotoMicroarchitecture:Single-Cycle

CS3330

AGENDA• Reviewfromlastlecture

• Single-cyclemicroarchitecture

• Evaluationofsingle-cyclemicroarchitecture

2

RecapofLastWeek• ISAbasicsandtradeoffs

• Instructionlength• Uniformvs.non-uniformdecode• Numberofregisters• Addressingmodes• RISCvs.CISCproperties

3

ANoteonRISCvs.CISC• Usually,…

• RISC• Simpleinstructions• Fixedlength• Uniformdecode• Fewaddressingmodes

• CISC• Complexinstructions• Variablelength• Non-uniformdecode• Manyaddressingmodes

4

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2

Y86-64InstructionSet#1Byte

pushq rA A 0 rA F

jXX Dest 7 fn Dest

popq rA B 0 rA F

call Dest 8 0 Dest

cmovXX rA, rB 2 fn rA rB

irmovq V, rB 3 0 F rB V

rmmovq rA, D(rB) 4 0 rA rB D

mrmovq D(rB), rA 5 0 rA rB D

OPq rA, rB 6 fn rA rB

ret 9 0

nop 1 0

halt 0 0

0 1 2 3 4 5 6 7 8 9

5

AVeryBasicInstructionProcessingEngine• Single-cyclemachine

• Whatistheclockcycletimedeterminedby?• Whatisthecriticalpath ofthecombinationallogicdeterminedby?

AS’ AS(State)CombinationalLogic

6

InstructionProcessing“Stage”• Instructionsareprocessedunderthedirectionofa“controlunit” stepbystep.

• Instructionstage:Sequenceofstepstoprocessaninstruction• Fundamentally,therearefivephases:

• Fetch• Decode• Execute• Memory• StoreResult

• Notallinstructionsrequireallstages

7

Single-cyclevs.Multi-cycle:Control&Data• Single-cyclemachine:

• Controlsignalsaregeneratedinthesameclockcycleastheoneduringwhichdatasignalsareoperatedon

• Everythingrelatedtoaninstructionhappensinoneclockcycle(serializedprocessing)

• Multi-cyclemachine:• Controlsignalsneededinthenextcyclecanbegeneratedinthecurrentcycle

• Latencyofcontrolprocessingcanbeoverlappedwithlatencyofdatapath operation(moreparallelism)

8

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3

ASingle-CycleMicroarchitectureACloserLook

Let’sStartwiththeStateElements• Dataandcontrolinputs

Registerfile

A

B

W dstW

srcA

valA

srcB

valB

valW

ALU

Operation

A

B

MUX0

1

PC

InstructionMem

InstrAddr

InstructionDataMem

AddressReadData

WriteData

RegWrite

MemWrite

MemRead

MUXSelect

10

InstructionProcessing• 6(5)genericsteps

• Instructionfetch(IF)• Instructiondecodeandregisteroperandfetch(ID/RF)• Execute/Evaluatememoryaddress(EX/AG)• Memoryoperandfetch(MEM)• Store/writeback result(WB)• PCUpdate

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem

InstrAddr Instruction

DataMem

Address ReadData

WriteData

rA

ValE

IF ID/RF EX/AG WBMEM

newPC

11



Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address ReadData

WriteData

rA

ValE


newPC

12

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4



Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address ReadData

WriteData

rA

ValE


newPC

13



Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address ReadData

WriteData

rA

ValE


newPC

14

Single-CycleDatapathforArithmeticandLogical

Instructions

ExecutingArith./LogicalOperation

•Fetch• Read2bytes

•Decode• Readoperandregisters

•Execute• Performoperation• Setconditioncodes

•Memory• Donothing

•Writeback• Updateregister

•PCUpdate• IncrementPCby2

OPq rA, rB 6 fn rA rB

ifMEM[PC]==OPq rA, rBR[rB]¬R[rB] opR[rA]PC¬ PC+2

16

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StageComputation:Arith/Log.Ops

• Formulateinstructionexecutionassequenceofsimplesteps

• Usesamegeneralformforallinstructions

OPq rA,rBicode:ifun¬M1[PC]rA:rB¬M1[PC+1]

valP¬ PC+2

FetchReadinstructionbyteReadregisterbyte

ComputenextPCvalA¬ R[rA]valB¬ R[rB]

Decode ReadoperandAReadoperandB

valE¬ valBOPvalASetCC

Execute PerformALUoperationSetconditioncoderegisterMemory

R[rB]¬ valEWrite

backWritebackresult

PC¬ valPPCupdate UpdatePC

17

ALUDatapath

**Basedonoriginalfigurefrom[P&HCO&D,COPYRIGHT2004Elsevier.ALLRIGHTSRESERVED.]


Combinationalstateupdatelogic

IF ID EX MEM WB

Registerfile

ValB

rA

DestE

valAALU

PC

InstructionMem


DataMem

Address ReadData

WriteData

rB

ValE

ADD

RegWrite ALU

OP

PC

2

18

ALUDatapath

**Basedonoriginalfigurefrom[P&HCO&D,COPYRIGHT2004Elsevier.ALLRIGHTSRESERVED.]



IF ID EX MEM WB

Registerfile

ValB

rA

DestE

valAALU

PC

InstructionMem


DataMem

Address ReadData

WriteData

rB

ValE

ADD

RegWrite ALU

OP

PC

2

19

Single-CycleDatapathforDataMovementInstructions

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Executingmrmovq (LoadfromMemtoReg)



•Execute• Computeeffectiveaddress

•Memory• Readfrommemory

•Writeback• WritetoRegister


6 fn rA rB

mrmovq D(rB),rA

D

ifMEM[PC]==mrmovq Disp (rB), rAEA=Disp +R[rB]R[rA]¬MEM[EA]PC¬ PC+10 21

StageComputation:mrmovq

• UseALUforaddresscomputation

mrmovq D(rB),rAicode:ifun¬M1[PC]rA:rB¬M1[PC+1]valC¬M8[PC+2]valP¬ PC+10

Fetch

ReadinstructionbyteReadregisterbyteReaddisplacementDComputenextPC

valB¬ R[rB]Decode

ReadoperandBvalE¬ valB +valC

ExecuteComputeeffectiveaddress

valM¬ M8[valE]Memory WritevaluetomemoryR[rA]¬ valMWrite

backPC¬ valPPCupdate UpdatePC

ifMEM[PC]==mrmovq Disp (rB), rAEA=Disp +R[rB]R[rA]¬MEM[EA]PC¬ PC+10 22

Ld Datapath

ifMEM[PC]==mrmovq Disp (rB), rAEA=Disp +R[rB]R[rA]¬MEM[EA]PC¬ PC+10


IF ID EX MEM WB

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

D

FromALU

FromMem10

PC

23

Ld Datapath:CalculatetheEffectiveAddress



IF ID EX MEM WB

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

D

FromALU

FromMem10

PC

24

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IF ID EX MEM WB

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

D

FromALU

FromMem10

PC

Ld Datapath:LoadedmemoryneedstobewrittentotheRegisterFile

25



IF ID EX MEM WB

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

D

FromALU

FromMem10

PC

Ld Datapath:NeedtheDestinationRegister

26



IF ID EX MEM WB

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

D

FromALU

FromMem10

PC

Ld Datapath:UpdatePC

27

Executingrmmovq (Stfromreg toMemory)



•Execute• Computeeffectiveaddress

•Memory• Writetomemory

•Writeback• Donothing


rmmovq rA,D(rB)

4 0 rA rB D

ifMEM[PC]==rmmovq rA, Disp (rB)EA=Disp +R[rB]MEM[EA]¬R[rA]PC¬ PC+10 28

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StageComputation:rmmovq


rmmovq rA,D(rB)icode:ifun¬M1[PC]rA:rB¬M1[PC+1]valC¬M8[PC+2]valP¬ PC+10

Fetch


valA¬ R[rA]valB¬ R[rB]

DecodeReadoperandAReadoperandB

valE¬ valB+valCExecute

Computeeffectiveaddress

M8[valE]¬ valAMemory WritevaluetomemoryWrite


ifMEM[PC]==rmmovq rA, Disp (rB)EA=Disp +R[rB]MEM[EA]¬R[rA]PC¬ PC+10 29

StDatapath

ifMEM[PC]==rmmovq rA, Disp (rB)EA=Disp +R[rB]MEM[EA]¬R[rA]PC¬ PC+10


IF ID EX MEM WB

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

D

FromALU

FromMem

PC

10

MemWrite

30

StDatapath:Calculatetheeffectiveaddress

ifMEM[PC]==rnmovq rA, Disp (rB)EA=Disp +R[rB]MEM[EA]¬R[rA]PC¬ PC+10


IF ID EX MEM WB

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

D

FromALU

FromMem

PC

10

MemWrite

31



IF ID EX MEM WB

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

D

FromALU

FromMem

PC

10

MemWrite

StDatapath:Storedataneedstoreachmemory

32

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IF ID EX MEM WB

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

D

FromALU

FromMem

PC

10

MemWrite

StDatapath:UpdatePC

33

Executingirmovq (Moveimm toReg)



•Execute• Add0toV


•Writeback• WriteVtorB


irmovq V, rB

3 0 F rB V

ifMEM[PC]==irmovq V, rBR[rB]¬ V + 0PC¬ PC+10

34

StageComputation:irmovq


irmovq V,rBicode:ifun¬M1[PC]rA:rB¬M1[PC+1]valC¬M8[PC+2]valP¬ PC+10

Fetch


Decode

valE¬ 0 +valCExecute


R[rB]¬ valAMemory WritevaluetomemoryWrite


ifMEM[PC]==irmovq V, rBR[rB]¬ V + 0PC¬ PC+10

35

irmov Datapath:Option1

ifMEM[PC]==irmovq V, rBR[rB]¬ V + 0PC¬ PC+10 Combinational

stateupdatelogic

IF ID EX MEM WB

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

D

FromALU

FromMem

MUX

0

PC

MemWrite

10

36

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irmov Datapath Option1:readregisterandaddzero


stateupdatelogic

IF ID EX MEM WB

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

D

FromALU

FromMem

MUX

0

PC

MemWrite

10

37

irmov Datapath Option1:Writeback value


stateupdatelogic

IF ID EX MEM WB

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

D

FromALU

FromMem

MUX

0

PC

MemWrite

10

38


stateupdatelogic

IF ID EX MEM WB

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

D

FromALU

FromMem

MUX

0

PC

MemWrite

10

irmovDatapathOption1:Writebackvalue

39

irmov Datapath Option1:UpdatePC


stateupdatelogic

IF ID EX MEM WB

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

D

FromALU

FromMem

MUX

0

PC

MemWrite

10

40

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irmov Datapath Option2

ifMEM[PC]==irmovq V, rBR[rB]¬ VPC¬ PC+10 Combinational

stateupdatelogic

IF ID EX MEM WB

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

D

FromALU

FromMem

PC

MemWrite

10

41

irmov Datapath:Option2

ifMEM[PC]==irmovq V, rBR[rB]¬ VPC¬ PC+10 Combinational

stateupdatelogic

IF ID EX MEM WB

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

D

FromALU

FromMem

PC

MemWrite

10

42

• Tradeoffsbetweenoption1andoption2?

• Extra2-to-1MUX?• 3-to-1MUX?Whatisthecostforn-to-1MUX?• Wirelength?• Generality?

43

Executingrrmovq (MovefromReg toReg)


•Decode• ReadoperandregisterrA

•Execute• Add0toval rA


•Writeback• Writeval rA torB


2 0 rA rB

rrmovq rA, rB

ifMEM[PC]==rrmovq rA, rBR[rB]¬ R[rA]+0PC¬ PC+2 44

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StageComputation:rrmovqrrmovq rA,rBicode:ifun¬M1[PC]rA:rB¬M1[PC+1]

valP¬ PC+2

Fetch


ValA¬ R[rA]Decode

valE¬ 0 +valAExecute


Memory WritevaluetomemoryR[rB]ß valEWrite


ifMEM[PC]==rrmovq rA, rBR[rB]¬ R[rA]+0PC¬ PC+2 45

rrmov Datapath:Option1

ifMEM[PC]==rrmovq rA, rBR[rB]¬ R[rA]+0PC¬ PC+2 Combinational

stateupdatelogic

IF ID EX MEM WB

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

D

FromALU

FromMem

MUX

0

PC

MemWrite

2

46



stateupdatelogic

IF ID EX MEM WB

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

D

FromALU

FromMem

MUX

0

PC

MemWrite

2

47



stateupdatelogic

IF ID EX MEM WB

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

D

FromALU

FromMem

MUX

0

PC

MemWrite

2

48

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13



stateupdatelogic

IF ID EX MEM WB

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

D

FromALU

FromMem

MUX

0

PC

MemWrite

2

49


ifMEM[PC]==rrmovq rA, rBR[rB]¬ R[rA]PC¬ PC+2 Combinational

stateupdatelogic

IF ID EX MEM WB

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

D

FromALU

FromMem

PC

MemWrite

10 ?50

Single-CycleDatapathforControlFlowInstructions

ExecutingJumps

•Fetch• Read9bytes• IncrementPCby9

•Decode• Donothing

•Execute• Determinewhethertotake

branchbasedonjumpconditionandconditioncodes


•Writeback• Donothing

•PCUpdate• SetPCtoDest ifbranchtakenor

toincrementedPCifnotbranch

jXX Dest 7 fn Dest

XX XXfallthru:

XX XXtarget:

Nottaken

Taken

jmp 7 0

jle 7 1

jl 7 2

je 7 3

jne 7 4

jge 7 5

jg 7 6

ifMEM[PC]==jmp Destif(cond)PCß Dest elsePCß PC+9 52

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StageComputation:Jumps

• Computebothaddresses• Choosebasedonsettingofconditioncodesandbranchcondition

jXXDesticode:ifun¬M1[PC]

valC¬M8[PC+1]valP¬ PC+9

Fetch

Readinstructionbyte

ReaddestinationaddressFallthroughaddress

Decode

Cnd¬ Cond(CC,ifun)Execute

Takebranch?MemoryWrite

backPC¬ Cnd ?valC :valPPCupdate UpdatePC

ifMEM[PC]==jmp Destif(cond)PCß Dest elsePCß PC+9 53

Jump

ifMEM[PC]==jmp DestPCß Dest Combinational

stateupdatelogic

IF ID EX MEM WB

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

D

FromALU

FromMem

MUX

0

PC

MemWrite

2 MUX

109

MUX

D

54

UnconditionalJump

ifMEM[PC]==jmp DestPCß Dest Combinational

stateupdatelogic

IF ID EX MEM WB

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

D

FromALU

FromMem

MUX

0

PC

MemWrite

2 MUX

109

MUX

D

55

ConditionalJump

ifMEM[PC]==jmp Destif(cond)PCß Dest elsePCß PC+9 Combinational

stateupdatelogic

IF ID EX MEM WB

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

D

FromALU

FromMem

MUX

0

PC

MemWrite

2 MUX

109

MUX

D

56

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Executingcall

•Fetch• Read9bytes• IncrementPCby9

•Decode• Readstackpointer

•Execute• Decrementstackpointerby8

•Memory• WriteincrementedPCtonew

valueofstackpointer

•Writeback• Updatestackpointer

•PCUpdate• SetPCtoDest

call Dest 8 0 Dest

XX XXreturn:

XX XXtarget:

ifMEM[PC]==call DestMEM[R[rsp]-8]ß PC+9R[rsp]ß R[rsp]- 8PCß Dest

57

StageComputation:call

• UseALUtodecrementstackpointer• StoreincrementedPC

call Desticode:ifun¬M1[PC]

valC¬M8[PC+1]valP¬ PC+9

Fetch

Readinstructionbyte

ReaddestinationaddressComputereturnpoint

valB¬ R[%rsp]Decode

ReadstackpointervalE¬ valB +–8

ExecuteDecrementstackpointer

M8[valE]¬ valPMemory WritereturnvalueonstackR[%rsp]¬ valEWrite

backUpdatestackpointer

PC¬ valCPCupdate SetPCtodestination


58

Call



IF ID EX MEM WB

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address

ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

DFromALU

FromMem

MUX

0

PC

MemWrite

2 MUX

109

MUX

D

MUX

rB

rsp

rsp

8MUX

FromPC+x

59

Call:Decrementstackpointer



IF ID EX MEM WB

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address

ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

DFromALU

FromMem

MUX

0

PC

MemWrite

2 MUX

109

MUX

D

MUX

rB

rsp

rsp

8MUX

FromPC+x

60

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16

Call:Writereturnaddress tomemory



IF ID EX MEM WB

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address

ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

DFromALU

FromMem

MUX

0

PC

MemWrite

2 MUX

109

MUX

D

MUX

rB

rsp

rsp

8MUX

FromPC+x

61

Call:Updatersp intheregisterfile



IF ID EX MEM WB

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address

ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

DFromALU

FromMem

MUX

0

PC

MemWrite

2 MUX

109

MUX

D

MUX

rB

rsp

rsp

8MUX

FromPC+x

62

Call:UpdatePC



IF ID EX MEM WB

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address

ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

DFromALU

FromMem

MUX

0

PC

MemWrite

2 MUX

109

MUX

D

MUX

rB

rsp

rsp

8MUX

FromPC+x

63

Executingret

•Fetch• Read1byte


•Execute• Incrementstackpointerby8

•Memory• Readreturnaddressfromold

stackpointer

•Writeback• Updatestackpointer

•PCUpdate• SetPCtoreturnaddress

ret 9 0

XX XXreturn:

ifMEM[PC]==retPCßMEM[R[rsp]]R[rsp]ß R[rsp]+8 64

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StageComputation:ret

• UseALUtoincrementstackpointer• Readreturnaddressfrommemory

ret

icode:ifun¬M1[PC]

Fetch

Readinstructionbyte

valA¬ R[%rsp]valB¬ R[%rsp]

DecodeReadoperandstackpointerReadoperandstackpointer

valE¬ valB +8Execute

Incrementstackpointer

valM¬M8[valA]Memory ReadreturnaddressR[%rsp]¬ valEWrite

backUpdatestackpointer

PC¬ valMPCupdate SetPCtoreturnaddress

ifMEM[PC]==retPCßMEM[R[rsp]]R[rsp]ß R[rsp]+8 65

ifMEM[PC]==retPCßMEM[R[rsp]]R[rsp]ß R[rsp]+8

Ret


IF ID EX MEM WB

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address

ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

DFromALU

FromMem

MUX

0

PC

MemWrite

2 MUX

109

MUX

D

MUX

rB

rsp

rsp

8

MUX

FromPC+x

MUX

66


Ret:Incrementstackpointer


IF ID EX MEM WB

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address

ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

DFromALU

FromMem

MUX

0

PC

MemWrite

2 MUX

109

MUX

D

MUX

rB

rsp

rsp

8

MUX

FromPC+x

MUX

67


Ret:ReadreturnaddressfromMemory


IF ID EX MEM WB

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address

ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

DFromALU

FromMem

MUX

0

PC

MemWrite

2 MUX

109

MUX

D

MUX

rB

rsp

rsp

8

MUX

FromPC+x

MUX

68

2/14/17

18


Ret:UpdatePC


IF ID EX MEM WB

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address

ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

DFromALU

FromMem

MUX

0

PC

MemWrite

2 MUX

109

MUX

D

MUX

rB

rsp

rsp

8

MUX

FromPC+x

MUX

69


Ret:Updatersp


IF ID EX MEM WB

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address

ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

DFromALU

FromMem

MUX

0

PC

MemWrite

2 MUX

109

MUX

D

MUX

rB

rsp

rsp

8

MUX

FromPC+x

MUX

70

Single-CycleDatapath forStackOperations

Executingpopq



•Execute• Incrementstackpointerby8

•Memory• Readfromoldstackpointer

•Writeback• Updatestackpointer• Writeresulttoregister


popq rA b 0 rA 8

72

ifMEM[PC]==popR[rA]ßMEM[R[rsp]]R[rsp]ß R[rsp]+8

2/14/17

19

StageComputation:popq

• UseALUtoincrementstackpointer• Mustupdatetworegisters

• Poppedvalue• Newstackpointer

popq rAicode:ifun¬M1[PC]rA:rB¬M1[PC+1]

valP¬ PC+2

Fetch

ReadinstructionbyteReadregisterbyte

ComputenextPCvalA¬ R[%rsp]valB¬ R[%rsp]

DecodeReadstackpointerReadstackpointer

valE¬ valB +8Execute

Incrementstackpointer

valM¬M8[valA]Memory ReadfromstackR[%rsp]¬ valER[rA]¬ valM

Write

backUpdatestackpointerWritebackresult


73



Pop


IF ID EX MEM WB

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address

ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

DFromALU

FromMem

MUX

0

PC

MemWrite

2 MUX

109

MUX

D

MUX

rB

rsp

rsp

8

MUX

FromPC+x

MUX

74

Pop

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address

ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

D FromALU

FromMem

MUX

0

MemWrite

2 MUX

109

MUX

D

MUX

rB

rsp

rsp

8

MUX

FromPC+x

MUX

DestM ValM

75

Pop:Incrementstackpointer

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address

ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

D FromALU

FromMem

MUX

0

MemWrite

2 MUX

109

MUX

D

MUX

rB

rsp

rsp

8

MUX

FromPC+x

MUX

DestM ValM

76


2/14/17

20

Pop:ReadpushedvaluefromMemory

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address

ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

D FromALU

FromMem

MUX

0

MemWrite

2 MUX

109

MUX

D

MUX

rB

rsp

rsp

8

MUX

FromPC+x

MUX

DestM ValM

77


Pop:Movethevaluetoregisterfile

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address

ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

D FromALU

FromMem

MUX

0

MemWrite

2 MUX

109

MUX

D

MUX

rB

rsp

rsp

8

MUX

FromPC+x

MUX

DestM ValM

78


Pop:Writeback rsp value

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address

ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

D FromALU

FromMem

MUX

0

MemWrite

2 MUX

109

MUX

D

MUX

rB

rsp

rsp

8

MUX

FromPC+x

MUX

DestM ValM

79


Pop

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address

ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

D FromALU

FromMem

MUX

0

MemWrite

2 MUX

109

MUX

D

MUX

rB

rsp

rsp

8

MUX

FromPC+x

MUX

DestM ValM

80

2/14/17

21

Pop

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address

ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUX

rB

rA

D FromALUFromMem

MUX

0

MemWrite

2 MUX

109

MUX

D

MUX

rB

rsp

rsp

8

MUX

FromPC+x

MUX

DestM ValM

81

EvaluatingtheSingle-CycleMicroarchitecture

ASingle-CycleMicroarchitecture• Isthis agoodidea/design?

• Whenisthisagooddesign?

• Whenisthisabaddesign?

• Howcanwedesignabettermicroarchitecture?

83

ASingle-CycleMicroarchitecture:Analysis

• Everyinstructiontakes1cycletoexecute• CPI(Cyclesperinstruction)isstrictly1

• Howlongeachinstructiontakesisdeterminedbyhowlongtheslowestinstructiontakestoexecute

• Eventhoughmanyinstructionsdonotneedthatlongtoexecute

• Clockcycletimeofthemicroarchitectureisdeterminedbyhowlongittakestocompletetheslowestinstruction

• Criticalpathofthedesignisdeterminedbytheprocessingtimeoftheslowestinstruction

84

2/14/17

22

WhatistheSlowestInstructiontoProcess?n Let’sgobacktothebasics

n Allsixphasesoftheinstructionprocessingcycletakeasinglemachineclockcycle tocomplete

• Fetch• Decode• EvaluateAddress• FetchOperands• Execute• StoreResult

• Doeachoftheabovephasestakethesametime(latency)forallinstructions?

1. Instruction fetch (IF)2. Instruction decode and

register operand fetch (ID/RF)3. Execute/Evaluate memory address (EX/AG)4. Memory operand fetch (MEM)5. Store/writeback result (WB)

85

Single-CycleDatapath Analysis• Assume

• memoryunits(readorwrite):200ps• ALUandadders:100ps• registerfile(readorwrite):50ps• othercombinationallogic:0ps

steps IF ID EX MEM WBDelay

resources mem RF ALU mem RF

Reg-Reg Op 200 50 100 50 400ir mov 200 50 100 50 400LW 200 50 100 200 50 600SW 200 50 100 200 550Call 200 50 100 200 50 600Jump 200 200 86

Ld Datapath



IF ID EX MEM WB

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

D

FromALU

FromMem10

PC

200ps250ps

350ps

550ps

600ps

100ps

87

SingleCycleuArch:Complexity• Contrived

• Allinstructionsrunasslowastheslowestinstruction

• Inefficient• Allinstructionsrunasslowastheslowestinstruction• Mustprovideworst-casecombinationalresourcesinparallelasrequiredbyanyinstruction

• Needtoreplicatearesourceifitisneededmorethanoncebyaninstructionduringdifferentpartsoftheinstructionprocessingcycle

• NotnecessarilythesimplestwaytoimplementanISA• Single-cycleimplementationofREPMOVS(x86)orINDEX(VAX)?

• Noteasytooptimize/improveperformance• Optimizingthecommoncasedoesnotwork(e.g.commoninstructions)• Needtooptimizetheworstcaseallthetime

88

2/14/17

23

(Micro)architectureDesignPrinciples• Criticalpathdesign

• Findanddecreasethemaximumcombinationallogicdelay• Breakapathintomultiplecyclesifittakestoolong

• Breadandbutter(commoncase)design• Spendtimeandresourcesonwhereitmattersmost

• i.e.,improvewhatthemachineisreallydesignedtodo• Commoncasevs.uncommoncase

• Balanceddesign• Balance instruction/dataflowthroughhardwarecomponents• Designtoeliminatebottlenecks:balancethehardwareforthework

89

Single-CycleDesignvs.DesignPrinciples

nCriticalpathdesign

nBreadandbutter(commoncase)design

nBalanceddesign

Howdoesasingle-cyclemicroarchitecturefareinlightoftheseprinciples?

90

SamiraKhanUniversityofVirginia

Feb14,2017

IntrotoMicroarchitecture:Single-Cycle

CS3330

StageComputation:Cond.Move

• ReadregisterrA andpassthroughALU• Cancelmovebysettingdestinationregisterto0xF

• Ifconditioncodes&moveconditionindicatenomove

cmovXX rA,rBicode:ifun¬M1[PC]rA:rB¬M1[PC+1]

valP¬ PC+2

Fetch

ReadinstructionbyteReadregisterbyte

ComputenextPCvalA¬ R[rA]valB¬ 0

DecodeReadoperandA

valE¬ valB +valAIf!Cond(CC,ifun)rB¬ 0xF

ExecutePassvalA throughALU(Disableregisterupdate)

MemoryR[rB]¬ valEWrite

backWritebackresult


92

ifMEM[PC]==cmov rA,rBif(cond)R[rB]ß R[rA]If(!cond)R[rB]ß 0xF

2/14/17

24

ifMEM[PC]==cmov rA,rBif(cond)R[rB]ß R[rA]If(!cond)R[rB]ß 0xF


IF ID EX MEM WB

Registerfile

ValA

rB

DestE

valBALU

PC

InstructionMem


DataMem

Address

ReadData

WriteData

rA

ValE

ADD

RegWrite ALU

OP

MUX

MUXSelect

MUX

rB

rA

MUX

DFromALU

FromMem

MUX

0

PC

MemWrite

2 MUX

109

MUX

D

MUX

rB

rsp

rsp

8

MUX

FromPC+x

MUX

93

singlecycle-22017/02/14 · single-cycle datapath for arithmetic and logical instructions executing...

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