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FEATURES

3

2

4

51NC VCC

Y

A

GND

DCK PACKAGE(TOP VIEW)

3

2

4

5

DBV PACKAGE(TOP VIEW)

1NC

A

GND

VCC

Y

DESCRIPTION/ORDERING INFORMATION

SN74LVC1G17-EP

SGLS336A–APRIL 2006–REVISED JUNE 2007

SINGLE SCHMITT-TRIGGER BUFFER

• ESD Protection Exceeds JESD 22• Controlled Baseline – 2000-V Human-Body Model (A114-A)

– One Assembly/Test Site, One Fabrication – 200-V Machine Model (A115-A)Site – 1000-V Charged-Device Model (C101)

• Extended Temperature Performance of –55°C (1) Component qualification in accordance with JEDEC andto 125°C industry standards to ensure reliable operation over an

extended temperature range. This includes, but is not limited• Enhanced Diminishing Manufacturing Sources to, Highly Accelerated Stress Test (HAST) or biased 85/85,(DMS) Support temperature cycle, autoclave or unbiased HAST,

electromigration, bond intermetallic life, and mold compound• Qualification Pedigree(1)life. Such qualification testing should not be viewed asjustifying use of this component beyond specified• Supports 5-V VCC Operationperformance and environmental limits.

• Max tpd of 4.6 ns at 3.3 V• Low Power Consumption, 10 μA Max ICC

• ±24 mA Output Drive at 3.3 V• Ioff Supports Partial Power Down Mode

Operation• Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

This single Schmitt-trigger buffer is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G17 contains one buffer and performs the Boolean function Y = A. The device functions as anindependent buffer, but because of Schmitt action, it may have different input threshold levels for positive-going(VT+) and negative-going (VT–) signals.

NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using thedie as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,preventing damaging current backflow through the device when it is powered down.

ORDERING INFORMATION (1)

TA PACKAGE (2) ORDERABLE PART NUMBER TOP-SIDE MARKING

SOT (SC-70) - DCK Reel of 3000 SN74LVC1G17MDCKREP C70–55°C to 125°C

SOP (SOT-23) - DBV Reel of 3000 SN74LVC1G17MDBVREP C170

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com.

(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available atwww.ti.com/sc/package.

FUNCTION TABLE

INPUT A OUTPUT Y

H H

L L

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

NanoStar, NanoFree are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Copyright © 2006–2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

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A Y2 4

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS (1)

SN74LVC1G17-EP

SGLS336A–APRIL 2006–REVISED JUNE 2007

LOGIC DIAGARAM (POSITIVE LOGIC)

over operating free-air temperature range (unless otherwise noted) (1)

VALUE UNIT

VCC Supply voltage range –0.5 to 6.5 V

VI Input voltage range (2) –0.5 to 6.5 V

Voltage range applied to any output in the high-impedance or power-off state –0.5 to 6.5 VVO

Voltage range applied to any output in the high or low state (2) (3) –0.5 to VCC + 0.5 V

IIK Input clamp current (VI < 0) –50 mA

IOK Output clamp current (VO < 0) -50 mA

IO Continuous output current ±50 mA

Continuous current through VCC or GND ±100 mA

θJA Package thermal impedance (4): DCK package 252 °C/W

Tstg Storage temperature range –65 to 150 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.(3) The value of VCC is provided in the recommended operating conditions table.(4) The package thermal impedance is calculated in accordance with JESD 51-7.

MAX MAX UNIT

Operating 1.65 5.5VCC Supply voltage V

Data retention only 1.5

VI Input voltage 0 5.5 V

VO Output voltage 0 VCC V

VCC = 1.65 V –4

VCC = 2.3 V –8

IOH High –16 mAVCC = 3 V

–24

VCC = 4.5 V –32

VCC = 1.65 V 4

VCC = 2.3 V 8

IOL Low-level output current 16 mAVCC = 3 V

24

VCC = 4.5 V 32

TA Operating free-air temperature –55 125 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report,Implications of Slow or Floating CMOS Inputs (SCBA004).

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ELECTRICAL CHARACTERISTICS

SN74LVC1G17-EP

SGLS336A–APRIL 2006–REVISED JUNE 2007

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP (1) MAX UNIT

1.65 V to 4.5 V 0.76 1.13

2.3 V 1.08 1.56Positive-going inputVT+ 3 V 1.48 1.92 Vthreshold voltage

4.5 V 2.19 2.74

5.5 V 2.65 3.33

1.65 V to 4.5 V 0.35 0.59

2.3 V 0.56 0.88Negative-goingVT– input threshold 3 V 0.89 1.2 V

voltage 4.5 V 1.51 1.97

5.5 V 1.88 2.4

1.65 V to 4.5 V 0.36 0.64&Delta;V<S 2.3 V 0.45 0.78ubscri Hysteresis 3 V 0.51 0.83 Vpt>T</ (VT+ – VT–)

4.5 V 0.58 0.93Subscript> 5.5 V 0.69 1.04

IOH = –100 mA 1.65 V to 4.5 V VCC – 0.1

IOH = -4 mA 1.65 V 1.2

IOH = –8 mA 2.3 V 1.9VOH V

IOH = –16 mA 2.43 V

IOH = –24 mA 2.3

IOH = –32 mA 4.5 V 3.8

IOL = 100 mA 1.65 V to 4.5 V 0.1

IOL = 4 mA 1.65 V 0.45

IOL = 8 mA 2.3 V 0.3VOL V

IOL = 16 mA 0.43 V

IOL = 24 mA 0.55

IOL = 32 mA 4.5 V 0.55

II A input VI = 5.5 or GND 0 to 5.5 V ±5 μA

Ioff VI or VO = 5.5 V 0 ±10 μA

ICC VI = 5.5 V or GND, IO = 0 1.65 V to 5.5 V 10 μA

One input at VCC – 0.6 V,ΔICC 3 V to 5.5 V 500 μAOther inputs at VCC or GND

Ci VI = VCC or GND 3.3 V 4.5 pF

(1) All typical values are at VCC = 3.3 V, TA = 25°C.

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SWITCHING CHARACTERISTICS

SWITCHING CHARACTERISTICS

OPERATING CHARACTERISTICS,

SN74LVC1G17-EP

SGLS336A–APRIL 2006–REVISED JUNE 2007

over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1)

VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 VFROM TO ±0.15 V ±0.2 V ±0.3 V ±0.5 VPARAMETER UNIT(INPUT) (OUTPUT)

MIN MAX MIN MAX MIN MAX MIN MAX

tpd A Y 2.8 9.9 1.6 5.5 1.5 4.6 0.9 4.4 ns

over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 2)

VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 VFROM TO ±0.15 V ±0.2 V ±0.3 V ±0.5 VPARAMETER UNIT(INPUT) (OUTPUT)

MIN MAX MIN MAX MIN MAX MIN MAX

tpd A Y 3.8 11 2 6.5 1.8 5.5 1.2 5 ns

TA = 25°C

VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 VPARAMETER TEST CONDITIONS UNIT

TYP TYP TYP TYP

Cpd Power dissipaton capacitance f = 10 MHz 20 21 22 26

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PARAMETER MEASUREMENT INFORMATION

VM

thtsu

From OutputUnder Test

CL(see Note A)

LOAD CIRCUIT

S1VLOAD

Open

GND

RL

RL

Data Input

Timing InputVI

0 V

VI

0 V0 V

tw

Input

VOLTAGE WAVEFORMSSETUP AND HOLD TIMES

VOLTAGE WAVEFORMSPROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMSPULSE DURATION

tPLH

tPHL

tPHL

tPLH

VOH

VOH

VOL

VOL

VI

0 VInput

OutputWaveform 1S1 at VLOAD(see Note B)

OutputWaveform 2

S1 at GND(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

VLOAD/2

0 V

VOL + V∆

VOH − V∆

≈0 V

VI

VOLTAGE WAVEFORMSENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

Output

tPLH/tPHLtPLZ/tPZLtPHZ/tPZH

OpenVLOADGND

TEST S1

NOTES: A. CL includes probe and jig capacitance.B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.D. The outputs are measured one at a time, with one transition per measurement.E. tPLZ and tPHZ are the same as tdis.F. tPZL and tPZH are the same as ten.G. tPLH and tPHL are the same as tpd.H. All parameters and waveforms are not applicable to all devices.

OutputControl

VM VM

VM VM

VM VM

VM

VM VM

VM

VM

VM

VI

VM

VM

1.8 V ± 0.15 V2.5 V ± 0.2 V3.3 V ± 0.3 V5 V ± 0.5 V

1 MΩ1 MΩ1 MΩ1 MΩ

VCC RL

2 × VCC2 × VCC

6 V2 × VCC

VLOAD CL

15 pF15 pF15 pF15 pF

0.15 V0.15 V0.3 V0.3 V

V∆

VCCVCC3 VVCC

VI

VCC/2VCC/21.5 VVCC/2

VMtr/tf

≤2 ns≤2 ns

≤2.5 ns≤2.5 ns

INPUTS

SN74LVC1G17-EP

SGLS336A–APRIL 2006–REVISED JUNE 2007

Figure 1. Load Circuit and Voltage Waveforms

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VM

thtsu

From OutputUnder Test

CL(see Note A)

LOAD CIRCUIT

S1VLOAD

Open

GND

RL

RL

Data Input

Timing InputVI

0 V

VI

0 V0 V

tw

Input

VOLTAGE WAVEFORMSSETUP AND HOLD TIMES

VOLTAGE WAVEFORMSPROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMSPULSE DURATION

tPLH

tPHL

tPHL

tPLH

VOH

VOH

VOL

VOL

VI

0 VInput

OutputWaveform 1S1 at VLOAD(see Note B)

OutputWaveform 2

S1 at GND(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

VLOAD/2

0 V

VOL + V∆

VOH − V∆

≈0 V

VI

VOLTAGE WAVEFORMSENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

Output

tPLH/tPHLtPLZ/tPZLtPHZ/tPZH

OpenVLOADGND

TEST S1

NOTES: A. CL includes probe and jig capacitance.B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.D. The outputs are measured one at a time, with one transition per measurement.E. tPLZ and tPHZ are the same as tdis.F. tPZL and tPZH are the same as ten.G. tPLH and tPHL are the same as tpd.H. All parameters and waveforms are not applicable to all devices.

OutputControl

VM VM

VM VM

VM VM

VM

VM VM

VM

VM

VM

VI

VM

VM

1.8 V ± 0.15 V2.5 V ± 0.2 V3.3 V ± 0.3 V5 V ± 0.5 V

1 kΩ500 Ω500 Ω500 Ω

VCC RL

2 × VCC2 × VCC

6 V2 × VCC

VLOAD CL

30 pF30 pF50 pF50 pF

0.15 V0.15 V0.3 V0.3 V

V∆

VCCVCC3 VVCC

VI

VCC/2VCC/21.5 VVCC/2

VMtr/tf

≤2 ns≤2 ns

≤2.5 ns≤2.5 ns

INPUTS

SN74LVC1G17-EP

SGLS336A–APRIL 2006–REVISED JUNE 2007

PARAMETER MEASUREMENT INFORMATION (continued)

Figure 2. Load Circuit and Voltage Waveforms

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PACKAGE OPTION ADDENDUM

www.ti.com 11-Apr-2013

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish MSL Peak Temp(3)

Op Temp (°C) Top-Side Markings(4)

Samples

CLVC1G17MDCKREPG4 ACTIVE SC70 DCK 5 3000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -55 to 125 C70

SN74LVC1G17MDBVREP ACTIVE SOT-23 DBV 5 3000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -55 to 125 C170

SN74LVC1G17MDCKREP ACTIVE SC70 DCK 5 3000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -55 to 125 C70

V62/06621-01XE ACTIVE SOT-23 DBV 5 3000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -55 to 125 C170

V62/06621-01YE ACTIVE SC70 DCK 5 3000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -55 to 125 C70

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is acontinuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

PACKAGE OPTION ADDENDUM

www.ti.com 11-Apr-2013

Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74LVC1G17-EP :

• Catalog: SN74LVC1G17

• Automotive: SN74LVC1G17-Q1

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

SN74LVC1G17MDBVREP SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

SN74LVC1G17MDCKREP SC70 DCK 5 3000 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3

PACKAGE MATERIALS INFORMATION

www.ti.com 3-Aug-2017

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

SN74LVC1G17MDBVREP SOT-23 DBV 5 3000 203.0 203.0 35.0

SN74LVC1G17MDCKREP SC70 DCK 5 3000 203.0 203.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 3-Aug-2017

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

C

TYP0.220.08

0.25

3.02.6

2X 0.95

1.9

1.45 MAX

TYP0.150.00

5X 0.50.3

TYP0.60.3

TYP80

1.9

A

3.052.75

B1.751.45

(1.1)

SOT-23 - 1.45 mm max heightDBV0005ASMALL OUTLINE TRANSISTOR

4214839/C 04/2017

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.2. This drawing is subject to change without notice.3. Refernce JEDEC MO-178.

0.2 C A B

1

34

5

2

INDEX AREAPIN 1

GAGE PLANE

SEATING PLANE

0.1 C

SCALE 4.000

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EXAMPLE BOARD LAYOUT

0.07 MAXARROUND

0.07 MINARROUND

5X (1.1)

5X (0.6)

(2.6)

(1.9)

2X (0.95)

(R0.05) TYP

4214839/C 04/2017

SOT-23 - 1.45 mm max heightDBV0005ASMALL OUTLINE TRANSISTOR

NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SYMM

LAND PATTERN EXAMPLEEXPOSED METAL SHOWN

SCALE:15X

PKG

1

3 4

5

2

SOLDER MASKOPENINGMETAL UNDER

SOLDER MASK

SOLDER MASKDEFINED

EXPOSED METAL

METALSOLDER MASKOPENING

NON SOLDER MASKDEFINED

(PREFERRED)

SOLDER MASK DETAILS

EXPOSED METAL

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EXAMPLE STENCIL DESIGN

(2.6)

(1.9)

2X(0.95)

5X (1.1)

5X (0.6)

(R0.05) TYP

SOT-23 - 1.45 mm max heightDBV0005ASMALL OUTLINE TRANSISTOR

4214839/C 04/2017

NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLEBASED ON 0.125 mm THICK STENCIL

SCALE:15X

SYMM

PKG

1

3 4

5

2

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