A c t e l ’ s A n t i f u s e F P G A s

Single Chip High Performance SolutionsN

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Actel’s antifuse devices are low cost,high performance solutions fortoday’s logic designer. Ideal for integrating logic typically imple-mented in multiple CPLDs, PALs,and FPGAs, antifuse devices offer significant cost savings while main-taining high performance. In addi-tion, the Actel antifuse technology ensures design security and getsyour design to market faster. Actelantifuse FPGAs, combining lowcosts and high performance, are thesingle-chip ASIC alternative.

S a v e S o m e M o n e yWith a smaller switching elementand a smaller die size, Actel’s anti-fuse FPGAs provide a substantialcost advantage over equivalent SRAMFPGAs. Plus, Actel’s antifuse FPGAsare nonvolatile, which allows thedevice to retain its configurationindefinitely and without an externalstorage device. With no externalstorage device necessary to hold thedevices’ configuration data, the costof a PROM or microprocessor andthe associated board space are elimi-nated, providing additional savings.

M a i n t a i n H i g hP e r f o r m a n c eLow cost does not mean low perfor-mance. With its low resistance andlow capacitance properties, Actel’s antifuse technology offers very highspeeds. And since Actel devices arepermanently programmed, they areinstantly operational on power-up.There is no boot up period whiledata is being downloaded from anexternal device.

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2K 5K 20K 30K 50K 100KGates

A c t e l A n t i f u s e P r o d u c t s

MX FPGAs

FutureAntifuseProducts

SX FPGAs

P r o t e c t Yo u r I n t e l l e c t u a l P r o p e r t y Design security is a necessity intoday’s highly competitive technologyindustry to protect designs frompirating. Actel’s antifuse FPGAsoffer that security. Actel devices donot need a start up bitstream, elimi-nating the possibility of configura-tion data being intercepted. Thisalso prevents in-system errors andaccidental data erasures that other-wise may occur during download.

Add to that the inherent security ofantifuse technology itself. The anti-fuses that form the interconnections within an Actel FPGA are extremelysmall, are densely distributed through-out the device (over 6.5 million onthe largest Actel device), and do notleave an observable signature thatcan be electrically probed or visuallyinspected. With these safeguards,Actel devices are virtually immuneto copying and reverse engineering.

S p e e d T i m e t o M a r k e t Actel devices offer a host of otherbenefits that simplify the designcycle and speed the design to mar-ket. Using Actel’s automatic placeand route tools, 100% logic utiliza-tion is possible, speeding designtime. And Actel’s unique general

and local routingstructure allows100% pin-locking,even at full logic utilization, so thePCB can be devel-oped concurrentlywith the FPGA.Even during verifi-cation, Actel devicescan be analyzed in-system and in realtime using theSilicon Explorerdiagnostic tool,decreasing verifica-tion times.

C o n s u m e L e s s P o w e rAn additional benefit of Actel’santifuse technology is its inherentlow power consumption. Antifuseshave low resistance properties, andthe architecture does not requireactive circuitry to hold a charge,reducing thermal and power supplydesign problems.

F P G A

A S I C

Ship productionsooner and start next design earlier

E x p l o r e

D e s i g n

S i m u l a t e

T e s t Ve c t o r s

D e b u g

M o d i f y

Q u a l

*Based on a 528 bit Shift Register implemented in an A54SX16P device using 77% of the device.

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1000

800

600

400

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P o w e r C o n s u m p t i o n *

With capacities ranging from 8,000to 72,000 gates, 270MHz systemperformance, and prices startingbelow $5.00, Actel’s SX FPGAs arethe high performance, low priceleader. Featuring a sea-of-modulesarchitecture, SX devices are able todeliver integration at performancelevels previously limited to ASICs.

S e a o f M o d u l e s — A nE v o l u t i o n i n A r c h i t e c t u r eSX’s sea-of-modules architecture isenabled by Actel’s patented metal-to-metal antifuse interconnect elements.The unique architecture consists of agrid of fine grained logic modulescovering the entire floor of the device,reducing the distance signals have totravel between logic modules, andsaving almost 1/2 the die size of anequivalent FPGA with a ChannelArray architecture. The result is thatSX devices cost less overall thanFPGAs of comparable density.

S p e e d T h i n g s U pTo minimize signal propagationdelay, SX devices employ both localand general routing resources. Thehigh-speed local routing resources(DirectConnect and FastConnect)enable very fast local signal propaga-tion, optimal for fast counters, statemachines, and datapath logic. The general system of segmented routingtracks allows any logic module in thearray to be connected to any otherlogic or I/O module. This uniquelocal and general routing structuregives fast and predictable perfor-mance, allowing designers to meettheir goals with a minimum of effort.

Further complementing the flexiblerouting structure is a hardwired,constantly-loaded clock networkthat has been tuned to provide fastclock propagation with a maximumclock skew of only .25ns. Withinternal clock speeds of 320MHzand clock-to-out of 3.7ns, designspreviously limited to ASICs cannow be implemented in SX FPGAs. Metal 3

Silicon

Metal 2Metal-to-metal

Antifuse

Metal 1Contact

Via

Metal 2

S X F P G A s

S X I / O P e r f o r m a n c e

INPUT ARRAY R-CELL

CLOCK

D Q

OUTPUT

TIRD1 0.3ns TIRD1 0.3ns

TDLH/DHL 1.6nsTINYH/INYL 1.5ns

THCK 1.0nsTRCK 1.5ns

TRCO 0.8nsTSUD 0.5ns Hardwired Routed

Clock Clock

External Set-up TSU

Clock-to-Out (pad-to-pad) TCO

1.3ns 0.8ns3.7ns 4.2ns

Numbers shown for A54SX16-3, worst case commercial conditions.

Metal-to-Metal Antifuse

Channel Array Architecture

Sea of ModulesArchitecture

I n d u s t r y’ s P r i c e / Pe r f o r m a n c e L e a d e r

P e r f o r m a n c eSX devices allow designers to achievea higher level of performance with-out using complicated and time consuming performance-enhancingdesign techniques. With otherFPGAs, designers frequently have to use techniques such as redundantlogic to reduce fanout on criticalnets, introducing data pipelining toreduce register-to-register delays, orthe instantiation of custom macrosin VHDL or Verilog-HDL code.

6 6 M H z P C I C o m p l i a n c eWith the SX family, designers canimplement high speed 66MHz PCIapplications. In conjunction withSX, Actel offers a suite of intellectualproperty (IP) cores, intended toenhance time-to-market for pro-grammable logic users.

I n t e g r a t e Yo u r G a t e sDesigns that were previously seg-mented between CPLDs (for speed)and FPGAs (for capacity) can nowbe easily integrated into a single SXFPGA, improving system reliabilityand reducing power consumption.And, of course, fewer componentsmeans reduced production costsassociated with component countsand board space.

C C C CR R

C C C CR R

Direct Connect• No antifuses• 0.1 ns routing delay

Fast Connect• One antifuses• 0.4 ns routing delay

Routing Segments• Typically 2 anitfuse• Max. 5 antifuses

S X A r c h i t e c t u r e

C P L D / F P G A I n t e g r a t i o n

FPGACPLD

ACTEL SX FPGA

CPLD

CPLD

CPLD

• 8b/10b encoder for 1Gigabit Ethernet

Router with 125Mbyte/sec sustained

data throughput.

• 66MHz compliant PCI Bus Arbiter

with a 6ns clock-to-out and 3ns

input set-up time.

• 52MHz DS3 to DS2 bi-directional

converter with 19ns reg-reg timing.

S X A p p l i c a t i o n s

With capacities ranging from 2,000to 36,000 gates, 250MHz systemperformance, and clock-to-out delays as low as 5.6ns, Actel’s MXfamily of FPGAs offers high perfor-mance 5.0V solutions.

A M i x e d Vo l t a g e S o l u t i o nActel's 42MX family of FPGAsincludes MultiPlex I/O, an architec-tural feature that supports mixed-voltage systems and delivers highperformance operation at 5.0V.

42MX FPGAs can operate in 5.0Vonly systems, 3.3V only systems,and mixed 5.0V/3.3V systems, whichallows for 5.0V input tolerance in a3.3V system while providing maxi-mum internal performance. Thisfeature provides flexibility whenworking with mixed-voltage systemsby ensuring compatibility betweendevices of different voltages.

P C I C o m p l i a n t MultiPlex I/O also features chipwideselectable PCI output drives, enabling100% PCI compliance for both 5.0Vand 3.3V I/O systems. In systemsthat do not require PCI, the PCIoutput drivers can be disabled tominimize switching currents.

E m b e d d e d D u a l - P o r t S R A M42MX devices contain embeddeddual-port SRAM modules. With a5ns access time, this device familyallows designers to build on-boardFIFOs and buffers with up to100MHz performance. TheseSRAM modules have been opti-mized for synchronous and asyn-chronous applications. The modulesare arranged in 256-bit blocks thatcan be configured 32x8 or 64x4.They can also be cascaded togetherto form memory spaces of user-definable width and depth. The42MX dual-port SRAM blocks pro-vide an optimal solution for high-speed buffered applications requiringfast FIFO or LIFO queues.

Signals Supplies

3.3vInput/Output

5.0vInput

5.0vInput/Output

3.3vInput/Output

3.3vVCC 1/0

5.0vVCC Array

5.0vVCC I/O

5.0vVCC Array

3.3vVCC 1/0

3.3vVCC Array

MIXEDOPERATION

PURE 5.0vOPERATION

PURE 5.0vOPERATION

I/O MODULE

Array

I/O MODULE

Array

I/O MODULE

Array

MX-FPGAs

P r i c e / Pe r f o r m a n c e L e a d e r a t 5 . 0 V

• POS Terminal application used 1 MX09

to replace over 20 ICs. Over 16,000 MX

devices have shipped in the product.

• An HDSL application migrated to a

lower cost and high performance MX

device, enabling the customer to cancel

plans to convert to an ASIC.

• A flight controller system used Actel’s

software and an MX16 to meet density

and performance requirements and

production commitments in ten weeks.

M X A p p l i c a t i o n s

M X V o l t a g e O p e r a t i o n s

D e s i g n S e r v i c e s — T h eO n e S t o p D e s i g n S o l u t i o nWith a ten-year history of providinghardware and software services, Actel’sProtocol Design Services group offersits customers design support at allstages of project development. Withextensive knowledge of FPGA designand prototyping, services are deliveredon time, within budget, and to thecustomers’ specifications.

D e v e l o p m e n tS o f t w a r eThe DeskTOP seriesbrings together the best insilicon, synthesis, and sim-ulation to create a com-plete and integrated designenvironment for designingActel FPGAs. The basicDeskTOP is an integrateddevelopment environment,including simulation, syn-thesis, and place and routetools, for designs less than50K gates.

DeskTOP Pro increasesthe design simulationlimit to 400K withunlimited synthesis,allowing designers tomove up as their skillsand density require-ments increase.

DeskTOP Open, whichincludes simulation up to400K, and place androute tools, is ideal forASIC designers who arestarting to use FPGAs intheir designs, but have alreadyinvested in synthesis tools.

Designer Advantage is Actel’s suiteof FPGA development point toolsfor PCs and Workstations thatincludes the ACTmap VHDLSynthesis tool, ACTgen MacroBuilder, Designer with DirectTimetiming driven place and route andanalysis tools, and the SiliconSculptor and APS device program-ming software.

R e a l - t i m e D e v i c eVe r i f i c a t i o n Actel’s antifuse FPGAs containActionProbe circuitry that providesbuilt-in access to every node in adesign, enabling 100% real-timeobservation and analysis of a device'sinternal logic nodes without design

iteration. The probe circuit-ry is accessed by SiliconExplorer, an easy to use veri-fication and logic analysistool for the PC. SiliconExplorer allows designers tocomplete the design verifica-tion process at their desks.

P r o g r a m m i n g Actel offers many program-ming options, includingActivator and SiliconSculptor single site andmulti-site device program-mers for PC and UNIX.And when the design isready to go to production,Actel has a programmingsolution for that too. Acteloffers volume program-ming services, throughDistribution partners.

D e s i g n I m p l e m e n t a t i o n

Silicon Explorer

Graphical HDLTestbench Generator

Actel

Design Management

Synthesis

Schematics/Symbols

BehavioralHDL

ACTgenMacro Builder

L ibrar ie s

Behavioral/Structural/Timing Simulator

VeribestWavebench

UserTestbench

EDIFNetlist

FuseFile

Veribest HDLSimulator

Compile

LayoutDT Analyze ChipEdit

DT Edit PinEdit

Fuse Extract

StructuralHDL

Netlist

SDFFile

P r o g r a m m i n g

APS SoftwareActivator 2/2s Programmer

Silicon Sculptor

SMS Sprint System General

BP MicrosystemsData I/O

ActelDevice

ActelDevice

D e s i g n C r e a t i o n / Ve r i f i c a t i o n

S y s t e m Ve r i f i c a t i o n

DesignView

Synplify

Des ign Too l s SiliconExplorerSerial Connection

18 C

hann

el

SX FPGATDITCKTMS

TDO

PRAPRB

Actel Corporation • 955 East Arques Avenue • Sunnyvale, California 94086 • USA Tel: 408.739.1010 • Fax: 408.739.1540 Actel Europe, Ltd. • Daneshill House, Lutyens Close • Basingstoke, Hampshire RG24 8AG • United KingdomTel: +44.(0)1256.305600 • Fax: +44.(0)1256.355420Actel Japan • EXOS Ebisu Building 4F • 1-24-14 Ebisu Shibuya-ku • Tokyo 150 • JapanTel: +81.(0)3.3445.7671 • Fax: +81.(0)3.3445.7668

©1999 Actel Corporation. All rights reserved. Actel and the Actel logo are trademarks of Actel Corporation. All other brand or product names are the property of their owners.

5 1 9 2 2 7 0 - 0 / 6 . 9 9

For more information about Actel’s products, call 1.888.99.ACTEL orvisit our Web site at http://www.actel.com

Part Number A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36

Capacity 2,000 4,000 9,000 16,000 24,000 36,000(Gates)

Mixed Voltage - - YES YES YES YES

PCI Compliant - - - - YES YES

Maximum I/O 57 69 104 140 176 202

Dedicated 147 273 348 624 954 1230Flip-Flops

Logic Modules 295 547 684 1232 1890 2438

Dual-Port - - - - - 2560SRAM Bits

M X F P G A F a m i l y S e l e c t o r G u i d e

Part Number A54SX08 A54SX16 A54SX16P A54SX32 A54SA72*

Capacity 8,000 16,000 16,000 32,000 72,000(Gates)

JTAG YES YES YES YES YES

PCI Compliant - - 33MHz, 66MHz - 33MHz, 66MHz

Maximum I/O 130 177 177 249 360

Dedicated 256 528 528 1080 2012Flip-Flops

Logic Modules 768 1452 1452 2880 6036

*Available Q3 1999

S X F P G A F a m i l y S e l e c t o r G u i d e

Core Speed Width

Target 33MHz (0 wait) 32-bit66MHz (0 wait) 64-bit

Target +DMA 33MHz (0 wait) 32-bit64-bit

Master 33MHz (0 wait) 32-bit64-bit

M X / S X P C I C o r e s