simulation, prototyping and verification of standards-based … · umts/cdma2000 zigbee nfc nfc. 9...
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1© 2015 The MathWorks, Inc.
Simulation, prototyping and
verification of standards-based
wireless communications
Colin McGuire, Neil MacEwen
2
Real Time LTE Cell Scanner with MATLAB and Simulink
3
PSS/SSSOff the air
data
MIB
Cell ID
Freq.
Offset
Radio
ARM
Set center
frequency
UDP
Send
UDP
Receive
Print out
Display
Visualize
Host
Cell
Info
FPGA
24 bit MIB
info
Real time LTE Frequency Scanner
4
From Design to Prototype
▪ A common design environment across multiple teams
– Systems Engineers, RF Engineers, Algorithm Developers, HDL Engineers
▪ Target off-the-shelf hardware for prototype development
5
From Design to Prototype
Behavioral Model
Fixed point Simulink
Systems Implementation
Verification on hardware
6
Modeling Wireless Standards
with MATLAB & SIMULINK
7
Baseband
precoding
DAC RF
NT
…
DAC RF
Baseband
combining
ADCRF
NR
…
ADCRF
Wireless Modeling ChallengesBaseband DSP development
• Is my implementation correct?
• How can I evaluate link performance with my
algorithm?
• 5G challenges, e.g. out of band emission..
Explore beamforming trade-offs
• Baseband, analogue or hybrid
beamforming?
• Simulate capabilities and limitations
• Trade-off ADCs vs RF components
Antenna array design and evaluation
• Element coupling
• Edge effects
• Imperfections
Investigate the impact of RF impairments
• Frequency dependency
• Non-linearities
• Mismatches and coupling
8
Modeling Wireless Standards with MATLAB & SIMULINK
LTE 5G WLAN
UMTS/cdma2000 ZigBee NFC
NFC
9
From Design to Prototype
Behavioral Model
Fixed point Simulink
Systems Implementation
Verification on hardware
Behavioral Model
Fixed point Simulink
Systems Implementation
Verification on hardware
How can I evaluate the
performance of my algorithm?
Is my implementation correct?
System simulation
Working with real signals
10
Demo: Modeling 802.11ad Beamforming
Generate
802.11ad
packet
Generate tx & rx
steering weights
for desired angle
4x4
MIMO
channel
Apply
tx
weights
Apply
rx
weights
Demodulate
& decode
packet1 4 4 1
WLAN System
Toolbox
Phased Array
System Toolbox
▪ Uniform linear array of 4 elements at transmitter and receiver
▪ MIMO channel with 6 scatterers
▪ PER and EVM for 802.11ad link
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Demo: Modeling 802.11ad Beamforming
12
Extending standards… LTE to 5G
PDSCH generation and
mapping
DL-SCH generation
waveform generation:
OFDM
LTE channel model
synchronizationchannel
estimationPDSCH
decodingDL-SCH
decodingOFDM
demodulation
PDSCH generation and
mapping
DL-SCH gen: Turbo, LDPC
Waveform gen:OFDM, F-OFDM
or W-OFDMvar. subcarrier spacing
channel model:CDL or TDL
synchronizationchannel
estimationPDSCH
decodingDL-SCH
decodingOFDM
demodulation
5G channel models
WOLA-OFDM, F-OFDM
W-OFDM, F-OFDMvar. subcarrier
spacingLDPC LDPC
13
Demo – Extending LTE for 5G link level simulation
14
From Design to Prototype
Behavioral Model
Fixed point Simulink
Systems Implementation
Verification on hardware
Behavioral Model
Fixed point Simulink
Systems Implementation
Verification on hardware
How can I evaluate the
performance of my algorithm?
Is my implementation correct?
Working with real signals
15
Working with Real Signals…
Beyond Simulation
LTELTE, WLAN, and
Communications
System Toolbox
LTELTE, WLAN, and
Communications
System Toolbox
16
Supported Hardware for Radio Connectivity
SDR
USRP, PLUTO, Zynq, …
Customizable RF front end
Sizable FPGA for targeting designs
Decreasing
Cost
SDR
Hardware
Support
Package
Signal Generator and Analyser
Keysight, R&S, NI, Tektronix, …
High quality RF front end
Wide frequency range, high bandwidth
Instrument
Control
Toolbox
Ultra low-cost SDR
RTL-SDR, …
Low bandwidth
Receive only
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Prototype with Real Signals
▪ SDR platforms can be used as low-cost RF interface
▪ Transmit repeat capability allows USRP E310 or Zynq
to be used as an RF signal generator
▪ Capture a burst of IQ and process in MATLAB
SDR PlatformHardware
support
package
IQ Waveform
Generation RF
SDR Platform Hardware
support
package
IQ Waveform
AnalysisRF
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Demo: SDR as a low-cost RF interface
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Demo: Generating WLAN Beacons
20
Demo: LTE Scanner
SDR MATLAB
&
LTE System
Toolbox™
21
Demo: LTE Cell Scanner
22
Simulink for Wireless System Design
23
From Design to Prototype
Behavioral Model
Fixed point Simulink
Systems Implementation
Verification on hardware
24
From Design To Hardware
MATLAB
✓ Large data sets
✓ Explore mathematics
✓ Data visualization
Targeting FPGA and ASIC
Streaming design
Implementation detail
Architectural specification
Verification
Simulink
✓ Parallel architectures
✓ Timing
✓ Data type propagation?
DESIGN
MATLAB
Coders
Synthesizable
VHDL / Verilog / C
Simulink
Verification
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Generate C and HDL Code and Implement On Hardware
SoC Reference Design
AX
IADC
DAC
ARMPlaceholder
For HDL
Algorithm IP
Define Custom Platform
Zynq platform with AD9361 RF card
ARM
Driver
Algorithm C
FPGA IP
Algorithm HDL
AXI interface
26
Verification: MATLAB reference model to FPGA implementation
27
Demo - Verify Turbo Decoder with LTE System Toolbox
lteTurboDecode
lteTurboEncode
HDL LTE Turbo
Decoder
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Demo: LTE Turbo Decoder
29
Verification via SDR Prototyping
Test and
Verification
MATLAB and Simulink
30
From Design to Prototype
Behavioral Model
Fixed point Simulink
HW/SW co-design
Verification on hardware
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Verification via SDR Prototyping
RF
Transceiver
Baseband
Processing
Test and
Verification
MATLAB and Simulink
Baseband
Processing
Test and
Verification
MATLAB and Simulink
Test and
Verification
MATLAB and Simulink
System ModelingRadio I/O
PrototypingStandalone
Implementation ready
model
32
PSS/SSSOff the air
data
MIB
Cell ID
Freq.
Offset
Radio
ARM
Set center
frequency
UDP
Send
UDP
Receive
Print out
Display
Visualize
Host
Cell
Info
FPGA
24 bit MIB
info
Real time LTE Frequency Scanner
33
Targeting an algorithm to the FPGA and ARM
Run on Programmable Logic
Run on ARM
Processing
System
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Simulink model Zynq board
ARM (PS) Fabric (PL)
User Logic
Interface model
HW/SW Co-Design Implementation of MIB Detector
Tx
LTE MIB
Detector
AXI
DMA
AXI
DMA
AD9361
HDL IP
AD
9361 R
F C
ard
Tx baseband I/Q
Rx baseband I/QRx DMA I/Q
RF Out
RF In
Tx DMA I/Q
AXI-
LiteMonitors
AD
9361
Tx B
lock
Constant /
Switch etc
Rx Data
Tx Data
Exte
rnal M
ode T
CP
/IP
Display /
Scope etc
Tune center frequency
Read MIB info
Send
decoded
cell info
over UDP
to host
Parameters
AD
9361
Rx B
lock
35
SoC Workflow: HW/SW Co-design
Algorithm
Modeling
Algorithm
Simulation
with test bench
Does the ref
design represent
the end platform?
Build a custom
reference
design
No
Algorithm design
Choose a
shipping ref
design in HSPs
Test on
hardware
system
Prototyping algorithm on
supported hardware system
SDR HSP
Zynq HSPs
Vision HSP
Yes
36
Generate C and HDL code and implement on hardware
SoC Reference Design
AX
IADC
DAC
ARMPlaceholder
For HDL
Algorithm IP
Define Custom Platform
Zynq platform with AD9361 RF card
ARM
Driver
Algorithm C
FPGA IP
Algorithm HDL
AXI interface
37
LTE Cell Scanner Example: Algorithm
• Model algorithm
• Generate FPGA bitstream
• SW interface model
• Run on hardware
Input selector
PSS/SSS, MIB
Output Registers
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LTE Cell Scanner Example: Generation
• Model algorithm
• Generate FPGA bitstream
• SW interface model
• Run on hardware
39
Targeting workflow
Setup reference
design
Generate HDL code
Generate Vivado project
Generate SW
models
Generate bitstream
Load bitstream
Configure SW model
Generate SW
application
Run on hardware
40
Video: Compile Model
41
Targeting workflow
Setup reference
design
Generate HDL code
Generate Vivado project
Generate SW
models
Generate bitstream
Load bitstream
Configure SW model
Generate SW
application
Run on hardware
42
Video: Setup reference design
43
Targeting workflow
Setup reference
design
Generate HDL code
Generate Vivado project
Generate SW
models
Generate bitstream
Load bitstream
Configure SW model
Generate SW
application
Run on hardware
44
Video: Generate HDL code
45
Targeting workflow
Setup reference
design
Generate HDL code
Generate Vivado project
Generate SW
models
Generate bitstream
Load bitstream
Configure SW model
Generate SW
application
Run on hardware
46
Video: Generate Vivado project and software models
47
Targeting workflow
Setup reference
design
Generate HDL code
Generate Vivado project
Generate SW
models
Generate bitstream
Load bitstream
Configure SW model
Generate SW
application
Run on hardware
48
Video: Generate bitstream
49
Targeting workflow
Setup reference
design
Generate HDL code
Generate Vivado project
Generate SW
models
Generate bitstream
Load bitstream
Configure SW model
Generate SW
application
Run on hardware
50
LTE Cell Scanner Example: Software
ARM Interface to SDR Receiver
FPGA Register
Interface
LTE Scan
Control
Send to
Host
Center Frequency
Reset receiver
Send results
to host over
Ethernet, for
display
CellID, PSS/MIB flags, frequency offset, MIB data
• Model algorithm
• Generate FPGA bitstream
• SW interface model
• Run on hardware
External mode tunability
51
Targeting workflow
Setup reference
design
Generate HDL code
Generate Vivado project
Generate SW
models
Generate bitstream
Load bitstream
Configure SW model
Generate SW
application
Run on hardware
52
Video: Run on hardware
53
Thank you!