simulation: definition, motivation -...
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SIMULATION Page 1
SIMULATION:DEFINITION, MOTIVATION
Simulation: to construct and test a computermodel of the circuit to be built.
* It is useful because the costs of simulation arefar less than the costs of fabricating the circuitdirectly.
* Simulation only models those aspects of thecircuit relevant to the level of abstractionconcerned.
* For VLSI circuits simulation is not a guaran-teed way of verification as it is impossible toenumerate all combinations of input patternsand internal states. However, simulation canincrease the belief in the correctness of thedesign.
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LEVELS OF SIMULATION
From the lowest level to higher levels:
* Device-level simulation:
+ used to test the effect of fabrication param-eters;
+ used by technologists, not by circuit orsystem designers.
* Circuit-level simulation (e.g. SPICE):+ analog;+ nodal/tableau equations;+ numerical integration;+ DC analysis.
* Timing-level simulation:
+ analog, but with simplifications (macro-models, look-up tables);
+ piecewise-linear methods.
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LEVELS OF SIMULATION(Continued)
* Switch-level simulation:+ transistors are modelled as bidirectional
switches;+ mainly digital;+ circuits extracted from mask patterns can
directly be simulated;+ see later for more details.
* Gate-level (or logic) simulation:+ ‘‘gate’’ mainly refers to elements to be
found in a component library (e.g. forstandard-cell design): NAND, NOR,MULTIPLEXER, D-FLIPFLOP, LATCH,etc.;
+ unidirectional signal flow;+ also used for ‘‘fault simulation’’ and ‘‘au-
tomatic test pattern generation’’;+ see later for more details.
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LEVELS OF SIMULATION(Continued)
* Register-transfer simulation:+ circuit is seen as registers to store the state
and combinational logic to compute thenext state (finite state machine model).
registers
comb. logic
* Behavioral-level simulation:+ description in high-level language, e.g.
VHDL (VHSIC Hardware DescriptionLanguage).
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LEVELS OF SIMULATION(Continued)
+ descriptions at different levels of abstrac-tions coexist within the same simulationenvironment;
+ critical parts of the design are described ata lower level than non-critical parts, whileit is inefficient or infeasible to model thewhole circuit at the level of the most criti-cal part;
+ it might be easier to test a subsystem withstimuli from the system itself, rather thandescribing the stimuli explicitly;
* Hardware-software cosimulation:
+ useful in hardware-software codesign;+ requires combination of multiple simula-
tion techniques.
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COMPONENTS OF ASIMULATOR
SIMULATOR KERNEL:* the routines for doing the ‘‘real’’ simulation.* detailed description for event-driven simula-
tion follows.
ROUTINES FOR PROCESSING OF CIRCUIT DESCRIPTION:
* input format: either written by the designer orobtained through an interface with a schemat-ic entry tool.
* internal format: machine code or tables.* input format has to be compiled into internal
format.
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COMPONENTS OF ASIMULATOR (Continued)
ROUTINES FOR STIMULI PROCESSING:* stimuli: the input patterns for all time instants
during the simulation.* they have to provide the kernel with the cor-
rect input patterns.
ROUTINES FOR OUTPUT PROCESSING:* the simulator results are numbers; they have
to be presented in a user-friendly form, e.g. astables or waveforms.
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GATE-LEVELSIMULATION
SIGNAL MODELING
Signal values are, of course, discrete. The mini-mum set consists of ’0’ , ’1’ and ’X’ . ’X’means ‘‘unknown’’.
GATE MODELING
* Gate models should deal with multiple-val-ued logic.
* Gate behavior can be represented by truthtables or compiled code.
in 1 in 2 out’0’ ’0’ ’1’’0’ ’1’ ’1’’0’ ’X’ ’1’’1’ ’0’ ’1’’1’ ’1’ ’0’’1’ ’X’ ’X’’X’ ’0’ ’1’’X’ ’1’ ’X’’X’ ’X’ ’X’
Nand-gate:
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GATE-LEVELSIMULATION
DELAY MODEL* inertial delay: a change to an input signal has
to last at least a certain time before it can trig-ger any reaction.
* propagation (or transport) delay: some timepasses between the start of a signal change atthe gate input and the start of a signal changeat its output.
* rise/fall delay: due to capacitances that haveto be loaded or unloaded, there is a time dif-ference between the moment an output startsto change and the moment the output hasreached its final value.
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DELAY MODEL EXAMPLE
in_1
in_2out
time’0’’1’
in_2’0’’1’
in_1
0 1 2 3 4 5 6 7 8 9
out
time’0’
0 1 2 3 4 5 6 7 8 9
out
time’0’’1’
0 1 2 3 4 5 6 7 8 9
Prop. delay = 2:
Rise delay = 2, fall delay = 3:
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COMPILER-DRIVENSIMULATION
* Based on making executable-code model ofcircuit;
* Efficient simulation mechanism (fewmachine instructions per gate);
* Applicable to few delay models in synchro-nous circuits (e.g. zero-delay model).
combinational logic
registers
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ZERO-DELAY EXAMPLE
A
BC
DE
F
n1n2n3
n4n5
n6
n7
n8
n9
n1 A;n2 B;n3 C;n4 D;n5 E;n6 OR(n1, n2);n7 AND(n4, n5);n8 AND(n6, n3);n9 OR(n7, n8);F n9;
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UNIT-DELAY SIMULATION* Provides some information on signal evolu-
tion in time, especially to detect glitches.time
’0’’1’’0’’1’
0 1 2 3 4n1
n2
n3
n4
n5
n6
n7
n8
n9
’0’’1’’0’’1’
’0’’1’’0’’1’
’0’’1’’0’’1’
’0’’1’
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UNIT-DELAY SIMULATION(Ctd.)
Two-array technique:
for (t tstart; t � tend; t t+ 1) fnew[1] A;new[2] B;new[3] C;new[4] D;new[5] E;new[6] OR(old[1], old[2]);new[7] AND(old[4], old[5]);new[8] AND(old[6], old[3]);new[9] OR(old[7], old[8]);F new[9];old new;g
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EVENT-DRIVENSIMULATION
* Event-driven simulation is a widely-usedmechanism in gate-level simulators.
* An event is a change of a signal value thatmay trigger new changes.
* There is a queue of events ordered by the timethe event is going to happen.
* Basic steps:+ the output of a gate G changes at time ti.
+ the fanout of the gate is inspected; it con-sists of the inputs of the gates Gk that areconnected to the output of gate G.
+ if the outputs of the gates Gk change, theyare scheduled to change at time ti � �k,where �k is the delay associated with thetransition.
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IMPLEMENTATION OFEVENT QUEUE
Naive implementation with a linked list:
ev1t1
ev2t1
ev1t2
ev3t2
Disadvantages:* inefficient use of computation time (search
for position where to insert new event);
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IMPLEMENTATION OFEVENT QUEUE
(Continued)
Better implementation: time wheel with n timeslots.
* only simultaneous events are in the samelinked list, except those events that are sched-uled more than n time units ahead.
tt � �
t � k�
t � (k� 1)�
t � n�
Time wheel implementation: array of linkedlists.
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SWITCH-LEVELSIMULATION
Basic points:* A circuit is modeled as a network of nodes in-
terconnected by transistors.* Signals have two components <s,v>:
+ strength (s): associated with impedance.Often the set of values is discrete.
+ level (v): associated with voltage. Possiblevalues are: ‘‘0’’, ‘‘1’’ and ‘‘X’’.
* There are two types of nodes:+ storage nodes: they have a capacitance
value. Often the set of values is discrete.+ input nodes: they act as sources of fixed
value and can supply unlimited current.* The transistors:
+ act as bidirectional switches;+ have a strength value (signals passing
through a transistor have their strength re-duced to this value).
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STRENGTH MODELS
BRYANT’S MODEL OF STRENGTH VALUES
* There are w distinct strength values: 1, 2, ...,k, ..., w.
* s = w � s is the strength of an input signal.* k < s < w � s is the strength of a transistor.* 1 �s � k � s is the strength of a storage
node.
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STRENGTH MODELEXAMPLES
n0(5)
(3)
Vdd
(3)
(4)
(4)
A
B
(a) (b) (c)
A
B
Vdd
A
B
(3)
(3)
(3)
A
B
(3)
(3)
�
Vdd
(3)
(3)
VssVss Vss
n1(1)
n2(1)
Out Out
Out
n1(1)
n1(2)
n2(1)
n2(1)
n3(1)
n0(5)
n0(5)
n3(5) n3(5) n4(5)
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NODE EVALUATION
HAYES’ #-OPERATOR* It combines several <s,v>-pairs ‘‘seen’’ by a
node to give one <s,v>-pair, the actual signalon the node.
* The signals with maximum s-values deter-mine the new s-value; the new v-value is ‘‘X’’unless all maximum signals are ‘‘0’’ or ‘‘1’’.
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SWITCH-LEVELSIMULATIONTECHNIQUES
Main principles:* partition the circuit into subcircuits that can
be seen as unidirectional elements. The inter-action between these subcircuits can be as ingate-level simulation.
* apply special methods to compute the‘‘steady-state’’ of the subcircuits modelled atthe switch level (similar to unit-delay simu-lation).
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CIRCUIT PARTITIONINGEXAMPLE
Vdd
Vss
Vss
Vdd