simulation and analysis of multilevel inverter with reduced number of switches

Proceedings of the International Conference on Emerging Trends in Engineering and Management (ICETEM14)

30-31, December, 2014, Ernakulam, India

21

SIMULATION AND ANALYSIS OF MULTILEVEL

INVERTER WITH REDUCED NUMBER OF SWITCHES

NIMITHA MURALEEDHARAN1, REMANI T

2

1EEE, Govt. Engineering College, Thrissur,

2Professor, EEE, Govt. Engineering College, Thrissur,

ABSTRACT

As compared to conventional two level inverters, multilevel inverters have been widely accepted for high-power

and high-voltage applications due to their added advantages of low switching stress and lower total harmonic distortion

(THD), hence reducing the size and bulk of the passive filters. In this paper a new five level inverter topology is

presented with reduced number of switches as compared to conventional cascaded H-bridge multilevel inverter, and can

be extended to any number of levels. The performance of the new topology and its controller are validated with

simulation results using the MATLAB/SIMULINK software.

Keywords: Multilevel inverter, SPWM, THD

1. INTRODUCTION

Among all the modern power converters, the voltage source inverter (VSI) is the simplest and most widely used

device with power ratings ranging from fractions of kilowatt to megawatt level. It converts fixed DC voltage to AC

voltage with controllable frequency and magnitude. To improve the efficiency, performance and reliability of the system,

most of the loads are connected to the AC power line through power converters. In recent years, the multilevel voltage

inverter has received wide attention in high-power applications such as large induction motor drives, UPS systems and

flexible AC transmission systems [1]-[8]. Multilevel inverter synthesizes a desired stepped output voltage from several

input DC voltage sources. With an increasing number of input DC sources, the inverter output voltage waveform

approaches nearly sinusoidal waveform. As compared to traditional two-level inverters, the multilevel inverters have

more advantages, which include lower semiconductor voltage stress, better harmonic performance, low electromagnetic

interference and lower switching losses. A multilevel inverter also enables the use of renewable energy sources.

Renewable energy sources such as photovoltaic, wind and fuel cells can be easily interfaced to a multilevel inverter

system for high power applications.

The three common topologies for multilevel inverter are: (i) Diode clamped [9] (ii) Flying capacitor and [10]

(iii) Cascaded H-bridge inverter. Among them, a cascaded H-bridge inverter is useful because it requires reduced number

of components to achieve the same number of output voltage levels among the conventional multilevel inverters [11]-

[15]. One of the disadvantages of multilevel inverter is the large number of power semiconductor switches required.

Every switch requires a gate driver circuit, therefore increasing the complexity and size of the overall circuit.

INTERNATIONAL JOURNAL OF ELECTRICAL ENGINEERING &

TECHNOLOGY (IJEET)

ISSN 0976 – 6545(Print) ISSN 0976 – 6553(Online) Volume 5, Issue 12, December (2014), pp. 21-31

© IAEME: www.iaeme.com/IJEET.asp Journal Impact Factor (2014): 6.8310 (Calculated by GISI) www.jifactor.com

IJEET

© I A E M E



22

This paper presents a new topology of cascaded multilevel inverter that produces the same output as the

conventional cascaded multilevel inverter for a given input but has fewer semiconductor switches and gate driver

circuits. Its performance is analysed using different sinusoidal PWM techniques [16]-[17]. The remaining paper is

organized as: Section 2 gives a brief explanation about the conventional cascaded multilevel inverter. Section 3 describes

the working and control algorithm of the new multilevel inverter topology. Section 4 presents the simulation results of

the conventional and the new cascaded multilevel inverter topology. Section 5 concludes the paper.

2. CASCADED MULTILEVEL INVERTER

This multilevel inverter uses set of series connected cascaded inverter with separate dc sources to synthesize a

desired voltage from several independent dc sources, which may be obtained from batteries, fuel cells, or solar cells. This

inverter can avoid extra clamping diodes or voltage balancing capacitors as in diode clamped multilevel inverters and

flying capacitor type multilevel inverters respectively. AC output of each of the inverter is connected in series such that

the synthesized voltage waveform is the sum of the inverter outputs. In this topology, the number of output phase voltage

levels is defined by m = 2s+1, where s is the number of dc sources.

Fig.1 shows a three level cascaded multilevel inverter. When switches S1 and S2 alone are conducting the output

of the inverter is Vdc, Fig.1.a. When switches S3 and S4 alone are conducting the output of the inverter is -Vdc, Fig.1.b.

When switches S1 and S3, are conducting, the output of the inverter is zero, Fig.1.c.

Fig.1. 3 level cascaded multilevel inverter

Fig.1.a. Switching combination required to generate output Fig.1.b. Switching combination required to generate output

voltage level +Vdc voltage level –Vdc



23

Fig.1.c. Switching combination required to generate output voltage level zero

3. NEW MULTILEVEL TOPOLOGY

3.1. Working

In order to reduce the overall number of switching devices in conventional cascaded multilevel inverter

topologies, a new topology has been presented. The circuit configuration of the new five level inverter is shown in Fig.2.

It has four main switches in H-bridge configuration S3, S4, S5 and S6 and two auxiliary switches S1 and S2. The number of

dc sources (two) is kept unchanged as in similar five level conventional cascaded H-bridge multilevel inverter. Like other

conventional multilevel inverter topologies, this topology can be extended to any required number of levels.

The inverter can operate in four different modes according to the polarity of the load voltage and current.

• When switch S1, S3, S6 is conducting, the output voltage is +Vdc.

• When switch S2, S3, S6 is conducting, the output voltage is +2Vdc.

• When switch S1, S5, S4 is conducting, the output voltage is –Vdc.

• When switch S2, S5, S4 is conducting the output voltage is -2Vdc.

Fig.2. 5 level inverter with reduced number of switches

Fig.2.a. Switching combination required to generate Fig.2.b. Switching combination required to generate

output voltage level +2Vdc output voltage level +Vdc



24

Fig.2.c. Switching combination required to generate

output voltage level -Vdc

Fig.2.d. Switching combination required to generate

output voltage level -2Vdc

Considering the load to be a RL load,

Powering Mode: This occurs when both the load current and voltage have the same polarity. In the positive

half cycle, when the output voltage is Vdc, the current path comprises; the lower supply, S1, S3, load, S6, and back to the

lower supply. When the output voltage is 2Vdc, current path is; the lower source, S2, the upper source, S3, load, S6, and

back to the lower source. In the negative half cycle, S3 and S6 are replaced by S4 and S5 respectively.

TABLE 1: Operating modes

Output Voltage Level Conducting Switches

+Vdc S1, S3, S6

+2Vdc S2, S3, S6

-Vdc S1, S5, S4

-2Vdc S2, S5, S4

Free-Wheeling Mode: Free-wheeling modes exist when one of the main switches is turned-off while the load current

needs to continue its path due to load inductance. This is achieved with the help of the anti-parallel diodes of the

switches, and the load circuit is disconnected from the source terminals. In this mode, the positive half cycle current path

comprises; S3, load, and D5 or load, S6 and D4, while in the negative half cycle the current path includes S5, load, and D3

or load, S4 and D6.

Regenerating Mode: In this mode, part of the energy stored in the load inductance is returned back to the source. This

happens during the intervals when the load current is negative during the positive half cycle and vice-versa. When the

output voltage is Vdc, the positive current path comprises; load, D5, D1, the lower source, and D4, while the negative

current path comprises; load, D3, D1, the lower source, and D6. When the output voltage is 2Vdc, the positive current path

comprises; load, D5, upper source, D2, lower source and D4, while the negative current path comprises; load, D3, upper

source, D2, the lower source, and D6.

3.2. Switching Techniques

A single sinusoidal reference is compared with each carrier signal to determine the output voltage for the

inverter. Three dispositions of the carrier signal are considered to generate the PWM signal.

3.2.1 Phase disposition (PD): In PDPWM Strategy for a m-level inverter, (m-1) carriers with the same frequency

and same amplitude are all in phase with each other. If the reference wave is more than a carrier signal, then the active

devices corresponding to that carrier are switched on. Otherwise, the devices switch off.

3.2.2 Alternative phase opposition disposition (APOD): In APOD strategy the carriers of same amplitude are phase

displaced from each other by 180 degrees alternatively.

3.2.3 Phase opposition disposition (POD): In POD strategy the carrier waveforms above the zero reference are in

phase. The carrier waveforms below zero reference are also in phase, but are 180 degrees phase shifted from those above.



25

(a)

(b)

©

Fig.3. Carrier and reference signal arrangements for: (a) Phase disposition (PD). (b) Alternative phase opposition

disposition (APOD). (c) Phase opposition disposition (POD).

TABLE 2: Comparison Of Number Of Components

Number Of Switches

Inverter Type 5 LEVEL 7 LEVEL 9 LEVEL 11 LEVEL

Cascaded H-Bridge 8 10 12 14

New Topology 6 7 8 9



26

Fig.4.a. Simulink model of conventional five level cascaded multilevel inverter

Fig.4.b. Simulink model of five level cascaded multilevel inverter with reduced number of switches

4. SIMULATION RESULTS

A conventional five level cascaded multilevel inverter is first simulated using the following parameters and the

simulink model is shown in Fig.4.a. Fig.4.c shows the output voltage of conventional five level cascaded multilevel

inverter.

i. Input voltage: 100V

ii. Switching frequency: 1KHz

iii. Modulation index: 0.8

iv. R load =100Ω

Simulation is done for the new five level multilevel inverter topology in MATLAB/SIMULINK using the

following parameters. The simulink model is shown in Fig.4.b. Fig.4.d and Fig.4.e shows the switching signals given to

the switches. Fig.4.f shows the output voltage.

i. Input voltage: 100V

ii. Switching frequency: 1KHz

iii. Modulation index: 0.8

iv. R load =100Ω



27

Fig.4.c. Output voltage of conventional five level cascaded multilevel inverter

Fig.4.d. Switching signals to the switches S1, S2

Fig.4.e. Switching signals to the switches S3, S4, S5, S6

Fig.4.f. Output voltage of the new multilevel inverter topology



28

Fig.4.g and Fig.4.h shows the output voltage and output current of the new multilevel inverter topology with

filter at the output. The filter parameters used are: C=22 µf and L= 30 mH. The FFT analysis of output voltage of the new

multilevel inverter topology with filter at the output is shown in Fig.4.i.

Fig.4.g. Output voltage of the new multilevel inverter with filter at the output

Fig.4.h. Output current of the new multilevel inverter with filter at the output

Fig.4.i. FFT analysis of output voltage with filter



29

Fig.4.j. Voltage across auxiliary switch of the conventional 5 level inverter

Fig.4.k. Voltage across auxiliary switch S1 of the new 5 level inverter

Fig.4.l. Voltage across auxiliary switch S2 of the new 5 level inverter

Fig.4.j shows the voltage across each auxiliary switch of the conventional 5 level cascaded inverter. Fig.4.k and

Fig.4.l shows the voltage across the auxiliary switches S1 and S2 of the new 5 level inverter topology.



30

TABLE 3: Comparison Of THD And Number Of Switches

5 Level Cascaded Multilevel Inverter Number Of Switches THD

Conventional Topology 8 26.52%

New Topology 6

24.58%(POD)

25.58%(APOD)

26.68%(PD)

5. CONCLUSION

In this paper, a new cascaded inverter topology has been presented which has superior features over

conventional cascaded multilevel inverter topologies in terms of the fewer power switches, control requirements, cost,

and reliability. Three different SPWM control methods are used to drive the inverter and their performance in terms of

THD is compared and its found that POD PWM strategy gives an output voltage with less THD as compared to other

PWM strategies. Simulation of the new five level inverter topology is done for an input of 100V in

MATLAB/SIMULINK and the results are shown.

.

REFERENCES

1. L. M. Tolbert and F. Z. Peng, “Multilevel converters as a utility interface for renewable energy systems”, in Proc.

IEEE Power Eng. Soc. Summer Meeting, 2000, vol. 2, pp. 1271–1274.

2. L. G. Franquelo, J. Rodriguez, J. I. Leon, S. Kouro, R. Portillo, and M. A. M. Prats, “The age of multilevel

converters arrives”, IEEE Ind. Electron. Mag., vol. 2, no. 2, pp. 28–39, Jun. 2008.

3. Leon M. Tolbert, Fang Zheng Peng and Thomas G. Habetler, “Multilevel Converters for Large Electric Drives”,

IEEE Trans. Industry Applications, vol. 35, no. 1, Jan/Feb 1999.

4. Madhav D. Manjrekar, Peter K. Steimer and Thomas A. Lipo, “Hybrid Multilevel Power Conversion System: A

Competitive Solution for High-Power Applications”, IEEE Trans. Industry Applications, vol. 36, no. 3, May/June

2000.

5. Samir Kouro, Mariusz Malinowski, K. Gopakumar, Josep Pou, Leopoldo G. Franquelo, Bin Wu, Jose Rodriguez,

Marcelo A. Pérez, and Jose I. Leon, “Recent Advances and Industrial Applications of Multilevel Converters”, IEEE

Trans. Industrial Electronics, vol. 57, no. 8, August 2010.

6. Jose Rodriguez, Leopoldo G. Franquelo, Samir Kouro, Jose I. Leon, Ramon C. Portillo Ma Angeles Martin Prats,

Marcelo A. Perez “Multilevel converters: an enabling technology for high-power applications”, Proceedings of the

IEEE Vol.97, No.11, November 2009.

7. Fang Zheng, Peng, Jih-Sheng Lai, and Rodriguez J, “Multilevel inverters: a survey of topologies, controls, and

applications”, IEEE Transactions, Vol. 49, issue 4, pp. 724-738.

8. Ehsan Najafi, Abdul Halim Mohamed Yatim, “Design and Implementation of a New Multilevel Inverter Topology“,

IEEE Transactions on Industrial Electronics, vol. 59, no. 11, November 2012.

9. Mario Marchesoni and Pierluigi Tenca, “Diode-Clamped Multilevel Converters: A Practicable Way to Balance DC-

Link Voltages”, IEEE Trans. Industrial Electronics, vol. 49, no. 4, August 2002.

10. Sadigh A K, Dargahi V, Abarzadeh, M, Dargahi, S, "Reduced DC voltage source flying capacitor multicell

multilevel inverter: analysis and implementation," Power Electronics, IET , vol.7, no.2, pp.439,450, February 2014

11. F. Z. Peng, J. S. Lai, J. W. McKeever and J. VanCoevering, “A multilevel voltage- source inverter with separate dc

sources for static var generation”, IEEE Trans. Ind. Applications, vol. 32, pp. 1130–1138,Sept./Oct. 1996.

12. Mariusz Malinowski, K. Gopakumar, Jose Rodriguez and Marcelo A. Perez “A Survey on Cascade Multilevel

inverters”, IEEE Trans. Ind. Electron. , vol. 57, no. 7, July 2010.

13. Z. Du, L. M. Tolbert, J. N. Chiasson, and B. Ozpineci, “A cascade multilevel inverter using a single DC source”, in

Proc. 21st Annu. IEEE APEC, Mar. 19–23, 2006, pp. 426–430.

14. M. Farhadi Kangarlu and E. Babaei, “A generalized cascaded multilevel inverter using series connection of sub-

multilevel inverters”, IEEE Trans. Power Electron., vol. 28, no. 2, pp. 625-636, Feb. 2013.

15. Yun XU, Yunping ZOU, Xiong LIU, Yingjie He, “A Novel Composite Cascade Multilevel Converter”, The 33rd

Annual Conference of the IEEE Industrial Electronics Society (IECON),Nov. 5-8, 2007, Taipei, Taiwan.

16. Brendan Pete McGrath, Donald Grahame Holmes, “Multicarrier PWM Strategies for Multilevel Inverters,” IEEE

Trans. Ind. Electronics, vol. 49, no. 4, Aug 2002.



31

17. G. Carrara, S. Gardella, M. Marchesoni, R. Salutari, and G. Sciutto B, “A new multilevel PWM method: A

theoretical analysis”, IEEE Trans. Power Electron. , vol. 7, pp. 497–505, Jul. 1992.

18. Rajasekharachari K, K.Shalini, Kumar .K and S.R.Divya, “Advanced Five Level - Five Phase Cascaded Multilevel

Inverter With Svpwm Algorithm” International Journal of Electrical Engineering & Technology (IJEET), Volume 4,

Issue 4, 2013, pp. 144 - 158, ISSN Print : 0976-6545, ISSN Online: 0976-6553.

19. B.Kiran Kumar, Y.V.Sivareddy and M.Vijayakumar, “Comparative Analysis of Sine Triangle and Space Vector

Pwm For Cascaded Multilevel Inverters” International Journal of Engineering & Technology (IJEET), Volume 4,

Issue 2, 2013, pp. 155 - 164, ISSN Print : 0976-6545, ISSN Online: 0976-6553.

20. S. Nagaraja Rao, D.V. Ashok Kumar and Ch. Sai Babu, “PWM Control Strategies For Multilevel Inverters Based on

Carrier Redistribution Technique” International Journal of Engineering & Technology (IJEET), Volume 5, Issue 8,

2014, pp. 119 - 131, ISSN Print : 0976-6545, ISSN Online: 0976-6553.

simulation and analysis of multilevel inverter with reduced number of switches

Technology

multilevel voltage inverter

multilevel inverter

ac voltage

voltage source inverter

level inverter topology

cascaded hbridge inverter

highvoltage applications

input dc voltage sources