signetics saf1032p/1039p r/c receiver; r/c transmitter · 12 try3 keyboard input 13 try2 keyboard...

Signetics

Linear Products

DESCRIPTIONThe SAF1032P (receiver/decoder) and the SAF1039P (transmitter) form the basic parts of a sophisticated remote control system (PCM: pulse code modulation) for infrared operation.

Inputs and outputs are protected against electrostatic effects in a wide variety of device-handling situations. However, to be totally safe, it is desirable to take handling precautions into account.FEATURESSAF1032P Receiver/Decoder:• 16 program selection codes• Automatic preset to standby at

power 'ON', including automatic analog base settings to 50% and automatic preset of program selection '1' code

• 3 analog function controls, each with 63 steps

• Single supply voltage• Protection against corrupt codes

SAF1039P Transmitter:• 32 different control commands• Static keyboard matrix• Current drains from battery only

during key closure time• Two transmission modes

selectable

APPLICATIONS• TV• Audio• Industrial equipment

SAF1032P/1039PR/C Receiver; R/C TransmitterProduct Specification

PIN CONFIGURATIONSSAF1032P N Package

L 3 0 T [T m Voo

L 2 0 T |T 17] S E L A

L 1 0 T (T 16] S E L B

BIND |T j l ] S E L C

BINC (T TfQ S E L D

BIN B [T 13] o s a

B IN A [ 7 i f ] MAIN

T V O T [T TT] D ATA

vss U TOj H O L D

T O P VIEWCD11270S

PINNO. SYMBOL DESCRIPTION

1 L 3 0 T Linear ouput2 L2 0 T Linear ou tpu t3 L 1 0 T Linear output4 BIND Binary 8 output5 BINC Binary 4 output6 BINB Binary 2 output7 BINA Binary 1 output8 TVOT O n /o ff inp u t/o u tp u t9

10VssHOLD C ontrol input

11 DATA Data input12 MAIN Reset input13 OSCI C lock input14 SELD Binary 8 output15 SELC Binary 4 output16 SELB B inary 2 ou tput17 SELA Binary 1 output18 v DD

SAF1039P N Package

TRXO [T H VDD

TRX1 | T lU TRYO

TRX2 | T i f ] TRY1

T R X 3 [T 73]TRY2

TRDT [ 7 TU TRY3

TINH [ T TT] TRSL

TROS [ 7 10] TR02

V s s | T T ] t r o i

TOP VIEWCD11260S

PINNO. SYMBOL DESCRIPTION

1 TRXO Keyboard input2 TRX1 Keyboard input3 TRX2 Keyboard input4 TRX3 Keyboard input5 TRDT Data input6 TINH Inhibit ou tp u t/m o d e se lect input7 TROS O scilla tor output8 Vss9 TR 01 O scilla tor contro l input

10 T R 0 2 O scilla tor contro l input11 TRSL Keyboard se lect line12 TRY3 Keyboard input13 TRY2 Keyboard input14 TRY1 Keyboard input15 TRYO Keyboard input16 Vdd

ORDERING INFORMATIONDESCRIPTION TEMPERATURE RANGE ORDER CODE

18-Pin Plastic DIP (SOT-102A) -40°C to +85°C SAF1032PN

16-Pin Plastic DIP (SOT-38Z) -40°C to +85°C SAF1039PN

November 14, 1986 5-3 853-0954 86560

Signetics Linear Products Product Specification

R/C Receiver; R/C Transmitter SAF1032P/1039P

ABSOLUTE MAXIMUM RATINGSSYMBOL PARAMETER RATING UNIT

Vdd - vss Supply voltage range -0.5 to 11 V

Vi Input voltage 11 V

±l| Current into any terminal 10 mA

Po Power dissipation (per output) 50 mW

P t o t Power dissipation (per package) 200 mW

T aOperating ambient temperature range -40 to +85 °C

T s t g Storage temperature range -65 to +150 °C

DC ELECTRICAL CHARACTERISTICS Ta = 0 to + 85°C, unless otherwise specified.

SYMBOL PARAMETER Vdd(V)

Ta(°C)

SAF1039UNIT

Min Typ Max

Vdd Recommended supply voltage 7 10 V

Supply current

•d d Quiescent 107

2565 1

1050

juAMA

Id d

Operating; TR01 at Vss: outputs unloaded;One keyboard switch closed 10

10All25 0.8 1.7

< <

E E

Inputs1

V|HV|Ll|

TR02; TINH2 Input voltage HIGH Input voltage LOW Input current

7 to 10 7 to 10

10

AllAll25

0.8Vqd0

10“ 5

Vdd0.2Vdd

1 ><

<

Outputs

->OH

>OL

TRDT; TROS; TR01 Output current HIGH at V0H = VDD -0.5V Output current LOW at V0L = 0.4V

7

7

All

All

0.4

0.4

<

<

£ E

lO L

TRDT output leakage current when disabled vo = Vss to Vdd 10 25 1 /iA

>OL

TINHOutput current LOW Vql = 0.4V 7 All 0.4 mA

Oscillator

fosc Maximum oscillator frequency 120 kHzAf Frequency variation with supply voltage,

Temperature and spread of IC properties at f [ \ jo M = 36kHz3

7 to 10 All 0.15fNOM kHz

lose Oscillator current drain at fN O M “ 36kHz

10 25 1.3 2.5 mA

November 14, 1986 5-4



DC ELECTRICAL CHARACTERISTICS TA = 0 to + 85°C, unless otherwise specified.

SYMBOL PARAMETER Vdd(V)

Ta<°C)

SAF1032UNIT

Min Typ Max

V dd Recommended supply voltage 8 10 VSupply current

Idd Quiescent 1010

2585 1 50

300PApA

•dd Operating; lo = 0;at OSCI frequency of 100kHz 10 All 1 mA

Inputs

V|HV|L

DATA; OSCI, HOLD; TVOT4 Input voltage HIGH Input voltage LOW

8 to 10 8 to 10

AllAll

0.7Vdd0

Vdd0.2Vdd

VV

_ Q

MAIN; tripping levels Input voltage increasing Input voltage decreasing

5 to 10 5 to 10

AllAll o

o L». £3=

o a 0.9VDD

0.6Vdd V

ll Input current; all inputs except TVOT 10 25 10~5 1 juA

tR, tF Input signal rise and fall times (10% and 90% VDD) all inputs except MAIN

8 to 10 All 5 US

Outputs

lOL•OL

Program selection: BINA/B/C/D Auxiliary: SELA/B/C/D Analog: L30T; L20T; L10T TVOT4 All open-drain n-channel

output current LOW at Vol = 0.4V output leakage current at Vq = Vss to Vdd

810

AllAll

1.610

mAma

NOTES:1. The keyboard inputs (TRX, TRY, TRSL) are not voltage driven (see Application Information Diagram, Figure 5).

If one key is depressed, the circuit generates the corresponding code. The number of keys depressed at a time, and this being recognized by the circuit as an illegal operation, depends on the supply voltage Vdd and the leakage current (between device and printed circuit board) externally applied to the keyboard inputs. If no leakage is assumed, the circuit recognizes an operation as illegal for any number of keys > 1 depressed at the same time with Vdd = 7V. At a leakage due to a 1MS2 resistor connected to each keyboard input and returned to either Vdd or Vss. the circuit recognizes at least 2 keys depressed at a time with Vdd = 7V. The highest permissible values of the contact series resistance of the keyboard switches is 500£1

2. Inhibit output transistor disabled.3. A f is the width of the distribution curve at 2a points (a = standard deviation).4. Terminal TVOT is input for manual ON. When applying a LOW level TVOT becomes an output carrying a LOW level.

November 14, 1986 5-5



BLOCK DIAGRAM OF SAF1039P TRANSMITTER

VDD TR01 TR02 TROS VSSBD07620S

FORMAT 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bo 1 B! 1 B2 1 B3 1 B4 1 0 0 0 0 0 0

Im uuum niiim nniuui m°D[,a™ _______mi_______ nn_______nn_______n

/-BURST OF 26 / OSCILLATOR PERIODS

■ a II II II 1

iin n ju u u u iiin iin iin iiivll;;ll!;ll;;lliill!!n

m m i;i!iy KEY DOWN

t in h "

w ^ DATA DITO _ .... _ w

ONE DATA WORD

32 x t0

NOTES:1. To = 1 c lock period = 128 osc illa to r periods.2. fT in kHz.

Figure 1. Pattern for Da

= 32 x — ms<2) ** ft

WF18070S

ta to be Transmitted

OPERATING PRINCIPLESThe data to be transmitted are arranged as serial information with a fixed pattern (see Figure 1), in which the data bit locations B0 to B4 represent the generated key command code. To cope with IR (infrared) interferences of other sources, a selective data transmission is present. Each transmitted bit has a burst of 26 oscillator periods.

Before any operation will be executed in the receiver/decoder chip, the transmitted data must be accepted twice in sequence. This means the start code must be recognized each time a data word is applied and comparison must be true between the data bits of two successively received data words. If both requirements are met, one group of binary output buffers will be loaded with a code defined by the stored data bits, and an internal operation can also take place (See operating code table).

The contents of the 3 analog function registers are available on the three outputs in a pulse code versus time modulation format after D-to-A (digital-to-analog) conversion. The proper analog levels can be obtained by using simple integrated networks. For local control a second transmitter chip (SAF1039P) is used (see Figure 4).

TIMING CONSIDERATIONSThe transmitter and receiver operate at different oscillator frequencies. Due to the design neither frequency is very critical, but correlation between them must exist. Calculation of these timing requirements shows the following.

With a tolerance of ±10% on the oscillator frequency (fj) of the transmitter, the receiver oscillator frequency (fR = 3 X fj) must be kept constant with a tolerance of ±20%.

On the other hand, the data pulse generated by the pulse stretcher circuit (at the receiver side) may vary ±25% in duration.

GENERAL DESCRIPTION OF THE SAF1039P TRANSMITTERAny keyboard activity on the inputs TRXO to TRX3, TRYO to TRY3 and TRSL will be

detected. For a legal key depression, one key down at a time (one TRX and TRY input activated), the oscillator starts running and a data word, as shown above, is generated and supplied to the output TRDT. If none, or more than 2 inputs are activated at the same time, the input detection logic of the chip will generate an overall reset and the oscillator stops running (no legal key operation).

This means that for each key-bounce the logic will be reset, and by releasing a key the transmitted data are stopped at once.

November 14, 1986 5-6



OPERATION MODEMODE DATA FUNCTION OF TINH

12

Unmodulated: LOCAL operation Modulated: REMOTE control

Output, external pull-up resistor to Vqd Input, connected to Vss

The minimum key contact time required is the duration of two data words. The on-chip oscillator is frequency-controlled with the external components R1 and C1 (see circuit Figure 3); the addition of resistor R2 means that the oscillator frequency is virtually independent of supply voltage variations. A complete data word is arranged as shown in Figure 1, and has a length of 32 X T0ms, where Tq = 27/f j.

GENERAL DESCRIPTION OF THE SAF1032P RECEIVER/ DECODERThe logic circuitry of the receiver/decoder chip is divided into four main parts as shown in the Block Diagram.

Part IThis part decodes the applied DATA information into logic '1' and 'O'. It also recognizes

the start code and compares the stored data bits with the new data bits accepted.

Part IIThis part stores the program selection code in the output group (BINF) and memorizes it for condition HOLD = LOW.

It puts the functional code to output group (SELF) during data accept time, and decodes the internally-used analog commands (AIM-DEC).

BLOCK DIAGRAM OF SAF1032P RECEIVER/DECODER

< m o a < o o q1 1 1 1 d u u um m m a > co a> <o </>

BD07630S

November 14, 1986 5-7



Part IIIThis part controls the analog function registers (each 6 bits long), and connects the contents of the three registers to the analog outputs by means of D/A conversion. During sound mute, output L10T will be forced to HIGH level.

Part IVThis part keeps track of correct power 'ON' operation, and puts chip in 'standby' condition at supply voltage interruptions.

The logic design is dynamic and synchronous with the clock frequency (OSCI), while the required control timing signals are derived from the bit counter (BITC).

OperationSerial information applied to the DATA input will be translated into logic '1' and 'O' by means of a time ratio detector.

After recognizing the start code (CSTO) of the data word, the data bits will be loaded into the data shift register (SRDT). At the first trailing edge of the following data word, a comparison (KOM) takes place between the contents of SRDT and the buffer register (BFR). If SRDT equals BFR, the required operation will be executed under control of the comparator counter (COMP).

As shown in the operating code table on the next page, the 4-bit wide binary output buffer (BINF) will be loaded for BFRO = 'O', while for BFR0 = '1' the binary output buffer (SELF), also 4-bits wide, will be activated during the data accept time.

At the same time operations involving the internal commands are executed. The contents of the analog function registers (each 6 bits long) are controlled over 63 steps, with minimum and maximum detection, while the D/A conversion results in a pulsed output

signal with a conversion period of 384 clock periods (see Figure 2).

First power ON will always put the chip in the standby position. This results in an internal clearing of all logic circuitry and a 50% presetting of the contents of the analog registers (analog base value). The program selection 'T code will also be prepared and all the outputs will be nonactive (see operating output code table).

From standby, the chip can be made operational via a program selection command, generated LOCAL or via REMOTE, or directly by forcing the TV ON/OFF output (TVOT) to zero for at least 2 clock periods of the oscillator frequency.

For POWER-ON RESET, a negative-going pulse should be applied to input MAIN, when Vdd Is stabilized and pulse width LOW > 100/xs.

ANALOG OUTPUT

(50% CONTENTS)

H h 6 CLOCK PERIODS

-384 CLOCK PERIODS-

Figure 2. Analog Output Pulses

November 14, 1986 5-8



OPERATING CODE TABLE

K E Y -M A TR IXP O S ITIO N

B U F FE RBFR

BINF(B IN .)

S E L F(S E L .) F U N C T IO N

TR X . TR Y . T R S L 0 1 2 3 4 A B c D A B c D

0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 10 1 0 0 0 0 1 0 1 0 0 0 1 1 1 10 2 0 0 0 1 0 0 0 1 0 0 1 1 1 10 3 0 0 0 0 0 0 1 1 0 0 1 1 1 1 Program1 0 0 0 1 1 1 0 0 0 1 0 1 1 1 1 ■ Select + ON1 1 0 0 1 0 1 0 1 0 1 0 1 1 1 11 2 0 0 1 1 0 0 0 1 1 0 1 1 1 11 3 0 0 1 0 0 0 1 1 1 0 1 1 1 1

2 0 0 0 0 1 1 1 0 0 0 1 1 1 1 12 1 0 0 0 0 1 1 1 0 0 1 1 1 1 12 2 0 0 0 1 0 1 0 1 0 1 1 1 1 12 3 0 0 0 0 0 1 1 1 0 1 1 1 1 1 Program3 0 0 0 1 1 1 1 0 0 1 1 1 1 1 1 ’ Select + ON3 1 0 0 1 0 1 1 1 0 1 1 1 1 1 13 2 0 0 1 1 0 1 0 1 1 1 1 1 1 13 3 0 0 1 0 0 1 1 1 1 1 1 1 1 1

0 0 1 1 0 1 1 0 X X X X 0 1 1 1 Analog base0 1 1 1 0 0 1 0 X X X X 0 0 1 1 Reg. (LIN3) + 10 2 1 1 0 1 0 0 X X X X 0 1 0 1 Reg. (LIN2) + 10 3 1 1 0 0 0 0 X X X X 0 0 0 1 Reg. (LIN1) + 11 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 OFF1 1 1 1 1 0 1 0 X X X X 1 0 1 1 Reg. (LIN3) -11 2 1 1 1 1 0 0 X X X X 1 1 0 1 Reg. (LIN2) -11 3 1 1 1 0 0 0 X X X X 1 0 0 1 Reg. (LIN1) -1

2 0 1 1 0 1 1 1 X X X X 0 1 1 0 Mute (set/reset)2 1 1 1 0 0 1 1 X X X X 0 0 1 02 2 1 1 0 1 0 1 X X X X 0 1 0 02 3 1 1 0 0 0 1 X X X X 0 0 0 03 0 1 1 1 1 1 1 X X X X 1 1 1 0 • Spare functions3 1 1 1 1 0 1 1 X X X X 1 0 1 03 2 1 1 1 1 0 1 X X X X 1 1 0 03 3 1 1 1 0 0 1 X X X X 1 0 0 0

NOTE:Reset mute also on program select codes, (LIN1) ±1, and analog base.

OPERATING OUTPUT CODE

(BIN.) (SEL.) (L.OT)TVOT

A B c D A B c D 1 2 3

Standby OFF via remote 0 0 0 0 0 0 0 0 1 0 0 1ON — 'not hold' condition 1 1 1 1 1 1 1 1 X X X 0non-operating ON — 'hold' condition

1 I

X 1 1 1 1X X X X X X 0non-operating

November 14, 1986 5-9



Figure 3. Interconnection Diagram of Transmitter Circuit SAF1039P in a Remote Control System for a Television Receiver With 12 Programs

November 14, 1986 5-10



November 14, 1986 5-11



TC14020S

Figure 5. Additional Circuits from Outputs L10T(1), L20T(2), L30T(3) and TVOT(4) of the SAF1032P in Circuit of Figure 4

November 14, 1986 5-12

signetics saf1032p/1039p r/c receiver; r/c transmitter · 12 try3 keyboard input 13 try2 keyboard...

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