Page 1 of 3

SIDDHARTH SHARMA Design Verification Engineer

Mob :- 7795191034 Email :- siddharth5722@gmail.com

Objective

To obtain an ASIC/SOC Verification Engineer position that will utilize my skills and experience in engineering and provide me opportunity to grow and learn.

Experience Summary

Over all experience of 3.5+ year in ASIC verification:

Currently working in ARM Embedded Technology as Design Engineer (Design Verification).

Worked at Synapse Techno Design as Project Engineer (Design Verification).

Worked at Lattice Semiconductor International Corporation as Trainee Eng.

Completed Diploma in VLSI (design & Verification) from CDAC ACTS, Pune.

Worked for Analog Devices in UVM based verification from scratch for two of their chips, as a Synapse Contractor.

Worked for Texas instruments on a Hard Disk controller UVM verification, as a Synapse Contractor.

Writing a Paper on "Novel approach for advanced UVM RAL integration".

Participated in SNUG (Synopsys Users Group India) and demonstrate a power saving strategy on Lattice CPLD.

Good knowledge of System Verilog with UVM. Sound knowledge of Digital logic Design Concepts. Worked on various interfacing protocols like: AXI 3, AXI4, AHB, APB, SPI, UART,I2C.

Honors/Certifications

CDAC Diploma in VLSI Design. Attended SNUG (Synopsys Users Group) as Lattice exhibitor and demonstrated a design on

CPLD. Participated in many ROBOTICS workshops and also won ROBOTICS competitions like Line

Follower Racing, ROBO Racing. Participated and won in many junkyard competition, implemented Heartbeat Counter by using

electronic components like LED, LDR, transistors and diodes from junk. Captain of my school’s cricket team.

Page 2 of 3

Project Summary

Industrial Project:

Project- 1: Testchips for GF and TSMC Foundry– in ARM (Verification) Description: Testchip contains Memories (single port and dual port SRAM and ROM), Standard Cells, IOs, Level Shifter and Retention Cells and Delay Chains. Role and Responsibility:

a) Testchip architecture improvement for advance memory features.b) Functional Verification of Testchips.c) Setup/Hold and access time measurement.

----------------------------------------------------------------------------------------------------------------------------------------

Project- 2: 3-axis accelerometer and thermometer – For Analog Devices (UVM Verification from scratch) Description: It is an ASIC which takes input from temperature and acceleration sensors then processed on input data & finally give output data with interrupts to host. Role and Responsibility:

d) Prepared VPlan for assigned modules using EPlanner from Cadence.e) Integrated advanced RAL with project environment which can support SPI/I2C burst operation

and Error Injection and many other features.f) Verification of NVM (Non-volatile memory)/OTP (One Time Programmable).g) Verification of sub-modules like SPI, I2C, CSR, Activity detection.h) Checker implementation for verifying various scenarios.i) Coverage item creation and monitoring.

-----------------------------------------------------------------------------------------------------------------------------

Project- 3: A Hard disk controller- For Texas Instruments (UVM Verification) Description: It is a Hard disk controller which will control spindle, arm motion, retract and other parts of Hard disk. Role and Responsibility:

a) Prepared VPlan for assigned modules.b) Verified a block by writing checkers and testcases.c) Wrote a PERL Script to automatically generate connectivity checker by reading RTL files.d) Wrote assertions to check various state machines.e) Coverage item identification and monitoring.f) Achieved 100% coverage for given modules.

----------------------------------------------------------------------------------------------------------------------------------------

Project- 4: AXI 4 verification IP in UVM.Role and Responsibility: Developed AXI 4 slave environment (Sequencer, Sequence Item, Driver, Agent).-----------------------------------------------------------------------------------------------------------------------------

Page 3 of 3

Project- 5: Verification of AXI to AHB Bridge in UVM. Role and Responsibility: Developed AHB slave environment & AXI monitor.----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------Academic Projects:

Project-1: Computer Controlled Robot by MATLABDescription: The main aim of this project is to control a Robot wirelessly by computer. It can be used as a spy robot, in defense and in various industries. Role and responsibility :

Developed algorithm and implemented MATLAB code to interface with the robot. Worked on the placement and connections between various ICs and designed PCB layout. Design power supply circuit

------------------------------------------------------------------------------------------------------------------------------

Project-2: Automatic fan controllerDescription: Automatic fan controller controls the fan by sensing the temperature of environment. Used in CPU and also in industries. Role and responsibility: Developed logic and block diagram for project, prepared layout for PCB and mounted all electronics component and troubleshooting of circuit.------------------------------------------------------------------------------------------------------------------------------

Skill Set

Programming Languages: C, C++ Scripting Languages: Perl Simulators: VCS, Verdi, NC-SIM, ModelSIM and QuestaSIM Synthesis: Synplify pro FPGA tools: Lattice Diamond 2.0 ,ISE integrated tool suite, Synplify pro HDL: Verilog & Vhdl HVL: System Verilog, SystemC Protocol: AXI3/4,AHB3,APB,I2C,SPI Methodology UVM Coverage: NCVerilog (ICCR), IMC Operating Systems: UNIX, Linux and Windows Processors: 8085/86, 8051 FPGA: Lattice ECP3,Xilinx Spartan-3 family CPLD Latice MachXO2 Testing: Experience with logic analyzers

Education

Course University Marks (%) YearPG Diploma in VLSI CDAC ACTS, Pune 70 2012B.E Electronics & Communications RGTU, Bhopal 68 2011HSC M.P. Board 84 2007SSC M.P. Board 84 2005