sherlock 4.0 and printed circuit...
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9000 Virginia Manor Rd Ste 290, Beltsville MD 20705 | 301-474-0607 | www.dfrsolutions.com
Sherlock 4.0 and
Printed Circuit Boards
DfR Solutions – January 22, 2015
Presented by:
Dr. Nathan Blattau – Senior Vice President
Who is DfR Solutions?
The Industry Leader in
Quality-Reliability-Durability
of Electronics 50 Fastest Growing Companies in the Electronics Industry - Inc Magazine
2012 Global Technology Award Winner
Best Design Verification Tool - Printed Circuit Design
9000 Virginia Manor Rd Ste 290, Beltsville MD 20705 | 301-474-0607 | www.dfrsolutions.com
™
PCB
Sherlock
4.0
• Printed Circuit Boards (PCB), also known as
– Printed Wiring Boards (PWB)
– Circuit Cards, etc..
• Provides mechanical support and electrical
interconnects to the electronic components
• Basic Materials
– Conductors
– Dielectric or insulator
– Structural reinforcement
• Woven glass cloth
• Fibers
• Must be able to provide the necessary:
– Electrical performance
– Structural performance
– Survive manufacturing
• Composite material
– Reinforcement (glass cloth)
– Polymer (resin)
– Copper
Printed Circuit Board
copper
Glass fibers
polymer
• PCB laminates (and prepregs) are fabricated with a variety of glass styles
• Problem: All datasheet properties are for laminate with 7628 glass style – Most laminate (and prepreg) in complex
PCBs have a low volume fraction of glass (i.e., 1080 or 106)
Glass Style Glass Style
Resin Volume Content
Fiber Volume Content
1027 0.86 0.14
1037 0.86 0.14
106 0.84 0.16
1067 0.84 0.16
1035 0.83 0.17
1078 0.82 0.18
1080 0.79 0.21
2313 0.74 0.26
2116 0.71 0.29
3313 0.71 0.29
3070 0.68 0.32
1647 0.66 0.34
1651 0.66 0.34
2165 0.66 0.34
2157 0.66 0.34
7628 0.64 0.36
• Thickness specified as a weight:
– Weight rolled out over a square foot, determines the thickness
– Thickness (mils) = Copper weight (oz) * 1.37
• 0.5 oz copper = 0.685 mils, 17.4 µm
• 1 oz copper = 1.37 mils, 34.8 µm
• 2 oz copper = 2.74 mils, 69.6 µm
• 3 oz copper = 4.11 mils, 104.4 µm
• During manufacturing of the copper layer starts out as
complete and is etched away to define the interconnects
Copper
• Two types of resins (not including composition) are
used:
– Pre-preg – partially cured resin that flows and fills in all the
etched away copper features, cures during the pressing
process, does not have copper on it
– Laminate – fully cured resin that typically has copper foil
already attached to it
• There are many different types of resin systems
– Dicy
– Phenolic, etc..
Resin
• Historically, two material properties of concern – Out-of-plane coefficient of thermal expansion (CTEz)
– Out-of-plane elastic modulus (‘stiffness’)(Ez)
– These drive fatigue of the plated through holes
• Key Assumption: No exposure to temperatures above the glass transition temperature (Tg) (field environment)
• The two material properties (CTE and E) are driven by choices in resin, glass style, and filler
• Additional concern is in-plane properties (solder joint fatigue)
PCB Materials and Reliability
• The CTE mismatch between the printed circuit board
and the components attached to it is one of the major
fatigue issues of electronics
• Warpage and movement of the PCB during reflow can
cause cracked components, starved solder joint and
other assembly related defects
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Printed Circuit Board Properties
• Is the amount a material expands when exposed to a change in temperature
• It is unlikely that the designer or end user will be able to influence the component properties – Component packaging is typically driven by the die and assembly
– Passing of JEDEC level package tests
– May be able to pick parts with different lead frame materials
• Printed wiring board properties – Designer can influence printed wiring board properties
• Glass style
• Laminate type
• Copper
• Thickness
• This is one of the main factors that drive solder joint fatigue
• CTE mismatch within the printed circuit board causes warpage of the board during thermal exposure
Coefficient of Thermal Expansion
• In the past most electronic packages had CTE values closer to that of copper, 17.6 ppm/°C
• Larger die and smaller packages have driven a reduction in the component CTE, examples: – Leadless ceramic chip resistors – 5.6 ppm/°C
– QFN (quad flat no-leads) – 8 to 12 ppm/°C
• The CTE of the laminates has decreased over the years – The PCB laminate manufactures do not make it easy to determine
the CTE of their laminate
Influence of Board Properties
• Elimination of leaded devices
– Provides lower RC and higher package densities
– Reduces compliance
Solder Joint Fatigue
Cycles to failure
-40 to 125C QFP: >10,000
BGA: 3,000 to 8,000
QFN: 1,000 to 3,000 CSP / Flip Chip: <1,000
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• Not only a PCB issue but also a major concern of
laminate based components
– BGA devices
– LGA device
• As the solder joints get smaller the more sensitive they
are to component and board warpage effects
– QFN solder joints are more susceptible to dimensional
changes
Board Warpage
• Adds additional tools for more detailed modeling of
the printed circuit board and components
– Detailed FEA modeling options for traces
– Export of PCB traces to FEA tools
• Heatsink Modeling
• Additional lead modeling capabilities
• Improved ODB++ parsing, improved cut out editor and
the ability to use routing files
Sherlock 4.0
More FEA Model Parameters
• Allows more flexible FEA model generation
• Options for node and element numbering
• Vertical meshing size
• Element types
– 1st order
– 2nd order
– 3D solid shell
Effect of Arc Length
This is a de-featuring
function that helps reduce
the number of elements
produced in the FEA tool
Trace Export • Sherlock generates scripts that
build the PCB in FEA Tools (.apdl or .py supported) – Assigns material properties to the
regions – Can export copper, resin or drill
features
• Designed for doing more detailed analyses of substrates using finite element simulations – Models can be used for doing
warpage analyses – Thermal conduction simulations,
etc..
• These models are typically too detailed for use in mechanical shock or vibration simulations
Script Based • Material properties
assigned to copper and resin areas
• Best suited for generating detailed package models for investigating package CTE
Additional Board Modeling Techniques
Mosaic technique, material properties are averaged over the individual elements
• Uniform model, homogeneous properties for the whole board
• Layered model, homogenous properties per layer (layers have different mechanical properties)
Meshing Techniques
• Uniform elements model, mechanical properties vary only in-plane
• Layered elements model, each element has properties computed based on location and layer
Meshing Techniques, cont
• Sherlock now allows one to add through hole or surface mount leads to select components
• As expected adding features greatly increases the FEA model complexity
• 3D part viewer shows the part
Lead Modeling
• Sherlock
automatically post
processes the
simulation results to
extract the strains
developed in the lead
to make fatigue
predictions for it
Lead Modeling (cont.)
Sherlock automatically post-processes the FEA results to make predictions for lead vibration fatigue
Lead Modeling (cont.)
Lead Modeling (cont.)
Bonded model with leads on all through
hole components, model exported into Abaqus
or Ansys
• Sherlock 4.0
allows the user to
define
parameterized
heat sinks to the
top of components
Heat Sink Modeling
• Allows the user to specify routing files for making cuts
in the circuit board
• Polygon are now supported for making complex cut
shapes manually
– Predefined Shapes
– Slots
– Circular
– Rectangular
Improved Cut Out Operations
• Sherlock will automatically
detect the presence of a
routing layer
• Can set manually
Setting a Router Layer
• This Sherlock release is focused on adding additional
tools to allow more detailed Finite Element Modeling of
circuit board assemblies and packages
– Geometric trace modeling
– Improved cutouts
– Lead structures
– Heatsinks
Sherlock 4.0
41
Thank you!
Nathan Blattau
1-301-640-5821
Tom O’Connor
301-640-5812
Questions??