sh2 bus state controller - renesas e-learning · flash bus state controller high-performance user...

1© 2008, Renesas Technology America, Inc., All Rights Reserved

Course Introduction

� Purpose:

� This course provides an overview of the Bus State Controller and theData Transfer Controller on SH-2 and SH-2A families of 32-bit RISCmicrocontrollers, members of the SuperH® series

� Objectives:

� Gain a basic knowledge of the features and operation of the bus statecontroller

� Learn about the features and operation of the data transfer controller

� Content:� 25 pages� 3 questions

� Learning Time:� 20 minutes

© 2008, Renesas Technology America, Inc., All Rights Reserved

SuperH Peripheral Functions

� Microcontrollers for embedded

system applications require

extensive on-chip peripherals to

� Minimize system chip count

� Reduce overall system cost

� Facilitate small system size, etc.

� Built-in peripheral functions must

� Provide required capabilities

� Deliver needed performance levels

� Offer design flexibility

� Maintain a basic commonality

within product family, if possible

� Offer an acceptable cost-benefit

compromise, etc.

SH-2 SuperH32-bit RISC CPU

MAC32/DSP Function

SH7047 SuperH™ Series Microcontroller

Multi-function TimerPulse Unit

Compare-MatchTimer

Watchdog Timer

A/D Converter

Advanced User Debugger

Bus Interface

FLASH

Bus StateController

High-performanceUser Debug Interface

Clock PulseGenerator

RAM

Data TransferController

Interrupt Controller

User BreakController

I/O Ports

Motor Management Timer

Serial CommunicationInterface

Controller AreaNetwork Function


BREQ > DRAM > DTC > DMAC > CPU

SH-2 Series Bus State Controller

� In SH-2 series BSCs, the address space is divided intomultiple memory areas, each of which

� Has its own chip select (CS) signal

� Accesses internal memory as 32 bits wide, in 1 cycle

� Supports connection to SRAM, DRAM, SDRAM

� Can be configured individually for databus width and number of wait states

� Inserts idle cycles to eliminatecontention on the data bus

� Multiplexed address anddata bus interfaces simplifyASIC connection

� Parallel execution of externalwrites and internal accessimproves performance

� Internal bus arbitrator prioritizesbus masters as shown below:

On-chip Memory

Control Unit

Bus Interface

Module

Bus

Inte

rnal B

us

BRC1

BRC2

WRC1

RAMERWAIT

CS0

RD

WRL

Wait

Control Unit

Area

Control Unit

Memory

Control Unit

BSC (SH7047)


Memory Address Format

A31 - A24 A23, A22 A21 - A0

Output address on address pins

Chip Select space selection

Decoded outputs /CS0 - /CS3 when

A24-A31=0b00000000

Space selection

Not output externally; used to select the type of space as follows:

� On-chip ROM space or CS space when 00000000

� DRAM space when 00000001

� Reserved space form 00000002 to 11111110

� On-chip peripheral module space or on-chip RAM for 0b11111111

16MB space

4MB space

4GB space


Memory Interface Examples

32-bit data-width connection

SH-2 MCU 128Kx8 SRAM






Basic Bus Access

Normal space basic 2-state access Normal space basic access with software wait


Chip Select Insertion

Normal space /CSn period expansion

CS insertion process isuseful for mixing fast andslow memory devices

• /CSn asserted before /RDand /WR

• /RD and /WR de-selectedbefore /CSn

PROPERTIES

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On failing, 'Finish' button: Goes to Slide

Allow user to leave quiz: At any time

User may view slides after quiz: After passing quiz

User may attempt quiz: Unlimited times


SH-2A Bus State Controller

� Operation is similar to that of the SH-2 series BSC

� External address space supports

� 9 memory areas of 64MB each

– SRAM

– Burst ROM – clocked sync and async

– Multiplexed-IO (MPX-IO)

– Burst MPX-IO

– SDRAM

– PCMCIA interface

� 8-, 16-, and 32-bit data bus widths, settable for each area

� Wait cycle number, selectable for each area

� Idle cycle insertion


SH-2A BSC Features

� SDRAM interface, available on 2 memory areas, supports

� Multiplexed row and column addresses

� Auto-refresh and self-refresh modes

� Mode register set (MRS) and extended mode register set (EMRS)

commands

� Low frequency and power-down modes

� Use of refresh timer as an interval timer

� Bus arbitration allocates shared memory resources among the

CPU, internal, and external bus masters


SH-2A Address Space Division

� SH-2A further divides the 32-bit address space into

� Cache-enabled areas

� Cache-disabled areas

� On-chip areas (RAM, peripheral modules and reserved space)

� Division is defined by upper bits of address

� External spaces CS0 to CS7 are cache-enabled when the

internal address is A29=0

� External spaces CS0 to CS7 are cache-disabled when the

internal address is A29=1

� The CS8 space is always cache-disabled


SH-2A Addressing Example


SH-2A SDRAM Interface

No glue logic needed!


SH-2A MCU 1Mx16x4bank SDRAM



16-bit data-widthconnection



SH-2A BSC PCMCIA Interface

PCMCIA connection example

SH-2A MCUPC Card

(memory or I/O)

PROPERTIES




User may view slides after quiz: After passing quiz



Data Transfer Controller

�DTC moves the contents of memory or peripherals betweenlocations without using the CPU core

�Transfers can be requested by most peripherals, by interrupts,or by software

�Transfer information is stored in RAM, so� DTC can handle a large number of data transfer channels� Number of channels is limited only by memory size,

not hardware (unlike a DMAC)

�One activation source can trigger a number of data transfersusing DTC’s chain mode

�DTC supports a wide range of transfer modes� Normal� Repeat� Block transfer� Increment or decrement source or destination

�However, DTC is 3 times slower than a DMAC!


DTC Operation

To transfer data, the DTC� Is programmed to receive interrupt requests from specific external memory

and peripherals (other requests are sent to CPU)

� Receives an interrupt request

� Loads appropriate configuration data from internal RAM

� Transfers the data

� Writes configuration data back to RAM

� Clears source interrupt flag or sends interrupt to the CPU

DTC activated by an interrupt request


DTC Setup

�General setup is done in the DTC registers, which can beaccessed directly by the CPU

�Specific transfer information is stored in RAM� One block of RAM specifies a transfer

� Transfer registers cannot be accessed directly by CPU; instead, transferregister contents are read from memory

� Blocks are addressed from a vector table

�DTC vector table

� For each DTC transfer, the setup sequence must occur before the DTCcan read the corresponding RAM contents

�Calculation of DTC information

� DTC vector table stores low-order address word (16 bits) according tointerrupt source

� DTBR stores the high-order address word (16 bits)

� Recombining low-order and high-order words gives the 32-bit pointer toDTC register information


Data Transfer Speed

� Transfer speed depends in anumber of factors;in particular, the memory type(internal or external) and speed

�Execution state count

= vector read+ register information R/W+ data R/W+ internal operation

�Example of data transfer

process:

� On-chip RAM to I/O registers

� DTC information in internalmemory

� Number of states = 13(for first-generation SH-2 DTC)

END

Yes

No

Store register information to RAM

Next transfer?

Load register information from RAM

Data transfer

Read DTC vector

Start


Chain transferif selected

0 1 2Register informationstart address

Register information

Register informationfor second transfer in chain transfer mode

4 Bytes

DTDAR

DTSAR

DTCRADTMR

- / DTIAR / DTCRB

DTC Configuration Information

3


DTSAR

DTDAR

- / DTIAR / DTCRB

DTMRStart of setup table

Start of next table

+

0x400

DTC

Module32

+

16 bytes ofon-chip RAMrequired foreach DTCchannel

DTC Vector Table

0x4B4

DTC RAM

DTC Information Base Register

(DTBR)

Upper 16 bits

Lower 16 bits

DTCRA

Construction of Address in RAM

adrs:16


Three Transfer Modes

Normal ModeNormal Mode Repeat ModeRepeat Mode Block ModeBlock Mode

RegisterControl

Inte

rnal B

us

CPU interrupt request source clear control

RequestPriorityControl

External device(memory mapped)

Bus Interface DTC Module Bus

Bus Controller

DTMR

DTCR

DTSAR

DTDAR

DTIAR

DTER

DTCSR

DTBR

ActivationControl

Periphera

l B

us

Exte

rnal B

us

On-chip ROM

On-chip RAM

On-chip Peripheral

Module

Interrupt request

External memory

DTC (SH7047)


Transfers in Normal Mode

In normal mode, the DTC

� Transfers one byte, word, or longword per activation

� Makes 1 to 65,536 transfers

� Can generate a CPU interrupt at the end of the transfer

� Fixes, increments, or decrements source and destination addressesat the end of the transfer

� Clears the interrupt source flag at the end of each transfer

Transfer

Source Address Register

(SAR)

Destination Address Register(DAR)


Transfer

SARorDAR

DARorSAR

Transfers in Repeat Mode

In repeat mode, the DTC

� Transfers a byte, word, or longword per activation

� Makes 1 to 256 transfers

� Can generate a CPU interrupt at the end of the transfer

� Can increment or decrement the source and destination addresses

� Restores the SAR or DAR and transfer count registers to their initial valuesat the end of the transfer


Transfers in Block Mode

In block mode, the DTC

� Transfers one block of data per activation

� Designates either destination or source as the block area

� Specifies block length of 1 to 65,536

� Makes 1 to 65,536 block transfers

� Restores initial values of address register for block area and block sizecounter at the end of the transfer

Transfer

SARorDAR

DARorSAR

First block

nth block

Block area


Chain Transfers

Chain transfer enables the DTC to

� Make a number of data transfers consecutively in response toa single transfer request

� Make transfers using different modes

DTC vector

address

Register informationstart address

Register informationCHNE=1

Register informationCHNE=0

Source

Destination

Source

Destination

PROPERTIES




User may view slides after quiz: At any time



Course Summary

� Bus state controller

� Data transfer controller

sh2 bus state controller - renesas e-learning · flash bus state controller high-performance user...

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