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DRAFT SFF-TA-1024 Rev 0.0.2 Template Rev 1.0
Test Procedure for SFF-TA-1016 Mated Cable Assembly Page 1
Copyright Β© 2021 SNIA. All rights reserved.
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SFF-TA-1024 7
Specification for 8
Test Procedure for SFF-TA-1016 Mated Cable Assembly 9
Rev 0.0.2 March 03, 2021 10 11
SECRETARIAT: SFF TA TWG 12 This specification is made available for public review at http://www.snia.org/sff/specifications. Comments 13
may be submitted at http://www.snia.org/feedback. Comments received will be considered for inclusion in 14
future revisions of this specification. 15 16
The description of the connector in this specification does not assure that the specific component is available 17 from connector suppliers. If such a connector is supplied, it should comply with this specification to achieve 18
interoperability between suppliers. 19
20 21
ABSTRACT: This specification defines the test procedure and outlines the steps required to perform high 22 speed signal integrity measurements on SFF-TA-1016 style mated cable assemblies. 23
24 POINTS OF CONTACT: 25
26
Paul Coddington Chairman SFF TA TWG 27 Amphenol High Speed Interconnects Email: [email protected] 28
20 Valley Street 29 Endicott, NY 13760 30
31
Ph: 607-754-4444 32 Email: [email protected]
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Copyright Β© 2021 SNIA. All rights reserved.
Intellectual Property 1 The user's attention is called to the possibility that implementation of this specification may require the use 2
of an invention covered by patent rights. By distribution of this specification, no position is taken with 3 respect to the validity of a claim or claims or of any patent rights in connection therewith. 4
This specification is considered SNIA Architecture and is covered by the SNIA IP Policy and as a result goes 5
through a request for disclosure when it is published. Additional information can be found at the following 6 locations: 7
8
Results of IP Disclosures: http://www.snia.org/sffdisclosures 9
SNIA IP Policy: http://www.snia.org/ippolicy 10 11
Copyright 12 The SNIA hereby grants permission for individuals to use this document for personal use only, and for 13
corporations and other business entities to use this document for internal use only (including internal 14
copying, distribution, and display) provided that: 15 16
1. Any text, diagram, chart, table or definition reproduced shall be reproduced in its entirety with no alteration, and,
2. Any document, printed or electronic, in which material from this document (or any portion hereof) is
reproduced shall acknowledge the SNIA copyright on that material, and shall credit the SNIA for granting permission for its reuse.
17 Other than as explicitly provided above, there may be no commercial use of this document, or sale of any 18
part, or this entire document, or distribution of this document to third parties. All rights not explicitly granted 19 are expressly reserved to SNIA. 20
21
Permission to use this document for purposes other than those enumerated (Exception) above may be 22 requested by e-mailing [email protected]. Please include the identity of the requesting individual 23
and/or company and a brief description of the purpose, nature, and scope of the requested use. Permission 24 for the Exception shall not be unreasonably withheld. It can be assumed permission is granted if the 25
Exception request is not acknowledged within ten (10) business days of SNIA's receipt. Any denial of 26
permission for the Exception shall include an explanation of such refusal. 27 28
29 Disclaimer 30
The information contained in this publication is subject to change without notice. The SNIA makes no 31 warranty of any kind with regard to this specification, including, but not limited to, the implied warranties 32
of merchantability and fitness for a particular purpose. The SNIA shall not be liable for errors contained 33
herein or for incidental or consequential damages in connection with the furnishing, performance, or use 34 of this specification. 35
36 Suggestions for revisions should be directed to http://www.snia.org/feedback/. 37
38
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Copyright Β© 2021 SNIA. All rights reserved.
Foreword 1 The development work on this specification was done by the SNIA SFF TWG, an industry group. Since its 2
formation as the SFF Committee in August 1990, the membership has included a mix of companies which 3 are leaders across the industry. 4
5
For those who wish to participate in the activities of the SFF TWG, the signup for membership can be found 6 at http://www.snia.org/sff/join. 7
8 Revision History 9
10 Rev 0.0.1 January 15, 2021: 11
- Initial draft 12
Rev 0.0.2 March 03, 2021: 13 - Added βMated Cable Assemblyβ to the Section 4 heading. 14
- Removed Section 4.1 through Section 4.4 and renumbered the remaining Section 4 15 headings accordingly. 16
- Added βMated Cable Assemblyβ to the Section 4.1 heading. 17
- In Section 5.1.1, fixed typo in Appendix A reference. 18 - In Section 5.2.5, corrected reference to Appendix C. 19
- In Section 5.2.8.5, removed erroneous Appendix reference. 20 - In Section 6.3, edited Equation 6-1 label. 21
- In Section 6.4, edited Equation 6-2 label, removed Equation 6-3 label, and renumbered 22 all remaining Equations. 23
- In Section 6.5.1, added hyphen to single-aggressor and edited new Equation 6-3 label. 24
- In Section 6.5.2, edited new Equation 6-4 label. 25 - In Section 6.6.1, added hyphen to single-aggressor and edited new Equation 6-5 label. 26
- In Section 6.6.2, edited new Equation 6-6 label. 27 - Inserted a new Section 6.7 and renumbered the remaining Section 6 headings 28
accordingly. 29
- In Section 6.8, edited new Equation labels and updated the formatting of several 30 Equations. 31
- In Section 6.9, edited new Equation labels, replaced old Figure 6-14 with new Equation 32 6-15, renumbered the remaining Section 6 Figures, and updated the formatting of 33
several Equations. 34
- In Section 6.10, edited new Equation labels and updated the formatting of several 35 Equations. 36
- In Section 7, rotated Table 7-1, Table 7-2, and Table 7-3 in order to enlarge them to 37 increase the text size. 38
- In Appendix A, rotated Table A-1 3 in order to enlarge the table to increase the text 39 size. 40
- In Appendix B, Section B.4, added missing steps to Table B-4 and removed all rows 41
after step 43. 42 - In Appendix B, Section B.5, removed all rows after step 45 in Table B-5. 43
44 45
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Contents 1
1. Scope 7 2
2. References and Conventions 7 3 2.1 Industry Documents 7 4
2.2 Sources 7 5
2.3 Conventions 8 6
3. Keywords, Acronyms, and Definitions 9 7
3.1 Keywords 9 8 3.2 Acronyms and Abbreviations 10 9
3.3 Definitions 11 10
4. General Mated Cable Assembly Compliance Test Board Description 14 11
4.1 Mated Cable Assembly Compliance Board Design 14 12
4.2 Calibration Standards 15 13 4.3 Reference Plane Positions 16 14
4.4 Board Stack-up 18 15 4.5 Fixed Connector Footprint 19 16
4.6 Mated Cable Assembly Test Set-up 20 17
5. Equipment Settings, Calibration, & Verification 21 18 5.1 Overview 21 19
5.1.1 Device Under Test (DUT) 21 20 5.1.2 Time and Frequency Domain Measure Test Flow 21 21
5.2 VNA Equipment Settings 22 22 5.2.1 Electronic Calibration (E-Cal) 22 23
5.2.2 Manual Calibration 23 24
5.2.3 Stop Frequency, F(max) 23 25 5.2.4 Reference Plane Definition 24 26
5.2.5 Time Domain Reflectometry Tuning 24 27 5.2.6 Fixture Intra-pair Skew 25 28
5.2.7 Flight Time 26 29
5.2.8 Calibration Verification 26 30 5.2.8.1 Secondary Line Phase Margin 26 31
5.2.8.2 Calibration Stability 26 32 5.2.8.3 Dynamic Range 26 33
5.2.8.4 Check System Reference Impedance 27 34
5.2.8.5 TRL Four Port Calibration 27 35
6. Frequency Domain Measurement 28 36
6.1 Port Naming Convention 28 37 6.2 Fixed Connector Termination During Measurement 29 38
6.3 Differential Insertion Loss (SDD21) 29 39 6.4 Differential Return Loss (SDD11 and SDD22) 30 40
6.5 Crosstalk Measurement 32 41
6.5.1 Single-aggressor Near-end Crosstalk (DDNEXT) 32 42 6.5.2 Multi-Disturber Near-end Crosstalk (MDNEXT) 32 43
6.6 Far End Crosstalk 34 44 6.6.1 Single-aggressor Far-End Crosstalk (DDFEXT) 34 45
6.6.2 Multi-Disturber Far-End Crosstalk (MDFEXT) 34 46
6.7 MDFEXT Without Fixture FEXT (MDFEXTwoff) 36 47 6.8 Effective Intra-Pair Skew (EIPS) 36 48
6.9 Effective Pair-to-Pair Skew (EPPS) 38 49
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6.10 Mated Cable Assembly Skew Measurement 39 1 6.11 Impedance Measurement 39 2
6.11.1 Rise Time 39 3 6.11.2 Instantaneous Impedance 39 4
6.11.3 Average Impedance 40 5
7. Test Plans 41 6 7.1 Vertical Receptacle to Vertical Receptacle, MCA Measurement, Rx to Tx Cable 41 7
7.2 Vertical Receptacle to RA Receptacle, MCA Measurement, Rx to Tx Cable 42 8 7.3 RA Receptacle to RA Receptacle, MCA Measurement, Rx to Tx Cable 43 9
Appendix A Cyllene Bill of Materials 44 10
Appendix B VNA TRL Calibration 45 11
B.1 TRL Calibration Crossover Frequencies 45 12
B.2 TRL Calibration E-cal and Fixture Bandwidth 45 13 B.3 Initial TRL Calibration Steps 1 - 22 46 14
B.4 Final TRL Calibration Steps Using 2 Defined Throughs + 2 Unknown Throughs 47 15 B.5 Final TRL Calibration Steps Using 2 Defined Throughs + 4 Unknown Throughs 48 16
Appendix C Rise Time Measurement 49 17
C.1 TDR Head Connections 49 18 C.2 TDR Instrument Default Settings. 49 19
C.3 TDR Mode Setup. 50 20 C.4 Channel Definition 50 21
C.5 View the Rising Edge 51 22 C.6 Rise Time Measurement Setup. 51 23
C.7 Rise Time Adjustments. 54 24
C.7.1 Rise Time Adjustment Option 1 54 25 C.7.2 Rise Time Adjustment Option 2. 54 26
27 Figures 28
Figure 3-1 Plug and Receptacle Definition 12 29
Figure 3-2 Right Angle Connector and Cable Assembly 12 30 Figure 3-3 Wipe for a Continuous Contact 13 31
Figure 4-1 Mated Cable Assembly Evaluation Board Set: Cyllene RAR, Cyllene VR 14 32 Figure 4-2 Mated Cable Assembly Evaluation TRL Calibration Traces 15 33
Figure 4-3 Mated Cable Assembly Evaluation Board Reference Plane Location: RAR 16 34
Figure 4-4 Mated Cable Assembly Evaluation Board Reference Plane Location: VR 17 35 Figure 4-5 Mated Cable Assembly Reference Plane Location in Crosstalk Spider 18 36
Figure 4-6 The 8-Layer Stack-up for Cyllene RAR & Cyllene VR Test Boards 19 37 Figure 4-7 Mated Cable Assembly Evaluation Board Footprint Dimensions: RAR, VR 19 38
Figure 4-8 Mated Cable Assembly Evaluation Board Stack-up: RAR, VR 20 39 Figure 4-9 Recommended Mated Cable Assembly Configurations 20 40
Figure 5-1 Mated Cable Assembly Evaluation Device Under Test, VR-RAR Fixed Connectors 21 41
Figure 5-2 Time and Frequency Domain Measurement Test Flow 22 42 Figure 5-3 Example of Allen Test results to characterize the stop frequency, Fmax 23 43
Figure 5-4 Open Circuit Configuration 24 44 Figure 5-5 RL Measurement from Test Fixtures 25 45
Figure 5-6 TDR Obtained via FD to TD Conversion of RL of a Differential Pair 25 46
Figure 6-1 VNA Port Naming Convention Example 28 47 Figure 6-2 Mated Cable Assembly Evaluation Board Pin Termination: RAR, VR 29 48
Figure 6-3 Vertical MCIO to Vertical MCIO, Insertion Loss/Return Loss, Tx to Rx Cable 30 49 Figure 6-4 Vertical MCIO to RA MCIO Tx to Rx Cable 31 50
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Figure 6-5 Right Angle MCIO to Right Angle MCIO, Insertion Loss/Return Loss, Tx to Rx Cable 31 1 Figure 6-6 Vertical Receptacle, NEXT RX Victim 33 2
Figure 6-7 Right Angle Receptacle, NEXT RX Victim, Tx to Rx Cable 33 3 Figure 6-8 Vertical to Vertical, FEXT Rx Victim, Tx to Rx Cable 34 4
Figure 6-9 Vertical to Right Angle, FEXT Rx Victim, Tx to Rx Cable 35 5
Figure 6-10 Vertical to Right Angle, FEXT Rx Victim, Tx to Rx Cable 35 6 Figure 6-11 Modified Mixed-Mode Insertion Loss, S2d1 and S4d1 36 7
Figure 6-12 Intra-Pair Skew Introduction to a 4-Port System 37 8 Figure 6-13 2 Differential Pair Port Map 38 9
Figure 6-14 Skew Measurement Test Set 39 10 Figure 6-15 Instantaneous Impedance Example 40 11
Figure 6-16 Average Impedance Example 40 12
Figure C-1 TDR Head Connections 49 13 Figure C-2 TDR Instrument Default Settings Screenshot 49 14
Figure C-3 TDR Mode Setup Screenshot 50 15 Figure C-4 Channel Definition Setup 50 16
Figure C-5 TDR View of Rising Edge 51 17
Figure C-6 Screenshot for Setup Steps a. and b. 51 18 Figure C-7 Screenshot for Setup Steps b. and c. 52 19
Figure C-8 Screenshot for Setup Steps d. and e. 52 20 Figure C-9 Screenshot for Setup Step f. 53 21
Figure C-10 Screenshot for Setup Steps g. and h. 53 22 Figure C-11 Screenshot for Option 2 Steps a. and b. and c. 54 23
Figure C-12 Screenshot Showing Measured Rise Time 55 24
25 26
Tables 27 Table 5-1 VNA Equipment Settings 22 28
Table 5-2 CYLLENE Mated Cable Evaluation Board TRL Calibration Launch Position vs TRL Line 26 29
Table 7-1 VR to VR Test Plan 41 30 Table 7-2 VR to RA Test Plan 42 31
Table 7-3 RA to RA Test Plan 43 32 Table A-1 Cyllene Bill of Materials 44 33
Table B-1 TRL Calibration Kit Crossover Frequencies 45 34
Table B-2 E-cal and Fixture Bandwidth Checks 45 35 Table B-3 Initial TRL Calibration Steps 46 36
Table B-4 TRL Calibration Steps 23 to 43 Using 2 Defined Throughs + 2 Unknown Throughs 47 37 Table B-5 Final TRL Calibration Steps Using 2 Defined Throughs + 4 Unknown Throughs 48 38
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1. Scope 1
This specification defines the test procedure and outlines the steps required to perform high speed signal 2
integrity measurements on SFF-TA-1016 style mated cable assemblies. 3
2. References and Conventions 4
2.1 Industry Documents 5
The following documents are relevant to this specification: 6
- ASME Y14.5 Dimensioning and Tolerancing 7 - EIA-364-1000 Environmental Test Methodology for Assessing the Performance of Electrical 8
Connectors and Sockets Used in Controlled Environment Applications 9 - REF-TA-1011 Cross Reference to Select SFF Connectors 10
- Sample Doc # Sample Document Title 11
- Sample Doc ## Sample Document Title 2 12 13
2.2 Sources 14
The complete list of SFF documents which have been published, are currently being worked on, or that 15 have been expired by the SFF Committee can be found at http://www.snia.org/sff/specifications. 16
Suggestions for improvement of this specification will be welcome, they should be submitted to 17 http://www.snia.org/feedback. 18 19 EDITORβS NOTE: Delete sources not cited in Section 2.1; e.g. PCIe, SAS, etc. (or add in any missing 20 references) 21
22 Copies of PCIe standards may be obtained from PCI-SIG (http://pcisig.com). 23
24 Copies of InfiniBand standards may be obtained from the InfiniBand Trade Association (IBTA) 25
(http://www.infinibandta.org). 26 27
Copies of IEEE standards may be obtained from the Institute of Electrical and Electronics Engineers (IEEE) 28
(https://www.ieee.org). 29 30
Copies of SAS and other ANSI standards may be obtained from the International Committee for Information 31 Technology Standards (INCITS) (http://www.incits.org). 32
33
Copies of JEDEC standards may be obtained from the Joint Electron Device Engineering Council 34 (https://www.jedec.org). 35
36 Copies of OIF Implementation Agreements may be obtained from the Optical Internetworking Forum 37
(http://www.oiforum.com). 38
39 Copies of ASME standards may be obtained from the American Society of Mechanical Engineers 40
(https://www.asme.org). 41 42
Copies of Electronic Industries Alliance (EIA) standards may be obtained from the Electronic Components 43 Industry Association (ECIA) (https://www.ecianow.org). 44
45
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2.3 Conventions 1
The following conventions are used throughout this document: 2
3 DEFINITIONS 4
Certain words and terms used in this standard have a specific meaning beyond the normal English meaning. 5
These words and terms are defined either in the definitions or in the text where they first appear. 6 7
ORDER OF PRECEDENCE 8 If a conflict arises between text, tables, or figures, the order of precedence to resolve the conflicts is text; 9
then tables; and finally figures. Not all tables or figures are fully described in the text. Tables show data 10
format and values. 11 12
LISTS 13 Lists sequenced by lowercase or uppercase letters show no ordering relationship between the listed items. 14
15 EXAMPLE 1 - The following list shows no relationship between the named items: 16
a. red (i.e., one of the following colors): 17
A. crimson; or 18 B. pink; 19
b. blue; or 20 c. green. 21
22
Lists sequenced by numbers show an ordering relationship between the listed items. 23 24
EXAMPLE 2 -The following list shows an ordered relationship between the named items: 25 1. top; 26
2. middle; and 27
3. bottom. 28 29
Lists are associated with an introductory paragraph or phrase, and are numbered relative to that paragraph 30 or phrase (i.e., all lists begin with an a. or 1. entry). 31
32 DIMENSIONING CONVENTIONS 33
The dimensioning conventions are described in ASME-Y14.5, Geometric Dimensioning and Tolerancing. All 34
dimensions are in millimeters, which are the controlling dimensional units (if inches are supplied, they are 35 for guidance only). 36
37 NUMBERING CONVENTIONS 38
The ISO convention of numbering is used (i.e., the thousands and higher multiples are separated by a 39
space and a period is used as the decimal point). This is equivalent to the English/American convention of 40 a comma and a period. 41
42 American French ISO
0.6 0,6 0.6 1,000.0 1 000,0 1 000.0
1,323,462.9 1 323 462,9 1 323 462.9
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3. Keywords, Acronyms, and Definitions 1
For the purposes of this document, the following keywords, acronyms, and definitions apply. 2 EDITORβS NOTES: 3
- Add any abbreviations or definitions specific to the connector being defined. Keywords may not be 4 added. 5
- Remove keywords, acronyms, or definitions that are not relevant to this specification 6
3.1 Keywords 7
May/ may not: Indicates flexibility of choice with no implied preference. 8
9 Obsolete: Indicates that an item was defined in prior specifications but has been removed from this 10
specification. 11
12 Optional: Describes features which are not required by the SFF specification. However, if any feature 13
defined by the SFF specification is implemented, it shall be done in the same way as defined by the 14 specification. Describing a feature as optional in the text is done to assist the reader. 15
16
Prohibited: Describes a feature, function, or coded value that is defined in a referenced specification to 17 which this SFF specification makes a reference, where the use of said feature, function, or coded value is 18
not allowed for implementations of this specification. 19 20
Reserved: Defines the signal on a connector contact [when] its actual function is set aside for future 21 standardization. It is not available for vendor specific use. Where this term is used for bits, bytes, fields, 22
and code values; the bits, bytes, fields, and code values are set aside for future standardization. The default 23
value shall be zero. The originator is required to define a Reserved field or bit as zero, but the receiver 24 should not check Reserved fields or bits for zero. 25
26 Restricted: Refers to features, bits, bytes, words, and fields that are set aside for other standardization 27
purposes. If the context of the specification applies the restricted designation, then the restricted bit, byte, 28
word, or field shall be treated as a reserved bit, byte, word, or field (e.g., a restricted byte uses the same 29 value as defined for a reserved byte). 30
31 Shall: Indicates a mandatory requirement. Designers are required to implement all such mandatory 32
requirements to ensure interoperability with other products that conform to this specification. 33 34
Should: Indicates flexibility of choice with a strongly preferred alternative. 35
36 Vendor specific: Indicates something (e.g., a bit, field, code value) that is not defined by this specification. 37
Specification of the referenced item is determined by the manufacturer and may be used differently in 38 various implementations. 39
40
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3.2 Acronyms and Abbreviations 1
AWG: American Wire Gauge 2
dB: decibel, given in dB-volt i.e., 20log10(V2/V1) 3 DUT: Device Under Test 4
E-Cal: Electronic calibration 5
EMLB: Early Mate Late Break 6 EIPS: Effective Intra-pair Skew 7
EPPS: Effective Pair-to-Pair Skew 8 ESD: Electrostatic Discharge 9
Fmax: stop frequency, maximum operating frequency, and frequency at which insertion loss β return loss 10
of the fixture 5 dB 11 IDC: Insulation Displacement Contact 12
IDT: Insulation Displacement Termination 13 Gbps: Gigabits per second 14
GT/s: Giga-Transfers per second 15 HVLP: Hyper Very Low Profile 16
HVSP: Hyper Very Smooth Profile 17
LLCR: Low Level Contact Resistance 18 MCA: Mated Cable Assembly 19
PCB: Printed Circuit Board 20 PF: Press Fit 21
PSFEXT: Power Sum Far End Crosstalk 22
PSNEXT: Power Sum Near End Crosstalk 23 PTH: Plated Through Hole 24
RA: Right Angle 25 RAR: Right Angle Receptacle 26
RAND: Reasonable and Non-Discriminatory 27
RL: Return Loss 28 SDD11: Input Differential Return Loss 29
SDD12: Output Differential Return Loss 30 SDD21: Input Differential Insertion Loss 31
SDD22: Output Differential Return Loss 32 SMA: Sub-Miniature version A 33
SMT: Surface Mount Technology 34
SOLT: Short, Open, Load, Thru 35 TDR: Time Domain Reflectometry 36
TDT: Time Domain Through 37 TEM: Transverse Electro-Magnetic 38
TRL: Through, Reflect, Line 39
VNA: Vector Network Analyzer 40 VR: Vertical Receptacle 41
VLC: Vertical Launch Connector 42 VSP: Very Smooth Profile 43
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3.3 Definitions 1
Allen Test: Insertion loss and return loss measurement of the primary thru, measurement made after 2
SOLT/E-calibration and prior to TRL/2x Thru calibration to determine the maximum operational frequency 3 of the VNA and fixture equipment set. 4
5
Alignment guides: A term used to describe features that pre-align the two halves of a connector interface 6 before electrical contact is established. Other common terms include: guide pins, guide posts, blind mating 7
features, mating features, alignment features, and mating guides. 8 9
Basic (dimension): The theoretical exact size, profile, orientation, or location of a feature. It is used as 10
the basis from which permissible variations are established by tolerances in notes or in feature control 11 frames (GD&T). 12
13 Cable Assembly: the combination of wire and free connectors 14
15 Connector: Each half of an interface that, when joined together, establish electrical contact and 16
mechanical retention between two components. In this specification, the term connector does not apply to 17
any specific gender; it is used to describe the receptacle, the plug or the card edge, or the union of 18 receptacle to plug or card edge. Other common terms include: connector interface, mating interface, and 19
separable interface. 20 21
Contact mating sequence: A term used to describe the order of electrical contact established/ 22
terminated during mating/un-mating. Other terms include: contact sequencing, contact positioning, mate 23 first/break last, EMLB (early mate late break) staggered contacts, and long pin/short pin. 24
25 Contacts: A term used to describe connector terminals that make electrical connections across a separable 26
interface. 27
28 Datum: A point, line, plane, etc. assumed to be exact for the purposes of computation or reference, as 29
established from actual features, and from which the location or geometric relationship of either feature is 30 established. 31
32 Device Under Test (DUT): The components within the measurement reference planes. 33
34
Free Connector: a connector, typically a plug, permanently attached to wire, creating a cable assembly. 35 36
Fixed Connector: a connector, typically a receptacle, permanently attached to the printed circuit board. 37 38
Frontshell / Backshell: A term used to describe the metallic part of a module that provides mechanical 39
and shielding continuity between the plug and receptacle. Other terms commonly used are: housing, snout, 40 and metal shroud. 41
42 Mated Cable Assembly (MCA): refers to the combination of copper wire, plugs, receptacles and 43
receptacle footprint that comprise the device under test in this specification. 44 45
Module: In this specification, module may refer to a plug assembly at the end of a copper (electrical) cable 46
(passive or active), an active optical cable (AOC), an optical transceiver, or a loopback. 47 48
Plug: A term used to describe the connector that contains the penetrating contacts of the connector 49 interface as shown in Figure 3-1. Plugs typically contain stationary contacts. Other common terms include 50
male, pin connector, and card edge. 51
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1
Figure 3-1 Plug and Receptacle Definition 2
3
Plated through hole termination: A term used to describe a termination style in which rigid pins extend 4 into or through the PCB. Pins are soldered to keep the connector or cage in place. Other common terms 5
are through hole or PTH. 6
7 Press fit: A term used to describe a termination style in which collapsible pins penetrate the surface of a 8
PCB. Upon insertion, the pins collapse to fit inside the PCBβs plated through holes. The connector or cage 9 is held in place by the interference fit between the collapsed pins and the PCB. 10
11 Receptacle: A term used to describe the connector that contains the contacts that accept the plug contacts 12
as shown in Figure 3-1. Receptacles typically contain spring contacts. Other common terms include female 13
and socket connector. 14 15
Reference (dimension): A dimension provided for information or convenience. It has no tolerance and 16 is not to be used for inspection or conformance. It can be calculated from other tolerance dimensions or 17
can be found elsewhere on the drawing with a tolerance. If removed, it would have no impact on the 18
defined object or the ability or reproduce it. 19 20
Reference Plane: the location within the measurement fixture where user calibration is performed and 21 where the measurement is made. 22
23 Right Angle: A term used to describe either a connector design where the mating direction is parallel to 24
the plane of the printed circuit board upon which the connector is mounted or a cable assembly design 25
where the mating direction is perpendicular to the bulk cable. 26
a) Right angle connector
b) Right angle cable assembly
Figure 3-2 Right Angle Connector and Cable Assembly 27
28
Straddle mount: A term used to describe a termination style that uses surface mount termination points 29
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on both sides of a PCB. 1 2
Straight: A term used to describe a connector design where the mating direction is parallel to the bulk 3 cable. 4
5
Surface mount: A term used to describe a termination style in which solder tails sit on pads on the surface 6 of a PCB and are then soldered to keep the connector or cage in place. Other common terms are surface 7
mount technology or SMT. 8 9
Termination: A term used to describe a connectorβs non-separable attachment point such as a connector 10 contact to a bulk cable/ a cage to a PCB or flex circuit/ bulk cable to a PCB or flex circuit/ solder tail to PCB. 11
Common PCB terminations include: surface mount (SMT), plated through hole termination (PTH), and press 12
fit (PF). Common cable terminations include insulation displacement contact (IDC), insulation displacement 13 termination (IDT), wire slots, solder, welds, crimps, and brazes. 14
15 Vertical: A term used to describe a connector design where the mating direction is perpendicular to the 16
printed circuit board upon which the connector is mounted. 17
18 Wipe: The distance a contact travels on the surface of its mating contact during the mating cycle as shown 19
in Figure 3-3. 20
21
Figure 3-3 Wipe for a Continuous Contact 22
23
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4. General Mated Cable Assembly Compliance Test Board 1
Description 2
4.1 Mated Cable Assembly Compliance Board Design 3
Test boards are designed to support TRL calibration and 2x thru methods with launch to reference plane 4
lengths equal within Β±0.0005β enabling accurate high-speed measurements of the mated cable assembly. 5 Crosstalk spider patterns are used to estimate fixture crosstalk to aid in accurate characterization of cable 6
assembly crosstalk. All boards are designed to achieve 42.5 Β± 5% impedance control. Board stacks, 7 materials, line lengths and calibration structures are designed to allow mated cable assembly 8
characterization. 9 10
11
12
Figure 4-1 Mated Cable Assembly Evaluation Board Set: Cyllene RAR, Cyllene VR 13
14
15
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4.2 Calibration Standards 1
TRL calibration standards, one primary through, one short (reflect), three lines (called Secondary 1, 2, and 2
3) and one load are used as depicted in Figure 4-2. The frequency range for each secondary is written on 3 the silkscreen. Secondary line delay labels are for reference only, use measured secondary delays for 4
calibration. 2X through calibration is enabled using the primary though (2X through). 5
6
7
Figure 4-2 Mated Cable Assembly Evaluation TRL Calibration Traces 8
9
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4.3 Reference Plane Positions 1
The primary through is designed to position the reference plane 0.050β from the trace/anti-pad transition 2
on the test board. 3 4
5
Figure 4-3 Mated Cable Assembly Evaluation Board Reference Plane Location: RAR 6
7
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1
Figure 4-4 Mated Cable Assembly Evaluation Board Reference Plane Location: VR 2
3
The fixture FEXT removal structure is based on the four traces with highest potential for fixture crosstalk 4
in the vertical receptacle board. 5 6
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1
Figure 4-5 Mated Cable Assembly Reference Plane Location in Crosstalk Spider 2
3
4.4 Board Stack-up 4
The VNA setup and test plan used in this procedure are designed to produce S-parameter measurements 5 referenced to a 42.5 ohm single-ended impedance. All test traces are held to a characteristic impedance of 6
42.5 ohms +/- 5%. The test board is an eight layer stack-up. MEGTRON 6 or TU-883 are used for the 7 laminate material on all layers. The stack-up details for the boards are shown in Figure 4-6. 8
9
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1
Figure 4-6 The 8-Layer Stack-up for Cyllene RAR & Cyllene VR Test Boards 2
3
4.5 Fixed Connector Footprint 4
Fixed connector surface pad, anti-pad, ground via size, and position have a significant impact on mated 5 cable assembly performance. The following figures illustrate optimal fixed connector footprints for vertical 6
and right angle receptacles. 7
8
Figure 4-7 Mated Cable Assembly Evaluation Board Footprint Dimensions: RAR, VR 9
10
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1
Figure 4-8 Mated Cable Assembly Evaluation Board Stack-up: RAR, VR 2
3
4.6 Mated Cable Assembly Test Set-up 4
The test boards should be attached to a rigid structure to ensure proper and stable mated cable assembly 5 configuration during test. Recommended mated cable assembly configurations are shown in Figure 4-9. 6
7
8
Figure 4-9 Recommended Mated Cable Assembly Configurations 9
10
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5. Equipment Settings, Calibration, & Verification 1
5.1 Overview 2
5.1.1 Device Under Test (DUT) 3
Figure 5-1 illustrates the test setup for the VNA measurement, location of the measurement reference 4 planes, and mated cable assembly DUT descriptions. 5
6
The vector network analyzer setup used in this test procedure performs single-ended S-parameter 7 measurements that are used to calculate differential response in an 85 ohm characteristic impedance 8
environment. 9 10
Test traces on the board are maintained to 42.5 Β±2.25 ohms (Β±5%). Test boards are designed with trace 11 length (L) from the launch connector to the reference plane to within Β±0.0005. The bill of materials is listed 12
in Appendix A. 13
14
15
Figure 5-1 Mated Cable Assembly Evaluation Device Under Test, VR-RAR Fixed Connectors 16
17
5.1.2 Time and Frequency Domain Measure Test Flow 18
The test flow in the following figure describes the key steps and responses needed to complete accurate 19
and repeatable time and frequency domain measurements. Key steps such as calibration, rise time 20 verification, de-skew and Cal check should be performed daily, both before and after completing the 21
measurement test plan to ensure stability of the test environment for the duration of the measurement 22
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activity. 1 2
3
Figure 5-2 Time and Frequency Domain Measurement Test Flow 4
5
5.2 VNA Equipment Settings 6
S-parameter measurements are made using a Vector Network Analyzer (VNA). VNA settings affect the 7 measurement and calibration performance. To improve measurement accuracy and repeatability, use the 8
baseline settings indicated in the following table when running a calibration procedure. 9 10
Table 5-1 VNA Equipment Settings 11
Frequency Range 0.01 GHz: 0.01 GHz: 40 GHz
IF Bandwidth β€ 1 kHz
Number of averages Averaging is not recommended
Smoothing Off 12
CAUTION: WHEN ATTACHING THE SMA FEMALE/MALE CONNECTORS BETWEEN THE FIXTURE AND THE VNA 13
INSTRUMENT MAKE SURE TO ROTATE THE EXTERNAL BOLT OF THE CONNECTOR AVOIDING THE 14 ROTATION OF THE CABLES/FIXTURE/CALIBRATION DEVICES TO AVOID THE DAMAGE OF THE 15
CENTRAL PIN. MAKE SURE TO TIGHTEN THE CONNECTIONS TO 8 IN-LBS USING A TORQUE 16 WRENCH. 17
18
5.2.1 Electronic Calibration (E-Cal) 19
To carry out the calibration of the equipment using the E-Cal device, the number of points, IF bandwidth, 20
and the start and stop frequencies must be set. With the proper setting of the VNA instrument, go to the 21 calibration menu and choose the option E-Cal, then chose the proper E-Cal device and run the calibration 22
making the proper connections as indicated by the wizard. Once the calibration is finished save the setup. 23
24
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5.2.2 Manual Calibration 1
The manual calibration is performed using the calibration kit provided by the manufacturer of the VNA 2
instrument. The calibration routine must be carried out setting the appropriate number of points and 3 ensuring that the start/stop calibration frequencies enclose the stop frequency of the Allen Test. 4
5
WARNING: VERIFY THE PROPER MATCHING OF THE CONNECTOR CABLES AND THE CONNECTIONS OF THE 6 MANUAL CALIBRATION DEVICES TO AVOID MECHANICAL DAMAGE. 7
8
Under normal conditions the following calibrations are required: 9
Reflective Calibration: This calibration includes three different measurements using the devices 10
provided in the calibration kit. 11
a. Short Circuit Calibration 12
b. Open Circuit Calibration 13
c. Broadband load calibration (usually a 50 Ξ© load) 14
Through Calibration: The through calibration is carried out connecting the ports to be calibrated 15
with the cables in short circuit. It is important to take into consideration the extra delay introduced 16
by the through device when the through calibration is carried out. 17
Isolation calibration: The isolation calibration is usually omitted. 18
19
5.2.3 Stop Frequency, F(max) 20
The Stop Frequency Test is a useful test procedure to determine the maximum operating frequency (Fmax) 21
of the test set-up including test fixture and VNA. Over the frequency range up to Fmax, the RF components 22 and the VNA should not resonate. The Allen Test is performed using the primary through. There should be 23
at least 5 dB margin between Insertion Loss (IL) and Return Loss (RL) at the highest measured frequency. 24 The following steps are recommended for the Allen Test. 25
26
1. Perform SOLT calibration to set the reference plane at the VNA cable ends. 27
2. Measure primary through on the baseboard 28
3. Assess IL for significant high Q deviations. 29
4. Assess frequency of 5 dB difference between insertion loss and return loss. 30
31
32
Figure 5-3 Example of Allen Test results to characterize the stop frequency, Fmax 33
34
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5.2.4 Reference Plane Definition 1
The VNA must be calibrated to a known standard to characterize the performance of the connector in the 2
test fixture. The intent of the calibration is to eliminate systematic errors in the measurement and improve 3 measurement accuracy. 4
5
The precise geometric location at which a vector network analyzer measurement is made is called the 6 reference plane. There are sometimes two different reference planes involved in a connector measurement. 7
If a commercial coaxial calibration kit is used, it will typically establish a reference plane near the end of 8 the test cables. In this case, a secondary calibration is needed to remove the influence of the test fixture 9
and move the reference plane closer to the DUT. 10
11 One key property of the reference plane is it is far enough from geometric transitions such as vias that 12
ephemeral modes die out before reaching the reference plane. The footprint is measured as part of the 13 DUT. The recommended reference plane VNA Settings (see Table 5-1) for Measuring Intel UPI 2.0 Cable 14
Assembly position is 50 mils from any geometric transition, e.g., signal trace to connector/via/anti-pad, 15 signal trace to baseboard pad/anti-pad or signal trace to edge finger/anti-pad. 16
17
5.2.5 Time Domain Reflectometry Tuning 18
Impedance measurements are obtained using TDR measurements. Two critical requirements must be tuned 19
before carrying out a TDR measurement: 20 21
De-skewing cables ensure the arrival of the TDR pulse at the end of the cables within appropriate delay, 22
minimizing common mode effects in the measurement. 23
1. Connect the cables to the channels of the TDR instrument and leave them in an open circuit 24
configuration, Ο= 1. 25
26
Figure 5-4 Open Circuit Configuration 27
2. Carry on the settings that were used to get the rise time of 15 psec at the reference plane of the 28
half primary through. 29
3. Under Setup> TDR configure the individual channels to form the differential channel. 30
31
For example, if using C1 and C2 as a differential channel, then set C1 as a rising edge and C2 as a falling 32 edge. 33
a. Turn ON the TDR step and acquisition for both the channels. 34 b. Change the units of both the channels to rho (Ο). 35
36
Rise time verification: The equipment must have an approximate rise time of the TDT step. TDR modules 37 must enable a 15 ps rise time (20-80%) at the reference plane. To measure the differential impedance, 38
two channels used as excitation (TDR pulse) must be de-skewed (in differential mode). See Appendix C. 39 40
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5.2.6 Fixture Intra-pair Skew 1
DUT (Device Under Test) skew is obtained using VNA measurement data. In order to capture the inter-pair 2
skew properly, the following procedures are recommended to estimate fixture skew. 3 4
1. Perform SOLT calibration at the VNA cable ends. 5
2. Measure RL on test boards as shown in the following figure. Note that DUT is not assembled, and 6 the board is open at the pads where DUT is to be placed. 7
3. Convert RL of a differential pair in FD (frequency-domain) into TDR in TD (time-domain) to 8
obtain the TDR, use a step voltage for the stimulus with the rise time (20-80%) defined for 9
impedance testing. 10
11
12
Figure 5-5 RL Measurement from Test Fixtures 13
14
4. Measure the fixture skew of fixtures using TDR, DF = [(TP-TN)/2]. 15
16
17
Figure 5-6 TDR Obtained via FD to TD Conversion of RL of a Differential Pair 18
19
5. Calculate fixture skew by adding average βFixture Aβ skew and average βFixture Bβ skew while 20 retaining the of Fixture skew values. Note that this addition should be done per differential signal 21
path without mixing different pairs. 22
6. Round Fixture skew using the following rule: 0 ps to 1 ps = 1 ps, 1 ps to 2 ps = 2 ps; -1 ps to 0 23
ps = -1 ps, -2 ps to -1 ps = -2 ps. 24
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7. Record fixture skew. 1
2
5.2.7 Flight Time 3
Measure flight time to obtain the actual flight time offset between the primary through and each secondary 4
line for the TRL calibration. The time of flight is measured using a TDT measurement following the 5
procedure shown below: 6
1. Make sure the TDR instrument is properly compensated at room temperature. 7
2. Set the screen scale to capture 50 ps/div and leave the acquisition mode to average. 8
3. Set one channel as the driver and the other the receiver. 9
4. Capture the primary through and save the waveform as a reference. 10
5. Connect the channels to Secondary 1 and capture the waveform and measure the flight time 11 difference between Primary Through and the Secondary 1 (reference to 20% of the maximum 12
voltage). 13
6. Repeat Step 4 for Secondary 2 and 3. 14
7. Record the flight time offsets of the secondary lines for TRL calibration. 15
8. Compare to design values. 16
9. Use measured delay values for TRL calibration. 17
18
Table 5-2 CYLLENE Mated Cable Evaluation Board TRL Calibration Launch Position vs TRL Line 19
Launch Connector Pair Calibration Line
J_HPRIM_A - J_HPRIM_B PRIMARY THRU β 2.621β
J_PRIM_A - J_PRIM_B HALF PRIMARY THRU - 1.3105β
J_SHORT SHORT - 1.3105β
J_SEC1A - J_SEC1B SECONDARY 1 - 4.0607β / 207.6 ps / 0.4 GHz - 2.0 GHz
J_SEC2A - J_SEC2B SECONDARY 2 β 2.9089β / 41.5 ps / 2.0 GHz - 10 GHz
J_SEC3A - J_SEC3B SECONDARY 3 β 2.6786β / 8.3 ps / 10 GHz - 50 GHz
J_CAL_A - J_CAL_B CAL CHECK 3.197β
J_LOAD LOAD 5.242β
20
5.2.8 Calibration Verification 21
5.2.8.1 Secondary Line Phase Margin 22
Verify secondary line phase margin on new boards. The phase plot should be linear over the secondary line 23
frequency range. Secondary line phase margin should be greater than 20 degrees. 24
5.2.8.2 Calibration Stability 25
Verify the stability of the calibration using the insertion loss measurement of the primary through before 26 and after completing the test plan. Absolute value of primary through loss |S21| after TRL calibration should 27
be β€ 0.1 dB up to 18 GHz and β€ 0.2 dB above 18 GHz. 28
5.2.8.3 Dynamic Range 29
Verify the dynamic range is large enough to capture the crosstalk. The noise floor measurement is a 30
crosstalk measurement between two distant traces. The crosstalk reading is the noise floor, which is the 31 lower boundary of the dynamic range the VNA in use can support after the calibration. The noise floor 32
should be less than -50 dB up to 8 GHz and less than -40 dB up to 18 GHz. 33
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5.2.8.4 Check System Reference Impedance 1
Some tools do not correctly handle S-parameters with reference impedances other than 50 ohms. If using 2
a reference impedance other than 50 ohms, check that the tool correctly recognizes the reference 3 impedance used in the measurement. If using S-parameters to obtain the TDR result, examine the 4
impedance in the time domain to ensure the target impedance is being correctly interpreted by the tool. 5
For example, if measuring 85 ohm connectors, TDR impedance should be around 85 ohms. 6 Helpful tips: 7
Make a copy of the touchstone file. 8
Edit the R parameter to change the stated reference impedance. 9
Reload the data into the tool. 10
Check that the tool recognizes the change by comparing insertion loss plots. 11
If the tool recognizes the change, the tool is working correctly. 12
If the tool does not recognize the change, the data must be normalized to 50 ohm reference 13
impedance before using the tool. 14
The reference impedance is the impedance of the TRL calibration lines on the board, which may 15 not be 50 ohms. The VNA may report a default value of 50 ohms regardless of the TRL line 16
impedance. 17 18
WARNING: IF THE VNA DOES NOT REPORT THE CORRECT REFERENCE IMPEDANCE, EDIT THE TOUCHSTONE 19
FILE SO THAT IT ACCURATELY STATES THE CORRECT REFERENCE IMPEDANCE. 20 21
Always distribute data files normalized to 50 ohm reference impedance. 22
Use actual measurement data to compare measurement to modeled cable performance 23
24
5.2.8.5 TRL Four Port Calibration 25
A TRL calibration is intended to remove the effect of the fixture moving the reference plane to closest 26
proximity to the fixed connector. The TRL calibration has the advantage that it can be easily tailored to 27 impedances other than 50 ohms and can eliminate the need for de- embedding the test fixture. It has the 28
disadvantage that it is not available on all machines and is not as familiar to many users as other calibration 29 methods. 30
1. To remove previous data in the memory, reboot the VNA instrument. 31
32
WARNING: FAILURE TO REBOOT CAN RESULT IN UNSTABLE/ UNUSABLE TRL CALIBRATION. 33 34
2. Set the start and stop frequencies for the TRL calibration in the instrument. Is important to notice 35
that the maximum frequency it is given by the Allen Test described previously. 36
3. Set frequency step size to 10 MHz, number of averages to three, smoothing off, power to 0 dBm 37
and IF bandwidth to 1 kHz. 38
4. For a (1,3;2,4) VNA configuration when performing a TRL calibration, set 1-2 and 3-4 as a defined 39
Through and 2-3 and 1-4 as an unknown Through. 40
5. Load the calibration file in the equipment for Keysight. 41
6. Open the calibration wizard in the calibration menu and select smart calibration, (when using a 42
Keysight VNA) and select 4 port calibration. 43
7. Select the calibration file for the Intel UPI connector. 44
8. Define the ports and run the calibration making the connections on the calibration fixture on 45
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CYLLENE board (as described in Table 5-1 VNA Equipment Settings) following the wizard 1 instructions. 2
9. Take notes of the delays and save the calibration. See Appendix B βVNA TRL Calibrationβ for more 3
details. 4
6. Frequency Domain Measurement 5
6.1 Port Naming Convention 6
Insertion and return loss are multi-port measurements using the port naming convention in the following 7
figure. All differential pairs other than those being measured need to be terminated. Since wide band 42.5 8 ohm terminators do not exist, adjacent unused measurement ports can be terminated with 50 ohm 9
terminators. 10 11
The measured S-parameter should be referenced to 85 ohm differential impedance for compliance check 12
against the cable assembly specification. 13 14
15
Figure 6-1 VNA Port Naming Convention Example 16
17
18
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6.2 Fixed Connector Termination During Measurement 1
2
Figure 6-2 Mated Cable Assembly Evaluation Board Pin Termination: RAR, VR 3
4
6.3 Differential Insertion Loss (SDD21) 5
Differential insertion loss is calculated using the following equation shown below where S is formatted as 6
a complex number. 7 8
Calculation of differential insertion loss SDD21 presuming ports 1 and 3 are driven, ports 2 and 4 are 9
outputs is shown in Equation 6-1. 10 11
Equation 6-1 Calculations for SDD21 12
ππ·π·21(ππ΅) = 20 πππ10 [|π21 + π43 β π23 β π41|
2] 13
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1
6.4 Differential Return Loss (SDD11 and SDD22) 2
Differential return loss is calculated using the following equation shown below where S is formatted as a 3 complex number. 4
5
Calculation of differential return loss SDD11 presuming ports 1 and 3 are driven, ports 2 and 4 are outputs 6 is shown in Equation 6-2. 7
8
Equation 6-2 Calculations for SDD11 and SDD22 9
ππ·π·11(ππ΅) = 20 πππ10 [|π11 + π33 β π13 β π31|
2] 10
ππ·π·22(ππ΅) = 20 πππ10 [|π22 + π44 β π24 β π42|
2] 11
12
The configuration of the cable assembly to carry out the differential measurements of insertion and return 13 loss are shown in the following figures. 14
15
16
Figure 6-3 Vertical MCIO to Vertical MCIO, Insertion Loss/Return Loss, Tx to Rx Cable 17
18
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1
Figure 6-4 Vertical MCIO to RA MCIO Tx to Rx Cable 2
3
4
Figure 6-5 Right Angle MCIO to Right Angle MCIO, Insertion Loss/Return Loss, Tx to Rx Cable 5
6
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6.5 Crosstalk Measurement 1
Differential power sum crosstalk is calculated using the following equations shown below where S is 2
formatted as a complex number. 3
6.5.1 Single-aggressor Near-end Crosstalk (DDNEXT) 4
5
Differential single-aggressor near end crosstalk (DDNEXT) on the victim differential pair is calculated by 6 the following formula. 7
8
Equation 6-3 Calculations for DDNEXT 9
π·π·ππΈππ(ππ΅) = 20 πππ10 [|π21 + π43 β π23 β π41|
2] 10
11
6.5.2 Multi-Disturber Near-end Crosstalk (MDNEXT) 12
13 Multi-Disturber Near-End Crosstalk (MDNEXT) on the victim differential pair is calculated as a power sum 14
using the following equation shown below where MDNEXT(f) is expressed in dB. 15
16
Equation 6-4 Calculations for MDNEXT 17
ππ·ππΈππ (π) = 10 πππ10 (β 10π·π·ππΈππ(π)
10
π) |π=1,2,3 18
19 The configuration of the cable assembly to carry out the differential measurements of insertion and return 20
loss are shown in the following figures. 21 22
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1
Figure 6-6 Vertical Receptacle, NEXT RX Victim 2
3
4
Figure 6-7 Right Angle Receptacle, NEXT RX Victim, Tx to Rx Cable 5
6
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6.6 Far End Crosstalk 1
6.6.1 Single-aggressor Far-End Crosstalk (DDFEXT) 2
3
Differential single-aggressor far end crosstalk (DDFEXT) on the victim differential pair is calculated by the 4 following formula. 5
6
Equation 6-5 Calculations for DDFEXT 7
π·π·πΉπΈππ(ππ΅) = 20πππ10 [|π21 + π43 β π23 β π41|
2] 8
9
6.6.2 Multi-Disturber Far-End Crosstalk (MDFEXT) 10
Multi-Disturber Far-End Crosstalk (MDFEXT) on the victim differential pair is calculated as a power sum 11 using the following equation shown below where MDFEXT(f) is expressed in dB. 12
13
Equation 6-6 Calculations for MDFEXT 14
ππ·πΉπΈππ (π) = 10 πππ10 (β 10π·π·πΉπΈππ(π)
10
π) |π=1,2,3 15
16
The configuration of the cable assembly to carry out the differential measurements of insertion and return 17 loss are shown in the following figures. 18
19
20
Figure 6-8 Vertical to Vertical, FEXT Rx Victim, Tx to Rx Cable 21
22
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1
Figure 6-9 Vertical to Right Angle, FEXT Rx Victim, Tx to Rx Cable 2
3
4
Figure 6-10 Vertical to Right Angle, FEXT Rx Victim, Tx to Rx Cable 5
6
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6.7 MDFEXT Without Fixture FEXT (MDFEXTwoff) 1
Test boards may include fixture FEXT contributions that might be significant to verification assessments. 2
Fixture FEXT may be removed using these steps: 3 1. Identify the worst case single-aggressor DDFEXT measurement including fixture, DDFEXTwc. 4
2. Identify the insertion loss measurement of the victim position, SDD21v. 5
3. Identify the fixture FEXT measurement, FEXTspider. 6 4. Subtract fixture FEXT from worse case aggressor (DDFEXTwcawf) as shown in Equation 6-7. 7
8
Equation 6-7 Calculations for DDFEXTwc Without Fixture FEXT 9
π·π·πΉπΈπππ€πππ€π = 20 πππ10(|π·π·πΉπΈπππ€π β (ππ·π·21π£ π₯ πΉπΈπππ πππππ)|) 10
11 5. Calculate multi-aggressor FEXT without fixture FEXT (MDFEXTwoff) as shown in Equation 6-8 12
where N is the number of lesser aggressors and MDFEXTwoff is expressed in dB. 13 14
Equation 6-8 Calculations for MDFEXT Without Fixture FEXT 15
ππ·πΉπΈπππ€πππ(π) = 10 πππ10 (10π·π·πΉπΈπππ€πππ€π
10 + β 10π·π·πΉπΈπππ
10
π) |π = 1,2,β¦π 16
17
6.8 Effective Intra-Pair Skew (EIPS) 18
The effective skew calculation starts from the frequency domain skew, which is captured from the modified 19 mixed-mode insertion loss. The modified mixed-mode insertion loss relates the differential input to the 20
single-ended output while accounting for the coupling within a differential pair properly. The modified 21
mixed-mode insertion loss, S2d1, and S4d1, which relate the differential input to the single-ended outputs 22 within a 4-port system, are depicted in Figure 6-11. The intra-pair skew addition mechanism is illustrated 23
in Figure 6-12. 24 25
26
Figure 6-11 Modified Mixed-Mode Insertion Loss, S2d1 and S4d1 27
28
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1
Figure 6-12 Intra-Pair Skew Introduction to a 4-Port System 2
3 The modified mixed-mode insertion loss can be represented by the single-ended S-parameter equations. 4
5
Equation 6-9 Calculations for S2d1 and S4d1 6
π2π1 =1
β2β (π21 β π23) 7
π4π1 =1
β2β (π43 β π41) 8
9
The frequency domain skew, skew(f) is obtained by calculating the difference between two phase delays. 10 11
Equation 6-10 Calculations for Skew 12
βπ‘1 = βπ’ππ€πππ(πβππ π(π2π1))
2ππβ 13
βπ‘2 = βπ’ππ€πππ(πβππ π(π4π1))
2ππβ 14
π πππ€(π) = βπ‘1 β βπ‘2 15
16
The calculated frequency domain skew is multiplied by a weighting function, which is the product of power 17 spectral density of the random binary sequence and skew impact on the normalized mode conversion. EIPS 18
is the weighted frequency domain skew and is integrated over the frequency region up to 1.5Γ(Nyquist 19 frequency), 20
Equation 6-11 Calculations for Effective Intra-pair Skew 21
πΈπΌππ = β« π(π)ππππ₯
ππππ
β |π πππ€(π)|ππ 22
π(π) =
(|πππ21 β πππ21|ππππππ‘ππ ππ¦ π πππ€πππ₯β |πππ21 β πππ21|0 ππ ππ π πππ€ ) Γ π πππ2 (
2ππππ
) Γ1
1 + (πππ‘
)4 Γ
1
1 + (πππ
)8
β« (|πππ21|ππππππ‘ππ ππ¦ π πππ€πππ₯β |πππ21|0 ππ ππ π πππ€ ) Γ π πππ2 (
2ππππ
) Γ1
1 + (πππ‘
)4 Γ
1
1 + (πππ
)8
ππππ₯
ππππππ
23
β¦ where fmax is set at 1.5Γ(Nyquist frequency, fN). 24
25 Calculate |Scd21-Sdd21|impacted by skewmax in dB. First calculate maximum skew in magnitude over the 26
frequency of interest, up to 1.5ΓfN and calculate |Scd21- Sdd21|impacted by skewmax in dB from the S-27 parameter matrix shown below. 28
29
DRAFT SFF-TA-1024 Rev 0.0.2 Template Rev 1.0
Test Procedure for SFF-TA-1016 Mated Cable Assembly Page 38
Copyright Β© 2021 SNIA. All rights reserved.
Equation 6-12 S-parameter Matrix for Calculationg Maximum Skew 1
[
π11π21π31
π41ππ2πππ πππ€πππ₯
π12π22π32
π42
π13π23π33
π43ππ2πππ πππ€πππ₯
π14ππ2πππ πππ€πππ₯ π24
π34ππ2πππ πππ€πππ₯ π44
] 2
3
6.9 Effective Pair-to-Pair Skew (EPPS) 4
5 The Effective Pair-to-Pair Skew (EPPS) is the flight time delta between two differential pairs. The flight time 6
is captured from phase delay, which is captured from differential insertion loss, 7 8
9
Figure 6-13 2 Differential Pair Port Map 10
11
Equation 6-13 Calculations for Pair-to-Pair Skew 12
βππππβπ‘_π‘πππ1 = βπ’ππ€πππ(πβππ π(πππ12))
(2ππ)β 13
βππππβπ‘_π‘πππ2 = βπ’ππ€πππ(πβππ π(πππ34))
(2ππ)β 14
pair-to-ππππ π πππ€(π) = βππππβπ‘_π‘πππ1(π) β βππππβπ‘_π‘πππ2(π) 15
16 β¦ where Sdd12 and Sdd34 are insertion loss which can be calculated from single-ended S-parameters as 17
shown below. 18 19
Equation 6-14 Calculations for Insertion Loss, Sdd12 and Sdd34 20
πππ12 = 12β β (π21 β π41 β π23 + π43) 21
πππ34 = 12β β (π65 β π85 β π67 + π87) 22
23
Once frequency domain skew is calculated, the calculated frequency domain skew is multiplied by a 24 weighting function which is the power spectral density of a random binary sequence. Effective Pair-to-Pair 25
Skew (EPPS) is obtained by integrating the weighted frequency domain skew over the frequency region up 26 to 1.5Γ(Nyquist frequency, fN). 27
28
Equation 6-15 Calculations for Effective Pair-to-Pair Skew 29
π¬πππ = β« π(π)ππππ₯
ππππ
β |π πππ€(π)|ππ 30
π(π) =π πππ2 (
2ππππ
β )
β« π πππ2ππππ₯
ππππ(
2ππππ
β ) ππ 31
β¦ where fmax is set at 1.5Γ(Nyquist frequency, fN). 32
33
DRAFT SFF-TA-1024 Rev 0.0.2 Template Rev 1.0
Test Procedure for SFF-TA-1016 Mated Cable Assembly Page 39
Copyright Β© 2021 SNIA. All rights reserved.
6.10 Mated Cable Assembly Skew Measurement 1
2
1. Insert cable assembly into the test fixtures for the full channel measurement. The test set up is 3 depicted in the following figure. 4
5
6
Figure 6-14 Skew Measurement Test Set 7
8
2. Capture the test set intra-pair skew from IL measurement of each differential pair in the test plan, 9 defined as 'test set skew'. The test set skew is calculated using the equations as shown below and 10
the maximum value over the frequency range is picked. 11
12
Equation 6-16 Calculations for Test Set Skew 13
πΉππππ πππ€ = πππ£ππππ΄π£πππππ (πβππ ππππππ¦1β πβππ ππππππ¦2) 15
β¦ for 5 GHz β€ f β€ 24 GHz, where β¦ 14
πβππ ππππππ¦1 =π’ππ€πππ(πππππ(π2π·1))
2ππβ 16
πβππ ππππππ¦2 =π’ππ€πππ(πππππ(π4π·1))
2ππβ 17
β¦ and β¦ 18
π2π·1 = 1β2
β (π21 β π23) 19
π4π·1 = 1β2
β (π43 β π41) 20
21
The window size of the moving average is 100 points. 22 23
3. Calculate DUT skew by subtracting absolute value of rounded fixture skew from absolute value 24 of the test set skew. 25
26
6.11 Impedance Measurement 27
6.11.1 Rise Time 28
Ensure a 15 psec (20-80%) rise time is achieved at the end of the half primary through such that the 29
proper rise time is set at the reference plane. 30 31
6.11.2 Instantaneous Impedance 32
For a given 85 Β± Zi Ohm instantaneous impedance specification one would evaluate as follows. 33 34
DRAFT SFF-TA-1024 Rev 0.0.2 Template Rev 1.0
Test Procedure for SFF-TA-1016 Mated Cable Assembly Page 40
Copyright Β© 2021 SNIA. All rights reserved.
1
Figure 6-15 Instantaneous Impedance Example 2
3
6.11.3 Average Impedance 4
For a given 85 Β± Za Ohm average impedance specification one would evaluate as follows 5 6
7
Figure 6-16 Average Impedance Example 8
9
DRAFT SFF-TA-1024 Rev 0.0.2 Template Rev 1.0
Test Procedure for SFF-TA-1016 Mated Cable Assembly Page 41
Copyright Β© 2021 SNIA. All rights reserved.
7. Test Plans 1
7.1 Vertical Receptacle to Vertical Receptacle, MCA Measurement, Rx to Tx 2
Cable 3
Table 7-1 VR to VR Test Plan 4
5
Test O
bje
ctive
Calib
ration T
ype
Equip
Test #
Gro
up
VN
A P
ort
1 -
IN
VN
A P
ort
3 -
INV
NA
Port
2 -
OU
TV
NA
Port
4 -
OU
T
Cable
PLU
G 2
= C
able
PO
RT
2 =
P2 =
p2
Cable
PLU
G 1
= C
able
PO
RT
1 =
P1 =
p2
De
lay M
ea
sV
NA
ALLE
N1
J4
J6
ALLE
Ncheck IL S
TO
P f
req o
f accepta
ble
TR
L c
al
De
lay M
ea
sV
NA
ALLE
N2
J4
J6
ALLE
Ncheck IL S
TO
P f
req o
f accepta
ble
TR
L c
al
Ris
e T
ime
Me
as
TD
TC
AL1
J8
J11
CA
LH
ALF
TH
RU
, ve
rify
23 p
s r
ise tim
e , 2
0%
-80%
De
lay M
ea
sT
DT
CA
L2
J3
J5
CA
LS
EC
_1 T
RLD
ela
y in
put
De
lay M
ea
sT
DT
CA
L3
J9
J10
CA
LS
EC
_2 T
RL D
ela
y in
put
De
lay M
ea
sT
DT
CA
L4
J13
J15
CA
LS
EC
_3T
RL D
ela
y in
put
TR
LV
NA
CA
L5
J4
J6
CA
LP
RIM
AR
Y T
HR
OU
GH
- IL m
easure
ment qualit
y check
TR
LV
NA
CA
L6
J4
J6
CA
LP
RIM
AR
Y T
HR
OU
GH
-IL
measure
ment qualit
y check
TR
LV
NA
CA
L7
J14
J16
CA
LC
AL C
HE
CK
-IL
m
easure
ment qualit
y check
TR
LV
NA
CA
L8
J14
J16
CA
LC
AL C
HE
CK
-IL
measure
ment qualit
y check
TR
LV
NA
CA
L9
J48
J41
J42
J47
CA
LN
OIS
E F
LO
OR
measure
ment usin
g IL
TR
LV
NA
CA
L10
J48
J41
J45
J49
CA
LF
IXT
UR
E F
EX
T m
easure
ment
TR
LV
NA
1J33-P
ER
n3
J30-P
ER
p3
J3
9-P
ET
n3
J3
6-P
ET
p3
IL / R
LT
HR
OU
GH
1
TR
LV
NA
2J32-P
ER
n2
J29-P
ER
p2
J3
8-P
ET
n2
J3
5-P
ET
p2
IL / R
LT
HR
OU
GH
2
TR
LV
NA
3J34-P
ER
n4
J31-P
ER
p4
J4
0-P
ET
n4
J3
7-P
ET
p4
IL / R
LT
HR
OU
GH
3
TR
LV
NA
4J39-P
ET
n3
J36-P
ET
p3
J3
3-P
ER
n3
J3
0-P
ER
p3
IL / R
LT
HR
OU
GH
4
TR
LV
NA
5J38-P
ET
n2
J35-P
ET
p2
J3
2-P
ER
n2
J2
9-P
ER
p2
IL / R
LT
HR
OU
GH
5
TR
LV
NA
6J40-P
ET
n4
J37-P
ET
p4
J3
4-P
ER
n4
J3
1-P
ER
p4
IL / R
LT
HR
OU
GH
6
TR
LV
NA
7J3
3-P
ER
n3
J3
0-P
ER
p3
J3
9-P
ET
n3
J3
6-P
ET
p3
NE
XT
PS
NE
XT
, V
ert
ical-T
x V
ictim
(pair 1
)
TR
LV
NA
8J3
2-P
ER
n2
J2
9-P
ER
p2
J3
9-P
ET
n3
J3
6-P
ET
p3
NE
XT
PS
NE
XT
, V
ert
ical, T
x-vi
ctim
(pair 2
)
TR
LV
NA
9J3
4-P
ER
n4
J3
1-P
ER
p4
J3
9-P
ET
n3
J3
6-P
ET
p3
NE
XT
PS
NE
XT
, V
ert
ical, T
x-vi
ctim
(pair 3
)
TR
LV
NA
8J3
9-P
ET
n3
J3
6-P
ET
p3
J3
3-P
ER
n3
J3
0-P
ER
p3
NE
XT
PS
NE
XT
, V
ert
ical-R
x V
ictim
(pair 1
)
TR
LV
NA
9J3
8-P
ET
n2
J3
5-P
ET
p2
J3
3-P
ER
n3
J3
0-P
ER
p3
NE
XT
PS
NE
XT
, V
ert
ical-R
x V
ictim
(pair2)
TR
LV
NA
10
J4
0-P
ET
n4
J3
7-P
ET
p4
J3
3-P
ER
n3
J3
0-P
ER
p3
NE
XT
PS
NE
XT
, V
ert
ical-R
x V
ictim
(pair 3
)
TR
LV
NA
11
J3
4-P
ER
n4
J3
1-P
ER
p4
J39-P
ET
n3
J36-P
ET
p3
FE
XT
PS
FE
XT
, V
ert
ical-R
x V
ictim
(pair 1
)
TR
LV
NA
12
J3
2-P
ER
n2
J2
9-P
ER
p2
J39-P
ET
n3
J36-P
ET
p3
FE
XT
PS
FE
XT
, V
ert
ical-R
x V
ictim
(pair 2
)
TR
LV
NA
11
J4
0-P
ET
n4
J3
7-P
ET
p4
J33-P
ER
n3
J30-P
ER
p3
FE
XT
PS
FE
XT
, V
ert
ical-R
x V
ictim
(pair 1
)
TR
LV
NA
12
J3
8-P
ET
n2
J3
5-P
ET
p2
J33-P
ER
n3
J30-P
ER
p3
FE
XT
PS
FE
XT
, V
ert
ical-R
x V
ictim
(pair 2
)
TR
LV
NA
CA
L11
J_P
RIM
_A
JP
RIM
_B
CA
LP
RIM
AR
Y T
HR
OU
GH
- IL m
easure
ment qualit
y check
TR
LV
NA
CA
L12
J_P
RIM
_A
JP
RIM
_B
CA
LP
RIM
AR
Y T
HR
OU
GH
-IL
measure
ment qualit
y check
Test O
bje
ctive
Calib
ration T
ype
Equip
Test #
Gro
up
TD
R Input/T
DT
Input
(+ =
+ s
ide o
f T
DR
T
DT
Outp
ut
Board
Com
bin
ations
Test F
ile o
utp
ut
Test T
ype
Com
ments
(+
= +
sid
e o
f T
DR
head)
Cal
receiv
er
and
transm
itte
r deskew
TD
R
Pre
-Cal check
n/a
deskew
receiv
er
and tra
nsm
itte
r (inclu
din
g b
oard
)
Cal
Edge r
ate
(E
R)
check
TD
TC
AL 1
3P
re-m
easure
Calib
ration
J8
J11
CY
LLE
NE
VR
ER
TD
RJ33
J30
ER
TD
RJ32
J29
ER
TD
RJ34
J31
ER
TD
RJ39
J36
ER
TD
RJ38
J35
ER
TD
RJ40
J37
CA
LE
dge r
ate
(E
R)
check
TD
TC
AL 1
4
J8
J11
CY
LLE
NE
VR
PS
NE
XT
(VR
-Tx
Vic
tim
)
PS
FE
XT
(VR
-Tx
Vic
tim
)
Diffe
rential
Impedance
*.csv (voltage, time, impedance)
p
ositiv
e a
nd n
egative
input, c
heck r
ise tim
e a
t re
f pla
ne
positiv
e a
nd n
egative
input, c
heck r
ise tim
e a
t re
f pla
ne
13
Diffe
rential
Impedance
14
Diffe
rential
Impedance
15
Diffe
rential
Impedance
16
PS
FE
XT
(VR
-Rx
Vic
tim
)
Diffe
rential
Impedance
CYL
LEN
E V
R
17
12
Diffe
rential
Impedance
CY
LLE
NE
VR
Post
Measurmen
t
Cal check
Post-
Measure
Cal C
heck
MCIO VR-VR Mated Cable Measurement
IL/R
L
PS
NE
XT
(VR
-Rx
Vic
tim
)
Measurement, Model Correlation
Troubleshooting (Compliance Excursion,
Impedance Profile Characterization),
23 ps at the ref plane, 20-80%
Cyllen
e V
R (
Vert
ical R
ecep
tacle
Ro
ot)
, C
ylle
ne V
R (
Vert
ical R
ecepta
cle
Targ
et)
Pre
-Cal N
ois
e C
heck
Pre
-Cal
Check
Test Cable & Fixture Check
Pre
-measure
Calib
ration
B1
9
A1
IN IN
OU
T
OU
T
DRAFT SFF-TA-1024 Rev 0.0.2 Template Rev 1.0
Test Procedure for SFF-TA-1016 Mated Cable Assembly Page 42
Copyright Β© 2021 SNIA. All rights reserved.
7.2 Vertical Receptacle to RA Receptacle, MCA Measurement, Rx to Tx Cable 1
Table 7-2 VR to RA Test Plan 2
3
Test O
bje
ctive
Calib
ration T
ype
Equip
Test #
Gro
up
VN
A P
ort
1 -
IN
VN
A P
ort
3 -
INV
NA
Port
2 -
OU
TV
NA
Port
4 -
OU
TT
est T
ype
Cable
PLU
G 2
= C
able
PO
RT
2 =
P2 =
p2
Cable
PLU
G 1
= C
able
PO
RT
1 =
P1 =
p2
De
lay M
ea
sV
NA
ALLE
N1
J4
J6
ALLE
Ncheck IL S
TO
P f
req o
f accepta
ble
TR
L c
al
De
lay M
ea
sV
NA
ALLE
N2
J4
J6
ALLE
Ncheck IL S
TO
P f
req o
f accepta
ble
TR
L c
al
Ris
e T
ime
Me
as
TD
TC
AL1
J8
J11
CA
LH
ALF
TH
RU
, ve
rify
23 p
s r
ise tim
e , 2
0%
-80%
De
lay M
ea
sT
DT
CA
L2
J3
J5
CA
LS
EC
_1 T
RLD
ela
y in
put
De
lay M
ea
sT
DT
CA
L3
J9
J10
CA
LS
EC
_2 T
RL D
ela
y in
put
De
lay M
ea
sT
DT
CA
L4
J13
J15
CA
LS
EC
_3T
RL D
ela
y in
put
TR
LV
NA
CA
L5
J4
J6
CA
LP
RIM
AR
Y T
HR
OU
GH
- IL m
easure
ment qualit
y check
TR
LV
NA
CA
L6
J4
J6
CA
LP
RIM
AR
Y T
HR
OU
GH
-IL
measure
ment qualit
y check
TR
LV
NA
CA
L7
J14
J16
CA
LC
AL C
HE
CK
-IL
m
easure
ment qualit
y check
TR
LV
NA
CA
L8
J14
J16
CA
LC
AL C
HE
CK
-IL
measure
ment qualit
y check
TR
LV
NA
CA
L9
J48
J41
J42
J47
CA
LN
OIS
E F
LO
OR
measure
ment usin
g IL
TR
LV
NA
CA
L10
J48
J41
J45
J49
CA
LF
IXT
UR
E F
EX
T m
easure
ment
TR
LV
NA
1J
33
-PE
Rn
3J
30
-PE
Rp
3J2
7-P
ET
n3
J2
4-P
ET
p3
IL / R
LT
HR
OU
GH
1
TR
LV
NA
2J
32
-PE
Rn
2J
29
-PE
Rp
2J2
6-P
ET
n2
J2
3-P
ET
p2
IL / R
LT
HR
OU
GH
2
TR
LV
NA
3J
34
-PE
Rn
4J
31
-PE
Rp
4J2
8-P
ET
n4
J2
5-P
ET
p4
IL / R
LT
HR
OU
GH
3
TR
LV
NA
4J
39
-PE
Tn
3J
36
-PE
Tp
3J2
1-P
ER
n3
J1
8-P
ER
p3
IL / R
LT
HR
OU
GH
4
TR
LV
NA
5J
38
-PE
Tn
2J
35
-PE
Tp
2J2
0-P
ET
n2
J1
7-P
ET
p2
IL / R
LT
HR
OU
GH
5
TR
LV
NA
6J
40
-PE
Tn
4J
37
-PE
Tp
4J2
2-P
ER
n4
J1
9-P
ER
p4
IL / R
LT
HR
OU
GH
6
TR
LV
NA
7J
33
-PE
Rn
3J
30
-PE
Rp
3J
39
-PE
Tn
3J
36
-PE
Tp
3N
EX
TP
SN
EX
T, V
ert
ical-R
x V
ictim
(pair 1
)
TR
LV
NA
8J
32
-PE
Rn
2J
29
-PE
Rp
2J
39
-PE
Tn
3J
36
-PE
Tp
3N
EX
TP
SN
EX
T, V
ert
ical-R
x V
ictim
(pair2)
TR
LV
NA
9J
34
-PE
Rn
4J
31
-PE
Rp
4J
39
-PE
Tn
3J
36
-PE
Tp
3N
EX
TP
SN
EX
T, V
ert
ical-R
x V
ictim
(pair 3
)
TR
LV
NA
10
J2
1-P
ER
n3
J1
8-P
ER
p3
J2
7-P
ET
n3
J2
4-P
ET
p3
NE
XT
PS
NE
XT
, V
ert
ical-R
x V
ictim
(pair 1
)
TR
LV
NA
11
J2
0-P
ET
n2
J1
7-P
ET
p2
J2
7-P
ET
n3
J2
4-P
ET
p3
NE
XT
PS
NE
XT
, V
ert
ical-R
x V
ictim
(pair2)
TR
LV
NA
12
J2
2-P
ER
n4
J1
9-P
ER
p4
J2
7-P
ET
n3
J2
4-P
ET
p3
NE
XT
PS
NE
XT
, V
ert
ical-R
x V
ictim
(pair 3
')
TR
LV
NA
7J
39
-PE
Tn
3J
36
-PE
Tp
3J
33
-PE
Tn
3J
30
-PE
Tp
3N
EX
TP
SN
EX
T, V
ert
ical-R
x V
ictim
(pair 1
)
TR
LV
NA
8J
38
-PE
Tn
3J
35
-PE
Tp
3J
33
-PE
Tn
3J
30
-PE
Tp
3N
EX
TP
SN
EX
T, V
ert
ical-R
x V
ictim
(pair2)
TR
LV
NA
9J
40
-PE
Tn
3J
37
-PE
Tp
3J
33
-PE
Tn
3J
30
-PE
Tp
3N
EX
TP
SN
EX
T, V
ert
ical-R
x V
ictim
(pair 3
)
TR
LV
NA
10
J2
7-P
ET
n3
J2
4-P
ET
p3
J2
1-P
ER
n3
J1
8-P
ER
p3
NE
XT
PS
NE
XT
, V
ert
ical-R
x V
ictim
(pair 1
)
TR
LV
NA
11
J2
6-P
ET
n2
J2
3-P
ET
p2
J2
1-P
ER
n3
J1
8-P
ER
p3
NE
XT
PS
NE
XT
, V
ert
ical-R
x V
ictim
(pair2)
TR
LV
NA
12
J2
8-P
ET
n4
J2
5-P
ET
p4
J2
1-P
ER
n3
J1
8-P
ER
p3
NE
XT
PS
NE
XT
, V
ert
ical-R
x V
ictim
(pair 3
')
TR
LV
NA
13
J2
2-P
ER
n4
J1
9-P
ER
p4
J3
9-P
ET
n3
J3
6-P
ET
p3
FE
XT
PS
FE
XT
, R
A-R
x V
ictim
(pair 1
)
TR
LV
NA
14
J2
0-P
ET
n2
J1
7-P
ET
p2
J3
9-P
ET
n3
J3
6-P
ET
p3
FE
XT
PS
FE
XT
, R
A-R
x V
ictim
(pair 2
)
TR
LV
NA
15
J2
8-P
ET
n4
J2
5-P
ET
p4
J3
3-P
ER
n3
J3
0-P
ER
p3
FE
XT
PS
FE
XT
, R
A-R
x V
ictim
(pair 1
)
TR
LV
NA
16
J2
6-P
ET
n2
J2
3-P
ET
p2
J3
3-P
ER
n3
J3
0-P
ER
p3
FE
XT
PS
FE
XT
, R
A-R
x V
ictim
(pair 2
)
TR
LV
NA
13
J4
0-P
ET
n3
J3
7-P
ET
p3
J2
1-P
ER
n3
J1
8-P
ER
p3
FE
XT
PS
FE
XT
, R
A-R
x V
ictim
(pair 1
)
TR
LV
NA
14
J3
8-P
ET
n2
J3
5-P
ET
p2
J2
1-P
ER
n3
J1
8-P
ER
p3
FE
XT
PS
FE
XT
, R
A-R
x V
ictim
(pair 2
)
TR
LV
NA
15
J3
4-P
ER
n4
J3
1-P
ER
p4
J2
7-P
ET
n3
J2
4-P
ET
p3
FE
XT
PS
FE
XT
, R
A-R
x V
ictim
(pair 1
)
TR
LV
NA
16
J3
2-P
ER
n2
J2
9-P
ER
p2
J2
7-P
ET
n3
J2
4-P
ET
p3
FE
XT
PS
FE
XT
, R
A-R
x V
ictim
(pair 2
)
TR
LV
NA
CA
L11
J4
J6
CA
LP
RIM
AR
Y T
HR
OU
GH
- IL m
easure
ment qualit
y check
TR
LV
NA
CA
L12
J4
J6
CA
LP
RIM
AR
Y T
HR
OU
GH
-IL
measure
ment qualit
y check
Test O
bje
ctive
Calib
ration T
ype
Equip
Test #
Gro
up
TD
R Input/T
DT
Input
(+ =
+ s
ide o
f T
DR
T
DT
Outp
ut
Board
Com
bin
ations
Test F
ile o
utp
ut
Test T
ype
Com
ments
(+
= +
sid
e o
f T
DR
head)
Cal
receiv
er
and
transm
itte
r deskew
TD
R
Pre
-Cal check
n/a
deskew
receiv
er
and tra
nsm
itte
r (inclu
din
g b
oard
)
Cal
Edge r
ate
(E
R)
check
TD
TC
AL 1
3P
re-m
easure
Calib
ration
J8
J11
CY
LLE
NE
VR
ER
TD
RJ35
J36
ER
TD
RJ34
J33
ER
TD
RJ37
J38
ER
TD
RJ26
J25
ER
TD
RJ18
J17
ER
TD
RJ21
J22
CA
LE
dge r
ate
(E
R)
check
TD
TC
AL 1
4
J8
J11
CY
LLE
NE
VR
Cyllen
e V
T (
Vert
ical R
oo
t), C
ylle
ne R
AR
(R
ight A
ngle
Targ
et)
Pre
-Cal N
ois
e C
heck
Pre
-Cal
Check
positiv
e a
nd n
egative
input, c
heck r
ise tim
e a
t re
f pla
ne
18
Diffe
rential
Impedance
19
Diffe
rential
Impedance
20
Diffe
rential
Impedance
*.csv (voltage, time, impedance)
p
ositiv
e a
nd n
egative
input, c
heck r
ise tim
e a
t re
f pla
ne
17
Diffe
rential
Impedance
Diffe
rential
Impedance
22
Diffe
rential
Impedance
CY
LLE
NE
VR
CYL
LEN
E R
AR
Post-
Measure
Cal C
heck
Test Cable & Fixture Check
Pre
-measure
Calib
ration
PS
FE
XT
(VR
-Tx
Vic
tim
)
21
Post
Measurmen
t
Cal check
Measurement, Model Correlation
Troubleshooting (Compliance Excursion,
Impedance Profile Characterization),
23 ps at the ref plane, 20-80%
MCIO V-RAR Mated Cable Measurement
IL/R
L
PS
NE
XT
(VR
-Tx
Vic
tim
)
PS
NE
XT
(RA
R-T
x V
ictim
)
PS
NE
XT
(VR
-Rx
Vic
tim
)
PS
NE
XT
(RA
R-R
x V
ictim
)
PS
FE
XT
(RA
R-T
x V
ictim
)
PS
FE
XT
(RA
R-R
x V
ictim
)
PS
FE
XT
(VR
-Rx
Vic
tim
)
B1
9
A1
IN IN
OU
T
OU
T
DRAFT SFF-TA-1024 Rev 0.0.2 Template Rev 1.0
Test Procedure for SFF-TA-1016 Mated Cable Assembly Page 43
Copyright Β© 2021 SNIA. All rights reserved.
7.3 RA Receptacle to RA Receptacle, MCA Measurement, Rx to Tx Cable 1
Table 7-3 RA to RA Test Plan 2
3
Test O
bje
ctive
Calib
ration T
ype
Equip
Test #
Gro
up
VN
A P
ort
1 -
IN
VN
A P
ort
3 -
INV
NA
Port
2 -
OU
TV
NA
Port
4 -
OU
TT
est T
ype
Cable
PLU
G 2
= C
able
PO
RT
2 =
P2 =
p2
Cable
PLU
G 1
= C
able
PO
RT
1 =
P1 =
p2
Note
s
De
lay M
ea
sV
NA
ALLE
N1
J4
J6
ALLE
Ncheck IL S
TO
P f
req o
f accepta
ble
TR
L c
al
De
lay M
ea
sV
NA
ALLE
N2
J4
J6
ALLE
Ncheck IL S
TO
P f
req o
f accepta
ble
TR
L c
al
Ris
e T
ime
Me
as
TD
TC
AL1
J8
J11
CA
LH
ALF
TH
RU
, ve
rify
23 p
s r
ise tim
e , 2
0%
-80%
De
lay M
ea
sT
DT
CA
L2
J3
J5
CA
LS
EC
_1 T
RLD
ela
y in
put
De
lay M
ea
sT
DT
CA
L3
J9
J10
CA
LS
EC
_2 T
RL D
ela
y in
put
De
lay M
ea
sT
DT
CA
L4
J13
J15
CA
LS
EC
_3T
RL D
ela
y in
put
TR
LV
NA
CA
L5
J4
J6
CA
LP
RIM
AR
Y T
HR
OU
GH
- IL m
easure
ment qualit
y check
TR
LV
NA
CA
L6
J4
J6
CA
LP
RIM
AR
Y T
HR
OU
GH
-IL
measure
ment qualit
y check
TR
LV
NA
CA
L7
J14
J16
CA
LC
AL C
HE
CK
-IL
m
easure
ment qualit
y check
TR
LV
NA
CA
L8
J14
J16
CA
LC
AL C
HE
CK
-IL
measure
ment qualit
y check
TR
LV
NA
CA
L9
J48
J41
J42
J47
CA
LN
OIS
E F
LO
OR
measure
ment usin
g IL
TR
LV
NA
CA
L10
J48
J41
J45
J49
CA
LF
IXT
UR
E F
EX
T m
easure
ment
TR
LV
NA
1J21 -
A18_R
x_3_D
NJ18 -
A17_R
x_3_D
PJ27 -
B18_T
x_3_D
NJ24 -
B17_T
X_3_D
PIL
/ R
LT
HR
OU
GH
1 (
pair 1
)
TR
LV
NA
2J20 -
A15_R
X_2_D
NJ17 -
A15_R
X_2_D
PJ26 -
B15_T
X_2_D
NJ23 -
B14_T
X_2_D
PIL
/ R
LT
HR
OU
GH
2 (
pair 2
)
TR
LV
NA
3J22 -
A21_R
x_4_D
NJ19 -
A20_R
x_4_D
PJ28 -
B21_T
x_4_D
NJ25 -
B20_T
X_4_D
PIL
/ R
LT
HR
OU
GH
3 (
pair 3
)
TR
LV
NA
4J27 -
B18_T
x_3_D
NJ24 -
B17_T
X_3_D
PJ21 -
A18_R
x_3_D
NJ18 -
A17_R
x_3_D
PIL
/ R
LT
HR
OU
GH
4 (
pair 4
)
TR
LV
NA
5J26 -
B15_T
X_2_D
NJ23 -
B14_T
X_2_D
PJ20 -
A15_R
X_2_D
NJ17 -
A15_R
X_2_D
PIL
/ R
LT
HR
OU
GH
5 (
pair 5
)
TR
LV
NA
6J28 -
B21_T
x_4_D
NJ25 -
B20_T
X_4_D
PJ22 -
A21_R
x_4_D
NJ19 -
A20_R
x_4_D
PIL
/ R
LT
HR
OU
GH
6 (
pair 6
)
TR
LV
NA
7J27 -
B18_T
x_3_D
NJ24 -
B17_T
X_3_D
PJ21 -
A18_R
x_3_D
NJ18 -
A17_R
x_3_D
PN
EX
TP
SN
EX
T,R
x V
ictim
_bottom
(pair 1
)
TR
LV
NA
8J28 -
B21_T
x_4_D
NJ25 -
B20_T
X_4_D
PJ21 -
A18_R
x_3_D
NJ18 -
A17_R
x_3_D
PN
EX
TP
SN
EX
T, R
x V
ictim
_bottom
(pair 2
)
TR
LV
NA
9J26 -
B15_T
X_2_D
NJ23 -
B14_T
X_2_D
PJ21 -
A18_R
x_3_D
NJ18 -
A17_R
x_3_D
PN
EX
TP
SN
EX
T, R
x-vi
ctim
_bottom
(pair 3
)
TR
LV
NA
7J21 -
A18_R
x_3_D
NJ18 -
A17_R
x_3_D
PJ27 -
B18_T
x_3_D
NJ24 -
B17_T
X_3_D
PN
EX
TP
SN
EX
T,R
x V
ictim
_bottom
(pair 1
)
TR
LV
NA
8J20 -
A15_R
X_2_D
NJ17 -
A15_R
X_2_D
PJ27 -
B18_T
x_3_D
NJ24 -
B17_T
X_3_D
PN
EX
TP
SN
EX
T, R
x V
ictim
_bottom
(pair 2
)
TR
LV
NA
9J22 -
A21_R
x_4_D
NJ19 -
A20_R
x_4_D
PJ27 -
B18_T
x_3_D
NJ24 -
B17_T
X_3_D
PN
EX
TP
SN
EX
T, R
x-vi
ctim
_bottom
(pair 3
)
TR
LV
NA
10
J28 -
B21_T
x_4_D
NJ25 -
B20_T
X_4_D
PJ21 -
A18_R
x_3_D
NJ18 -
A17_R
x_3_D
PF
EX
TP
SF
EX
T, R
x V
ictim
_to
p (
pair 1
)
TR
LV
NA
11
J26 -
B15_T
X_2_D
NJ23 -
B14_T
X_2_D
PJ21 -
A18_R
x_3_D
NJ18 -
A17_R
x_3_D
PF
EX
TP
SF
EX
T, R
x V
ictim
_to
p (
pair 2
)
TR
LV
NA
10
J22 -
A21_R
x_4_D
NJ19 -
A20_R
x_4_D
PJ27 -
B18_T
x_3_D
NJ24 -
B17_T
X_3_D
PF
EX
TP
SF
EX
T, R
x V
ictim
_to
p (
pair 1
)
TR
LV
NA
11
J20 -
A15_R
X_2_D
NJ17 -
A15_R
X_2_D
PJ27 -
B18_T
x_3_D
NJ24 -
B17_T
X_3_D
PF
EX
TP
SF
EX
T, R
x V
ictim
_to
p (
pair 2
)
TR
LV
NA
CA
L11
J4
J6
CA
LP
RIM
AR
Y T
HR
OU
GH
- IL m
easure
ment qualit
y check
TR
LV
NA
CA
L12
J4
J6
CA
LP
RIM
AR
Y T
HR
OU
GH
-IL
measure
ment qualit
y check
Test O
bje
ctive
Calib
ration T
ype
Equip
Test #
Gro
up
TD
R Input/T
DT
Input
(+ =
+ s
ide o
f T
DR
head)
TD
T O
utp
ut
Board
Com
bin
ations
Test F
ile o
utp
ut
Test T
ype
Com
ments
(+
= +
sid
e o
f T
DR
head)
TD
Skew
Check
receiv
er
and
transm
itte
r deskew
TD
R
Pre
-Cal check
n/a
deskew
receiv
er
and tra
nsm
itte
r (inclu
din
g b
oard
)
TD
Cal C
heck
Edge r
ate
(E
R)
check
TD
TC
AL 1
3P
re-m
easure
Calib
ration
J8
J11
CY
LLE
NE
VR
ER
TD
RJ20
J17
ER
TD
RJ21
J18
ER
TD
RJ22
J19
ER
TD
RJ26
J23
ER
TD
RJ27
J24
ER
TD
RJ28
J25
TD
Cal C
heck
Edge r
ate
(E
R)
check
TD
TC
AL 1
4
J8
J11
CY
LLE
NE
VR
Po
st M
easu
rmen
t
Cal
ch
eck
Post-
Measure
Cal C
heck
*.csv (voltage, time, impedance)
p
ositiv
e a
nd n
egative
input, c
heck r
ise tim
e a
t re
f pla
ne
MCIO-style
Mated cable assembly
Time domain measurement
23 ps at the ref plane, 20-80%
12
CY
LLE
NE
RA
- R
OO
T
Diffe
rential
Impedance
13
Diffe
rential
Impedance
positiv
e a
nd n
egative
input, c
heck r
ise tim
e a
t re
f pla
ne
14
Diffe
rential
Impedance
15
CY
LLE
NE
RA
- T
AR
GE
T
Diffe
rential
Impedance
IL/R
L
16
Diffe
rential
Impedance
17
Diffe
rential
Impedance
PS
FE
XT
(RA
R-T
x V
ictim
)
Test Cable & Fixture Check
Pre
-measure
Calib
ration
CY
LL
EN
E R
AR
- R
OO
T, C
YL
LE
NE
RA
R -
TA
RG
ET
Pre
-Cal N
ois
e C
heck
Pre
-Cal
Check
PS
NE
XT
(RA
R-R
x V
ictim
)
PS
FE
XT
(RA
R-R
x V
ictim
)
PS
NE
XT
(RA
R-T
x V
ictim
)
MCIO RAR-RAR cable assembly
Frequency domain measurement
IN IN
OU
T
OU
T
DRAFT SFF-TA-1024 Rev 0.0.2 Template Rev 1.0
Test Procedure for SFF-TA-1016 Mated Cable Assembly Page 44
Copyright Β© 2021 SNIA. All rights reserved.
Appendix A Cyllene Bill of Materials 1
Table A-1 Cyllene Bill of Materials 2
3
DRAFT SFF-TA-1024 Rev 0.0.2 Template Rev 1.0
Test Procedure for SFF-TA-1016 Mated Cable Assembly Page 45
Copyright Β© 2021 SNIA. All rights reserved.
Appendix B VNA TRL Calibration 1
B.1 TRL Calibration Crossover Frequencies 2
The TRL calibration kit designed to remove the test fixture effect from the S-parameter measurement are 3
included in the connector evaluation board design using the standards shown in Table B-1. 4 5
Table B-1 TRL Calibration Kit Crossover Frequencies 6
Frequency Ranges Description
DC to β€ 0.4 GHz Load 1 and Load 2
> 0.4 to β€ 2.0 GHz Secondary #1
> 2.0 to β€ 10.0 GHz Secondary #2
> 10.0 to β€ 50.0 GHz Secondary #3
7
8
B.2 TRL Calibration E-cal and Fixture Bandwidth 9
TRL calibration requires preparation including e-cal, fixture bandwidth assessment and measured secondary 10
delay times. Table B-2 shows the typical steps used to assess fixture bandwidth. 11 12
Table B-2 E-cal and Fixture Bandwidth Checks 13
Step Description
1 Restart the VNA
2 Set the frequency sweep
3 Set the port power
4 Set Averaging and IF bandwidth
5 Set e-cal calibration (3 defined throughs)
6 Save the calibration
ECAL1 IL, RL measurement of Primary through
ECAL2 IL, RL measurement of Primary through
14
DRAFT SFF-TA-1024 Rev 0.0.2 Template Rev 1.0
Test Procedure for SFF-TA-1016 Mated Cable Assembly Page 46
Copyright Β© 2021 SNIA. All rights reserved.
B.3 Initial TRL Calibration Steps 1 - 22 1
TRL calibration requires several steps. Table B-3, Table B-4, and Table B-5 show the typical steps used to 2
achieve stable TRL calibration. 3 4
Table B-3 Initial TRL Calibration Steps 5
Step Description
1 Restart the VNA
2 Recall the e-cal
3 Insert a new cal kit
4 Edit Cal Kit Information
5 TRL Cal Kit Setup: Open
6 TRL Cal Kit Setup: Short
7 TRL Cal Kit Setup: Load
8 TRL Cal Kit Setup: Primary Through
9 TRL Cal Kit Setup: Secondary 1 (use measured delay time)
10 TRL Cal Kit Setup: Secondary 2 (use measured delay time)
11 TRL Cal Kit Setup: Secondary 3 (use measured delay time)
12 TRL class assignment: TRL Through
13 TRL Class assignment: TRL Reflect
14 TRL Class assignment: TRL Line/Match
15 TRL Class assignment: Isolation
16 Set the frequency sweep
17 Set the port power
18 Set Averaging and IF bandwidth
19
TRL Guided Calibration (2 defined throughs + 2 unknown throughs or 2 defined
throughs + 4 unknown unknown throughs)
Note: Choice of 2 + 2 or 2 + 4 depends on VNA firmware. Use Type 1 on initial
calibration, use Type 2 to address TRL cal instability.
20 SmartCal (GUIDED Calibration)
21 DUT Connector selection
22 Modify Cal
6
DRAFT SFF-TA-1024 Rev 0.0.2 Template Rev 1.0
Test Procedure for SFF-TA-1016 Mated Cable Assembly Page 47
Copyright Β© 2021 SNIA. All rights reserved.
B.4 Final TRL Calibration Steps Using 2 Defined Throughs + 2 Unknown 1
Throughs 2
Final TRL calibration steps 23 to 43 and TRL calibration check using 2 defined throughs + 2 unknown 3
throughs are shown in Table B-4. 4 5
Table B-4 TRL Calibration Steps 23 to 43 Using 2 Defined Throughs + 2 Unknown Throughs 6
Step Description
23 Guided Calibration
24 Guided Calibration Step 1 of 18: Connect Port 1 to Short
25 Guided Calibration Step 2 of 18: Connect Port 2 to Short
26 Guided Calibration Step 3 of 18: Connect Port 1 to Port 2
27 Guided Calibration Step 4 of 18: Connect Port 1 and Port 2 to Secondary 3
28 Guided Calibration Step 5 of 18: Connect Port 1 and Port 2 to Secondary 2
29 Guided Calibration Step 6 of 18: Connect Port 1 and Port 2 to Secondary 1
30 Guided Calibration Step 7 of 18: Connect Port 1 to Load
31 Guided Calibration Step 8 of 18: Connect Port 2 to Load
32 Guided Calibration Step 9 of 18: Connect Port 3 to Short
33 Guided Calibration Step 10 of 18: Connect Port 4 to Short
34 Guided Calibration Step 11 of 18: Connect Port 3 to Port 4
35 Guided Calibration Step 12 of 18: Connect Port 3 and Port 4 to Secondary 3
36 Guided Calibration Step 13 of 18: Connect Port 3 and Port 4 to Secondary 2
37 Guided Calibration Step 14 of 18: Connect Port 3 and Port 4 to Secondary 1
38 Guided Calibration Step 15 of 18: Connect Port 3 to Load
39 Guided Calibration Step 16 of 18: Connect Port 4 to Load
40 Guided Calibration Step 17 of 18: Connect Port 1| Adapter | Port 4
41 Guided Calibration Step 18 of 18: Connect Port 2| Adapter | Port 3 : Quality check, adapter offset of Port 2 and Port 3 = Sec 3 delay +- 6 ps
42 Save the Calibration
43 Check the Calibration
7
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B.5 Final TRL Calibration Steps Using 2 Defined Throughs + 4 Unknown 1
Throughs 2
Final TRL calibration steps 23 to 45 and TRL calibration check using 2 defined throughs + 4 unknown 3
throughs are shown in Table B-5. 4 5
Table B-5 Final TRL Calibration Steps Using 2 Defined Throughs + 4 Unknown Throughs 6
Step Description
23 Guided Calibration
24 Guided Calibration Step 1 of 20: Connect Port 1 to Short
25 Guided Calibration Step 2 of 20: Connect Port 2 to Short
26 Guided Calibration Step 3 of 20: Connect Port 1 to Port 2
27 Guided Calibration Step 4 of 20: Connect Port 1 and Port 2 to Secondary 3
28 Guided Calibration Step 5 of 20: Connect Port 1 and Port 2 to Secondary 2
29 Guided Calibration Step 6 of 20: Connect Port 1 and Port 2 to Secondary 1
30 Guided Calibration Step 7 of 20: Connect Port 1 to Load
31 Guided Calibration Step 8 of 20: Connect Port 2 to Load
32 Guided Calibration Step 9 of 20: Connect Port 3 to Short
33 Guided Calibration Step 10 of 20: Connect Port 4 to Short
34 Guided Calibration Step 11 of 20: Connect Port 3 to Port 4
35 Guided Calibration Step 12 of 20: Connect Port 3 and Port 4 to Secondary 3
36 Guided Calibration Step 13 of 20: Connect Port 3 and Port 4 to Secondary 2
37 Guided Calibration Step 14 of 20: Connect Port 3 and Port 4 to Secondary 1
38 Guided Calibration Step 15 of 20: Connect Port 3 to Load
39 Guided Calibration Step 16 of 20: Connect Port 4 to Load
40 Guided Calibration Step 17 of 20: Connect Port 1 | Adapter | Port 3
41 Guided Calibration Step 18 of 20: Connect Port 1 | Adapter | Port 4
42 Guided Calibration Step 19 of 20: Connect Port 2| Adapter | Port 3 : Quality check, adapter offset of Port 2 and Port 3 = Sec 3 delay +- 6 ps
43 Guided Calibration Step 20 of 20: Connect Port 2| Adapter | Port 4 : Quality check, adapter offset of Port 2 and Port 4 = Sec 3 delay +- 6 ps
44 Save the Calibration
45 Check the Calibration
7
DRAFT SFF-TA-1024 Rev 0.0.2 Template Rev 1.0
Test Procedure for SFF-TA-1016 Mated Cable Assembly Page 49
Copyright Β© 2021 SNIA. All rights reserved.
Appendix C Rise Time Measurement 1
C.1 TDR Head Connections 2
Connect the CH1 TDR head through a cable to the half primary through and the CH2 TDR head directly to 3
the half primary through. 4 5
6
Figure C-1 TDR Head Connections 7
8
C.2 TDR Instrument Default Settings. 9
Set the TDR instrument to its default settings. 10 11
12
Figure C-2 TDR Instrument Default Settings Screenshot 13
14
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C.3 TDR Mode Setup. 1
Change the TDR Mode (Setup> Mode/ Trigger> TDR) and set the rate to 200 kHz. 2
3
4
Figure C-3 TDR Mode Setup Screenshot 5
6
C.4 Channel Definition 7
Define the channel. 8
a. Setup> TDR 9
b. Configure both the channels to have rising edge. 10 c. Configure the individual channels TDR step and acquisition as follows: 11
=> C1: TDR step= ON and ACQ= OFF 12 => C2: TDR step= OFF and ACQ= ON 13
d. Change the units of both the channels to βvoltage (V)β. 14 15
16
Figure C-4 Channel Definition Setup 17
18
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C.5 View the Rising Edge 1
Use the horizontal scale and position to be able to view the rising edge. 2
3
4
Figure C-5 TDR View of Rising Edge 5
6
C.6 Rise Time Measurement Setup. 7
Perform the following setup steps to enable making a rise time measurement. 8
a. Setup> Measurement. 9
b. Select Meas> Pulse- Timing> Rise Time. 10 c. Set Source1> C2 on Main. 11
d. Untick Use Wfm Database and click Clearβ. 12 e. Select the signal type as Pulse. 13
f. Set the RefLevel to relative 80-20%. 14 g. Turn on statistics and annotations. 15
h. Turn on the measurement. 16
17
18
Figure C-6 Screenshot for Setup Steps a. and b. 19
20
DRAFT SFF-TA-1024 Rev 0.0.2 Template Rev 1.0
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1
Figure C-7 Screenshot for Setup Steps b. and c. 2
3
4
Figure C-8 Screenshot for Setup Steps d. and e. 5
6
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1
Figure C-9 Screenshot for Setup Step f. 2
3
4
Figure C-10 Screenshot for Setup Steps g. and h. 5
6
DRAFT SFF-TA-1024 Rev 0.0.2 Template Rev 1.0
Test Procedure for SFF-TA-1016 Mated Cable Assembly Page 54
Copyright Β© 2021 SNIA. All rights reserved.
C.7 Rise Time Adjustments. 1
C.7.1 Rise Time Adjustment Option 1 2
a. Setup> Vertical. 3
b. Select waveform> C1. 4
c. Check βONβ. 5
d. Toggle between the different bandwidth options to set the right rise time. 6 7
C.7.2 Rise Time Adjustment Option 2. 8
β’ Another option to adjust the rise time is to use a software defined filter to slow the edge. 9
a. Edit> Define Math. 10
b. Math Expression: βFilter(C2)β 11
c. Set the number of averages to 200. 12
d. Adjust the filter rise time value to reach the desired rise time by monitoring the M1 rise time 13 measurement value. 14
15
16
Figure C-11 Screenshot for Option 2 Steps a. and b. and c. 17
18
DRAFT SFF-TA-1024 Rev 0.0.2 Template Rev 1.0
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Copyright Β© 2021 SNIA. All rights reserved.
1
Figure C-12 Screenshot Showing Measured Rise Time 2
3