Session six

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<ul><li> 1. Session 6Prepared byAlaa Salah ShehataMahmoud A. M. Abd El LatifMohamed Mohamed TalatMohamed Salah Mahmoud Version 02 October 2011Copyright 2006 Biz/ed</li></ul> <p> 2. -Scrambler mini project discussion -Finite State Machine -What is FSM? -Moore machine6 -Mealy machine -FSM in VHDL 2 Copyright 2006 Biz/ed 3. Session 6 mini project discussionB(i)=[b(i)+c(i)]mod2 3 Copyright 2006 Biz/ed 4. Session 6 4 Copyright 2006 Biz/ed 5. Session 6 is FSM Any digital system consists of two part:Data Part Data part Responsible for the processing of data. TheInputs Outputs processing is done through some blocks such as (full adder, digital filter, decoder,)Controls Control part Describes how and when these blocks will communicate with each other. The control part is generally described using a finite Control Part state machine.5Copyright 2006 Biz/ed 6. Session 6 is FSM S1Finite State MachineFSM is simply a finite number of states thatS3 S2each state describes a certain set of controloutputs that are connected to the data partblocks.The transition between these states dependsmainly on the inputs of the FSM.There are two main types of FSM: S4Moore FSMMealy FSM6Copyright 2006 Biz/ed 7. Session 6 in VHDLAssigning Moore OutputsOutputUse a combinational process to model Output Logic LogicOutputs are only dependant on the current stateAssigning Mealy Outputs Outputs = f(State)Use a combinatorial process to model Output LogicOutputs are dependant on the current state &amp; the input Outputs = f(Inputs, State) Output Logic 7 Copyright 2006 Biz/ed 8. Session 6 FSM In a Moore finite state machine, the output of the circuit is dependent only on the state of the machine and not on its inputs.Inputs Next Present statestateOutputs NextMachineOutput StateState Logic Logic Registers 8 Copyright 2006 Biz/ed 9. Session 6 FSM In a Mealy finite state machine, the output is dependent both on the machine state as well as on the inputs to the FSM.InputsNextPresentstate stateOutputsNextMachine OutputStateStateLogicLogic Registers 9 Copyright 2006 Biz/ed 10. Session 6 FSM transitioncondition 1 state 1state 2transitioncondition 2Mealy FSMtransition condition 1 / output 1state 1 state 2 transition condition 2 / output 2 10Copyright 2006 Biz/ed 11. Session 6 Synchronous &amp; asynchronous FSM -Moore (Synchronous ) -Mealy(asynchronous ) Example2611 Copyright 2006 Biz/ed 12. Session 6 FSM that Recognizes Sequence 100 110 S0 / 0S1 / 0 S2 / 1 reset S0: No S1: 1S2: 10Meaningelements observed observedof states: of the sequence observed12 Copyright 2006 Biz/ed 13. Session 6 FSM that Recognizes Sequence 100/0 1/0 1/0S0 S1 reset0/1 S0: No S1: 1 Meaning elements observed of states:of the sequence observed 13Copyright 2006 Biz/ed 14. Session 6 100 0inputS0S1 S2 S0 S0MooreS0S1 S0 S0 S0Mealy 14Copyright 2006 Biz/ed 15. Session 6 3-FSM in VHDL-Finite State Machines Can Be Easily Described With Processes-Synthesis Tools Understand FSM Description if Certain Rules Are Followed-----State transitions should be described in a process sensitive to clock and asynchronousreset signals only-----Output function described using rules for combinational logic, i.e. as concurrentstatements or a process with all inputs in the sensitivity list 15Copyright 2006 Biz/ed 16. Session 6 in VHDLThe 3 Processes, 1 Clocked + separate transitions/actions style1-Process modeling Next State Logic NextStateLogic2-Process modeling "Current State Registers" StateRegisters3-Process modeling Output LogicOutputLogic 16Copyright 2006 Biz/ed 17. Session 6 in VHDLNext-State LogicUse a combinational process to model next state logicprocess ( current_state, , , )Begincase ( Current_State ) iswhen =&gt; Nextif ( , ...)&gt; ) thenStateNext_State ) thenNext_State</p>


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