344 • 2011 IEEE International Solid-State Circuits Conference 978-1-61284-302-5/11/$26.00 ©2011 IEEE

ISSCC 2011 / SESSION 20 / HIGH-SPEED TRANSCEIVERS & BUILDING BLOCKS / OVERVIEW

Session 20 Overview / Wireline

High-Speed Transceivers & Building Blocks

Session Chair: Jae-Yoon Sim, Pohang University of Science and Technology, Pohang, Korea

Session Co-Chair: Masafumi Nogawa, NTT, Atsugi, Japan

Transceivers designed for very high-speed wireline communication must contend with significant chan-nel loss, crosstalk, and reflections by employing various equalization techniques in the transmitter andreceiver. Confronting these challenges becomes even more difficult as data rates increase beyond10Gb/s and designs become power-constrained. The first four papers in this session describe trans-ceivers that address these concerns. The remaining papers describe key building blocks for next-gener-ation transceivers with a focus on various receive equalizer adaptation techniques and spread-spectrumclock generation for EMI reduction.

Paper 20.1 from Fujitsu demonstrates a 10.3Gb/s transceiver in 90nm CMOS that achieves an adaptation for both of phase andamplitude distortions for the first time. It combines an analog linear equalizer, a decision-feedback equalizer (DFE), and a driverwith pre-emphasis to adaptively compensate up to 41dB channel loss.

Paper 20.2 from LSI Corporation presents a multimedia transceiver implemented in 40nm CMOS. It proposes a new baseline wan-der correction scheme with a linear equalizer, a 10-tap DFE, and a 4-tap feed-forward equalizer (FFE) for operation over a widerange of data rates from 1.0625 to 14.025Gb/s.

Texas Instruments and Arda Technologies describe their latest transceiver in paper 20.3. This SerDes supports a data rate of16Gb/s and uses a 14-tap DFE and analog equalizer along with an enhanced-swing voltage-mode driver to generate a 1.2V differ-ential output to compensate 34dB of channel loss.

In Paper 20.4, SnowBush-Gennum demonstrates a 4-lane multistandard-compliant transceiver that supports data rates rangingfrom 1 to 12Gb/s to satisfy standards including PCIe, SATA, and 1-to-10Gb/s Ethernet without using on-chip inductors.

Paper 20.5 from University of Toronto and Fujitsu Laboratories describes an adaptive engine for a 6Gb/s DFE for a 2× blind ADC-based receiver. This engine digitally extracts the optimum coefficients for the DFE irrespective of the sampling phase of the blindclock.

Paper 20.6 from National Taiwan University presents a 6Gb/s receiver in 90nm CMOS with an adaptive IIR-based DFE compensat-ing a channel loss of 32.7dB.

Yonsei University details a new receive equalizer adaptation technique using asynchronous-sampling histograms in Paper 20.7.The equalizer, implemented in 0.13µm CMOS, demonstrates successful adaptation at 5.4Gb/s over various lossy channels.

Finally, Paper 20.8 from Korea University demonstrates a 3.5GHz spread-spectrum clock generator in 0.13µm CMOS with a mem-oryless nonlinear Newton-Raphson modulation profile achieving an EMI reduction of 19.14dB.

345DIGEST OF TECHNICAL PAPERS •

ISSCC 2011 / February 23, 2011 / 8:30 AM

20.1 A 4-Channel 10.3Gb/s Transceiver with Adaptive Phase 8:30 AMEqualizer for 4-to-41dB Loss PCB Channel

Y. Hidaka,Fujitsu Laboratories of America, Sunnyvale, CA

20.2 A 1.0625-to-14.025Gb/s Multimedia Transceiver with Full-rate Source-Series-Terminated Transmit 9:00 AMDriver and Floating-Tap Decision-Feedback Equalizer in 40nm CMOS

S. Quan,LSI, Milpitas, CA

20.3 Analog-DFE-Based 16Gb/s SerDes in 40nm CMOS That Operates Across 34dB Loss Channels 9:30 AMat Nyquist with a Baud Rate CDR and 1.2Vpp Voltage-Mode Driver

A. K. Joy, Texas Instruments, Northampton, United Kingdom

20.4 An 8.4mW/Gb/s 4-Lane 48Gb/s Multi-Standard-Compliant 10:15 AMTransceiver in 40nm Digital CMOS Technology

M. Ramezani,Snowbush-Gennum, Toronto, Canada

20.5 A Pattern-Guided Adaptive Equalizer in 65nm CMOS 10:45 AMS. Shahramian,University of Toronto, Toronto, Canada

20.6 A 6Gb/s Receiver with 32.7dB Adaptive DFE-IIR Equalization 11:15 AMY-C. Huang,National Taiwan University, Taipei, Taiwan

20.7 A 5.4Gb/s Adaptive Equalizer Using Asynchronous-Sampling Histograms 11:45 AMW-S. Kim, Yonsei University, Seoul, Korea

20.8 A 0.076mm2 3.5GHz Spread-Spectrum Clock Generator with 12:00 PMMemoryless Newton-Raphson Modulation Profile in 0.13µm CMOS

S. Hwang, Korea University, Seoul, Korea

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