series of advanced mixed-signal test systemsa565 series of advanced mixed-signal test systems...

A585/A575/A565Series of Advanced Mixed-Signal Test Systems

System Description

1A585/A575/A565 SERIES ADVANCED MIXED-SIGNAL TEST SYSTEMS • SYSTEM DESCRIPTION

INTRODUCTION ...............................................................................................................7Testing Strategy for Mixed-Signal Devices .....................................................................7Functional versus Component Testing .............................................................................7Device Testing Synchronization ......................................................................................8Common System-Level Integration.................................................................................. 9

THE EVOLUTION FROM VLSI TO MIXED-SIGNAL TESTING ........................................ 10

THE EVOLUTION FROM ANALOG TO MIXED-SIGNAL TESTING .................................. 13

THE A585/A575/A565 ADVANCED MIXED-SIGNAL TEST SYSTEMS ........................... 15

THE VECTOR BUS® ARCHITECTURE ............................................................................. 16TimeMaster™ Clock Synchronization ............................................................................ 16MultiSource Data Mixing .............................................................................................. 18Mixed-Signal Microcode™ Control ............................................................................... 19MultiSync TimeGen™ ..................................................................................................... 22MultiState Memory Store .............................................................................................. 24

UNIVERSAL BUS ARCHITECTURE ................................................................................. 25Trigger Bus .................................................................................................................. 27Measure Bus .................................................................................................................. 28Modulation Bus .............................................................................................................. 28Test Head Analog Distribution System (THADS) Bus .................................................... 28

DUAL COMPUTER ARCHITECTURE ............................................................................... 30Computer Networking ................................................................................................... 31Sun Ethernet Networking .............................................................................................. 31Networking and X Windows ......................................................................................... 31

IMAGE™ SOFTWARE SYSTEM ...................................................................................... 32Customized ATE Dual-Computer Operating Environment ............................................. 32Ethernet TCP/IP Networking Software with Network File System .............................. 32IMAGE Programming ..................................................................................................... 32Instrumentation Drivers ................................................................................... 34Digital Signal Processing Software Library ....................................................... 35Test Program Organization ............................................................................................. 35Binning Strategy .............................................................................................. 35Pinmap ............................................................................................................ 35Sequencer........................................................................................................ 35Tests and Functions ......................................................................................... 36Device Pin-Oriented Language ....................................................................... 36Interactive Test Program Editor and Debugger ............................................................. 38Source-level Debugger with Breaktraps ........................................................... 38Incremental Compile for Fast Turnaround ....................................................... 39

Table of Contents

2 A585/A575/A565 SERIES ADVANCED MIXED-SIGNAL TEST SYSTEMS • SYSTEM DESCRIPTION

Immediate Statement Execution ..................................................................... 39Interactive Digital and Analog Design and Debug Tools .............................................. 40Digital Pattern Editor and Debugger................................................................ 40Digital Pattern Advanced Logic Analyzer ......................................................... 41Digital Waveshape Tools .................................................................................. 42Analog Waveform Display ................................................................................ 43Graphic Instrumentation Status Displays ......................................................... 44Data Analysis and Characterization Software .............................................................. 45Datalog Reports ............................................................................................... 45Summary Reports ............................................................................................ 45Real-Time Histograms ..................................................................................... 45Digital and Parametric Shmoo Plots ................................................................. 463-D Shmoo Plots .............................................................................................. 46Computer-Aided Test Development ............................................................................... 48Additional IMAGE Software Tools: IMAGE ExPress™ and ProGen™ ............... 48Device Test Libraries ....................................................................................... 49Sun Stand-Alone Workstation and Tester Simulation Software ......................... 49Using the Stand-Alone Workstation While Testing ........................................... 50Digital Simulator Software ............................................................................... 50Simulation-Based Development Using IMAGE ExChange™ ........................... 51Insight Analysis Software and Other Tools ................................................................... 53Design Insight ................................................................................................. 53Test Insight...................................................................................................... 54Wafer Insight ................................................................................................... 55Production Insight ........................................................................................... 56Manufacturing Data Pipeline ........................................................................... 57Automatic Time & Event Logger .................................................................... 57

ANALOG VLSI DIGITAL TEST CAPABILITIES ................................................................ 58Digital Channel Configuration ....................................................................................... 58Multiple Memory Architecture: Pattern Memory .......................................................... 59Digital Signal I/O Memory ............................................................................................. 62Vector Bus Memory for SCAN ....................................................................................... 64Digital Sequence Control Module ................................................................................. 64Timing And Format ......................................................................................................... 66Digital Clock and Data Rates ........................................................................... 66Edge Agility ..................................................................................................... 67Timing Sets and Edge Sets .............................................................................. 68Drive and Compare Formats ............................................................................ 70History RAM for Failure Analysis ................................................................................... 71Digital Channel Card ...................................................................................................... 71


140 MHz High Speed Digital Channels .......................................................................... 72Superclock Option ......................................................................................................... 72Super Speed Serial Pin .................................................................................................. 73

AC INSTRUMENTATION AND TEST CAPABILITIES ...................................................... 74Analog Instrument Architecture .................................................................................... 75Analog Instrumentation ................................................................................................. 78Analog Instrument Channel Card..................................................................... 78Precision Low Frequency Source ..................................................................... 79Precision Low Frequency Digitizer .................................................................. 80LFAC100 ........................................................................................................ 81Very High Frequency Arbitrary Waveform Generator ....................................... 83VHFAWG400 .................................................................................................. 84High Frequency Digitizer ................................................................................ 84Very High Frequency Continuous Waveform Source ........................................ 85High Speed Sampler (HSS) ............................................................................. 86Very High Frequency Measure Module ........................................................... 87Time and Jitter Measurements ...................................................................................... 87Advanced Time Measurement Subsystem ....................................................... 87Time Jitter Digitizer ........................................................................................ 88Microwave Instruments ................................................................................................ 90Microwave CW Source .................................................................................... 90IF Modulated Source ....................................................................................... 90Microwave Measure Module ........................................................................... 90Microwave Vector Network Analyzer Module .................................................. 91Teradyne’s Microwave Software Library ........................................................... 91

DC INSTRUMENTATION AND TEST CAPABILITIES ...................................................... 92DC Crosspoint Matrix ..................................................................................................... 92DC Subsystem ................................................................................................................ 92Standard V/l Sources ........................................................................................ 92Differential Voltmeter ...................................................................................... 93Analog Pin Unit ............................................................................................... 94Advanced Analog Pin Unit ............................................................................... 94High Current Unit ........................................................................................... 94Quad Power V/I ............................................................................................... 95Precision DC Instrumentation ........................................................................................ 95Precision Multimeter Module .......................................................................... 95Reference Source ............................................................................................. 95Quad Op Amp Loop ........................................................................................ 95Low Current Ammeter .................................................................................... 96


Pulse Driver ..................................................................................................... 97Synchronized Power Instrumentation ........................................................................... 98High Power V/l ................................................................................................ 99High Power Matrix .......................................................................................... 99High Current Current Source ......................................................................... 100High Current Voltage Source.......................................................................... 100High Voltage Ammeter .................................................................................. 100Breakdown Voltage Current Source ................................................................ 100

PRODUCTION INTERFACE ........................................................................................... 101Direct-Docking: Advanced Mixed-Signal Test Head .................................................. 101Configuration Board ....................................................................................... 102Iso-Pin™ Connections ................................................................................... 103Device Interface Boards ................................................................................. 103Cable Interface: Production Analog Test Head (PATH II) ............................................. 105Handler and Prober Interfacing ................................................................................... 107

SYSTEM CONFIGURATIONS ....................................................................................... 108Test System Footprint ................................................................................................... 109A585 Advanced Mixed-Signal Test System................................................................. 111A575 Advanced Mixed-Signal Test System................................................................. 111A565 Advanced Mixed-Signal Test System ................................................................ 111

INSTRUMENT SPECIFICATIONS ................................................................................. 113Key Instrument Specifications and Features ............................................................... 113Digital Instrumentation ................................................................................................ 114High Speed Digital (HSD25) ......................................................................... 114High Speed Digital (HSD50-50) .................................................................... 116Superclock (SCL) .......................................................................................... 118Super Speed Serial Pins (SSSP) ...................................................................... 119AC Instrumentation ...................................................................................................... 120Precision Low Frequency Source (PLFS) ...................................................... 120Precision Low Frequency Digitizer (PLFD) .................................................. 121Low Frequency AC Source (LFAC100 SRC)................................................. 122Low Frequency AC Digitizer (LFAC100 DIG) ............................................. 123VHF Measurement Module (VHFMM)........................................................ 124VHF Arbitrary Waveform Generator (VHFAWG)........................................... 125VHF Continuous Waveform Source (VHFCW) ............................................. 126High Frequency Digitizer (HFD) .................................................................. 127High Speed Sampler (HSS) ........................................................................... 128Advanced Time Measurement Subsystem (ATMS) ....................................... 129Time Jitter Digitizer (TJD) ............................................................................ 131


Microwave Continuous Waveform Source ................................................................. 132DC Instrumentation ...................................................................................................... 134DC Subsystem (V/I): 60 V/200 mA V/I Sources .............................................. 134DC Subsystem: DC Differential Voltmeter .................................................... 136Analog Pin Unit (APU) .................................................................................. 137Advanced Analog Pin Unit (AAPU)................................................................ 139High Current Unit (HCU) ............................................................................. 141Quad Power V/I (QPVI) ................................................................................. 142Quad Op Amp Loop (QOA) .......................................................................... 143Low Current Ammeter (LCA) ....................................................................... 144Pulse Driver ................................................................................................... 145Precision Multimeter (PMM) ......................................................................... 146Precision Reference Source ............................................................................ 148Synchronized Power Instrumentation ......................................................................... 149High Current Current Source (HCCS) ........................................................... 149High Current Voltage Source (HCVS) ............................................................ 151High Power V/I (HPVI) ................................................................................. 152High Power Matrix (HPM) ........................................................................... 154High Voltage Ammeter (HVA) ....................................................................... 155Breakdown Voltage Current Source (BVCS) ................................................... 156

FIGURES AND TABLES ................................................................................................ 157


A565 Advanced Mixed-SignalTest System




possible. With the A585/A575/A565series of test systems, semiconductormanufacturers can use one testprogram on a single test system toimplement both component andfunctional test during the characteriza-tion phase of new silicon. This cansignificantly shorten the developmentcycle time.

During component testing, individualdevice building blocks are accessedand tested as discrete units. Perfor-mance is verified and faults areidentified. In the development cycle,this information can be used to modifythe design and eliminate the problem.On the production floor, this samecomponent test will identify a failurethat would impact overall deviceoperation.

Functional testing ensures that thebuilding blocks work together andthe device functions as intended.Functional testing also helps tocorrelate faults at component testwith functional performance errors.In addition, functional test guaran-tees that the system silicon meetsthe required industry standardspecifications for Ethernet, ISDN,modems, video, and other mixed-signal devices, allowing a manufac-turer to differentiate his product byguaranteeing performance withgreater test coverage. Those manu-facturers who verify the most specson the device and price the deviceeconomically have a significantmarket advantage over other ven-dors of similar devices.

Introduction

TESTING STRATEGY FORMIXED-SIGNAL DEVICESDevice functionality continues tobecome more highly integrated, withanalog functions on traditionally“digital” devices and digital functionsand controls on formerly all analogdevices. Whether you come from aformerly all analog or all digital testingworld, the devices you must test noware mixed-signal devices. You mayknow them as “systems on a chip,”“mixed-signal ASICs,” or “systemsilicon”. However you know them,these devices require a high-perfor-mance mixed-signal test system tosuccessfully test both the componentswithin each device as well as theoverall system functionality of thedevice. The Teradyne A585/A575/A565 Series of Advanced Mixed-Signal Test Systems simplify thetransition from all analog to analog-with-digital, or mixed-signal, testingbecause the addition of testing digitalsignals is handled in a manner familiarto you. Similarly, the transition fromall digital to mixed-signal testing (withdynamic analog measurements) is alsosimplified because the architecturethroughout the Teradyne A585/A575/A565 Series of Advanced Mixed-Signal Test Systems is based on thefamiliar per-pin functionality of VLSItest systems.

FUNCTIONAL VERSUSCOMPONENT TESTINGTo reduce time to market and ensurethe greatest number of design-ins,device problems must be eliminatedas early in the development cycle as


An example of functional and compo-nent testing can be demonstrated withthe programmable filter device shownin figure 1. It contains an A/D con-verter that converts an analog signal toa digital signal for processing by theon-board DSP engine. The filter alsocontains a D/A converter for generat-ing an analog output. A number oftests can be performed by accessingthe components through the micropro-cessor bus: the converters can beisolated and tested for ac linearityperformance, the DSP engine can belogically tested with high speed digitalpatterns, and the ROM contents canbe read back to confirm that propervalues have been programmed. Oncethe components are verified, an analogsignal filtered by the device andcaptured by the test system can beanalyzed for frequency response.

Running only functional tests wouldrequire 256 frequency response teststo ensure that all filter settings workcorrectly. However, system functional-ity can be verified with only one or twofrequency response tests if thecomponent tests are run first to verifythe digital signal processor and that thecoefficients are correct and readablefrom the ROM. This second strategysaves substantial test time in theproduction environment by combin-ing functional and component testing.

The A585/A575/A565 series revolu-tionized component and functionaltest with the ability to run both typesof tests on a common system platformwith one test program. Numerousmanufacturers around the worldcurrently implement this strategy totest Ethernet, ISDN, video processors,

disk drives, palette DACs, CODECs,multimedia, mixed-signal ASICs andother mixed-signal devices.

DEVICE TESTINGSYNCHRONIZATIONMixed-signal device testing requiresthat the digital pins and the analoginstrumentation in the test system besynchronized. For example, if ananalog source is programmed togenerate a 1 MHz sine wave, and thedigital pins are programmed togenerate a 24 MHz pattern, eachinstrument must use the same timingreference to ensure that analog signaland digital patterns are locked to-gether and repeatable. In order toaccurately measure mixed-signaldevice performance, the analogwaveforms and the digital datagenerated by the D/A and A/D

16 PINS

D/A

ROM

MICRO INTERFACE

DIGITALSIGNAL

PROCESSORA/D

Figure 1Block Diagram of a DSP programmable filter with 256 filter selections


VECTOR BUSARCHITECTURE

A500/ A550

A520/ A540

A510/ A530

A580/ A585

A570/ A575

A565

Figure 2The Evolution of the A500 Family and the A585/A575/A565 Series ofAdvanced Mixed-Signal Test Systems

converters on the device need to besynchronous with input signals inorder to use digital signal processing todetermine test results.

COMMON SYSTEM-LEVELINTEGRATIONIn each A585/A575/A565 series mixed-signal test system, Teradyne’s innova-

tive Vector Bus® III architecture isused to provide integration andsynchronization of the digital pins andanalog instruments. High performanceinstrumentation is common to theentire family of test systems. TheUniversal Bus architecture providesadditional waveform distribution andtiming synchronization betweeninstruments. Finally, Teradyne’s

Interactive Menu-Assisted GraphicsEnvironment, or IMAGE™, softwareenvironment is used for programcreation, debugging and execution.Each of these elements is integral tothe systems described in this SystemDescription. See figure 2.


The Digital Pattern Controllercontrols the execution of digitalpatterns and provides the ability toloop a pattern, to implement vectorsubroutines, to jump on fail, and toexecute other functions that compressthe pattern memory requirements ofVLSI components.

The Digital Pattern Memory containsthe pin state information required bythe device under test (DUT). It sendsthe drive to 1 or 0, and the compare L,H, X or M states to the formatter andtiming generator.

The Digital Formatter creates edgesand waveshapes for the data such asreturn to zero or complement sur-

Because the A585/A575/A565 Series ofAdvanced Mixed-Signal Test Systemsshare a common architecture withVLSI test systems, the transition fromall digital testing to digital withdynamic analog measurements andmixed-signal testing is greatly simpli-fied. As shown in figure 3, each blockof the digital portion of the mixed-signal test system is the same as aVLSI test system. The digital per-pinchannel architecture consists of:

• Digital Pattern Controller

• Digital Pattern Memory

• Digital Formatter and TimingGenerator

• Digital Channel Card

The Evolution From VLSITo Mixed-Signal Testing

Figure 3Digital mixed-signal test system architecture

DIGITALPATTERN

CONTROLLER

VECTOR BUS III

TIMING

TIMING

DIGITALPATTERNMEMORY

DIGITALFORMATTER

ANDTIMING

GENERATOR

DIGITALCHANNEL

CARD

DEVICEUNDERTEST

ANALOGCHANNEL

CARD

ANALOGCONVERSION

ANDFILTERING

ANALOGWAVEFORM

MEMORY

ANALOGSEGMENT

CONTROLLER


round. The timing generator controlswhen the edges are applied. Thisinformation determines when theDUT receives data and when devicegenerated data is strobed to evaluateits logic states.

The Digital Channel Card provides acontrolled electrical interface for thedigital signals to the DUT, with levelcontrol of the digital driver and voltagethresholds for the comparators on thechannel card.

The analog signal sources and mea-surement capabilities of the mixed-signal test system are architected in asimilar manner to that above. Thebuilding block concept of the VLSI

architecture is applied to the analoginstrumentation, as shown in figure 4,with four basic analog building blocks:

• Analog Segment Controller

• Analog Waveform Memory

• Analog Conversion and Filtering

• Analog Channel Card

The Analog Segment Controller isanalogous to the Digital PatternMemory. It governs the waveformmemory sequencing, which containsdigital samples representing theanalog waveform that will be pro-duced. Controller functions includelooping, repeating, and executingthe subroutines that generatecomplex waveforms for testing

devices such as video processors andmultimedia components.

The Analog Waveform Memorycontains the digital samples thatrepresent the analog waveforms to beproduced. Segments of the waveformmemory contain the digital representa-tion of independent analog waveformsthat, under control of the AnalogSegment Controller, can be called inwhatever sequence is needed togenerate as complex an analogwaveform as necessary to test a device.

The Analog Conversion and Filteringblock converts the digital waveformsamples to a continuous, full scaleanalog waveform, and filters it to

Figure 4Analog mixed-signal test system architecture

DIGITALPATTERN

CONTROLLER

VECTOR BUS III

TIMING

TIMING

DITIGALPATTERNMEMORY

DIGITALFORMATTER

ANDTIMING

GENERATOR

DIGITALCHANNEL

CARD

ANALOGCHANNEL

CARD

ANALOGCONVERSION

ANDFILTERING

ANALOGWAVEFORM

MEMORY

ANALOGSEGMENT

CONTROLLER

DEVICEUNDERTEST


remove any extraneous high fre-quency components that result fromthe conversion process.

The Analog Channel Card adjusts theamplitude, offset and impedanceenvironment of the signal prior to itsapplication to the DUT.

Because the analog and digital instru-mentation are handled on a per pinbasis and are configured with the samebuilding-block architecture, program-ming the analog instruments is verysimilar to programming the digitalinstruments and these capabilities can

support both component and func-tional testing. Test programs can bedeveloped and placed on-line quickly.

An example of just one area where anA585/A575/A565 series mixed-signaltest system can reduce test timedevelopment over a VLSI test system,is when measuring time betweenevents in testing digital functions,pseudo-asynchronous events or phaselocked loops, etc. In the VLSI testsystem, an edge find using a binarysearch is used to determine when adigital edge occurs, and is repeated todetermine time between two events.

The edge find algorithm can consumeboth a great deal of development timeto implement and more test time thandesired in production. In the A585/A575/A565 mixed-signal test systems,the time between events can bemeasured directly with an analoginstrument used for time measure-ment in a “single shot,” making it easyto program and fast to execute.


memory in the digital instrumentationthat is just like the analog instrumentwhere samples of the waveform arestored. The waveform samples aredescribed just like an analog instru-ment in terms of level, frequency,phase and waveform type.

With the waveform sourcing andmeasuring in common between theanalog and digital portions of the testsystem, programming the A585/A575/A565 series of mixed-signal testsystems is straightforward.

Another commonality between theanalog system and a mixed-signalsystem is in measuring dc characteris-tics of the device pins. Just as ananalog system provides a V/I per pincapability, the mixed-signal testsystem can do the same with theaddition of a V/I per digital pin. Thiscapability provides for the easydevelopment and fast execution ofcontinuity and leakage testing on alldevice pins.

The A565 member of the A585/A575/A565 series of test systems canbe configured as an analog onlysystem. However, as your testrequirements grow, digital instru-mentation can be added. Thus theanalog test techniques that you areaccustomed to can be used in analogtesting as well as with analogdevices containing digital or inte-grated mixed-signal devices. In thesame manner that the instrumentsin an analog test system share acommon timing reference in orderto be synchronized, the digitalinstrumentation in a mixed-signalsystem is also tied to the samereference. This ensures that bothanalog and digital signals will besynchronized so that Digital SignalProcessing techniques can be usedto make the test measurements. Seefigure 5.

When performing analog testing, theDUT output can be sampled by ananalog digitizer and stored in a capturememory to be processed later. If thedevice output is digital data from anA/D converter, the mixed-signal testsystem can capture the waveformsamples into a memory to be pro-cessed later.

When generating waveforms into thedevice, the analog test system providesa memory-based instrument wheresamples of the waveform are stored.The waveforms are described in termsof level, frequency, phase and wave-form type. If the device requiresdigital inputs to a D/A, then themixed-signal test system has a

The Evolution From Analog ToMixed-Signal Testing


MIXED-SIGNAL

INTEGRATION

LOW AVERAGE SELLING PRICE/HIGH VOLUME HIGH AVERAGE SELLING PRICE/LOW VOLUME

D I G I T A L

A N A L O G

Figure 5Evolution of analog/analog-with-digital/mixed-signal test


testing. Options are available thatsupport 400 MHz performance.

Despite its smaller footprint, the A575test system can support up to 128digital pins. Although the smallercabinet limits the total number ofinstruments per single system, theA575 can be configured with much ofthe same analog and digital instrumen-tation available for the A585, with theexception of some synchronizedpower instrumentation.

The A565 is a highly modular testsystem. The basic A565 systemsupports instrumentation for any dcapplication. Power, ac or digitalinstruments can be added to create alow-cost mixed-signal test system,with performance similar to the A575and A585 systems.

The following sections describe eachsystem. Common elements include:

• Vector Bus III Architecture

• Universal Bus Architecture

• Dual Computer Architecture

• IMAGE Software System

The A585/A575/A565Advanced Mixed-SignalTest Systems

Regardless of your testing experi-ence, mixed-signal testing in theA585/A575/A565 series mixed-signal test system environmentwill be familiar to you. The build-ing-block architecture, synchroniza-tion between analog and digitalinstruments, and the IMAGEprogramming environment, allcontribute to the high level ofintegration within the A585/A575/A565 Series of Advanced Mixed-Signal Test Systems.

Each of the test system models withinthe A585/A575/A565 series are subsetsof one another. Most of the analog anddigital instruments are available forany of the models in the series. Themaximum number of pins supportedand the maximum number of instru-ments contained within each systemreflects the limitations of each. Foradditional information regarding thespecific system configurations, pleaserefer to the System Configurationsection of this document.

The A585 Advanced Mixed-SignalTest System provides the greatestconfiguration flexibility. A singlesystem can contain up to 192 digitalpins, support microwave instrumentscapable of generating 4 GHz andmeasuring 6 GHz analog waveforms,provide up to 750 volts dc withsynchronized power instrumentation,and measure sub-picoAmps withadvanced linear instrumentation. Thedigital pins support 200 Mbit/s datarates and both synchronous andasynchronous dual time domain


The Vector Bus III illustrated in figure6 is the foundation of the A585/A575/A565 Series of Advanced Mixed-Signal Test Systems. Five key featuresprovide the flexibility needed to testcurrent and future mixed-signaldevices:

• TimeMaster™ Clock Synchronization

• MultiSource Data Mixing

• Mixed-Signal Microcode™ Control

• MultiSync TimeGen™

• MultiState Memory Store

TIMEMASTER CLOCKSYNCHRONIZATIONOne of the most critical mixed-signaltester requirements is that both analog

The Vector Bus Architecture


SEQUENCECONTROLMODULE

VECTOR BUS IIITIMEMASTER CLOCK SYNCHRONIZATIONMULTISTATE MEMORY STOREMULTISYNC TIMEGENMULTISOURCE DATA MIXINGMIXED-SIGNAL MICROCODE CONTROL

MIXED-SIGNALTEST HEAD

DIGITAL SIGNALWAVEFORM MEMORY

AND CONTROL

ANALOG WAVEFORMMEMORY AND

CONTROL

ANALOGFORMAT

CONVERSION

ANALOGCHANNEL

CARD

DIGITAL FORMATAND TIMING

DIGITALCHANNEL

CARD

Figure 6The A585/A575/A565 series Vector Bus III architecture

and digital instruments be synchro-nized to a common timing reference.The TimeMaster Clock in figure 7provides the common reference for allanalog and digital pins. The highlyaccurate 10 MHz reference, along withthe frequency synthesizer and associ-ated circuitry, generates an extremelylow jitter clock that is programmableover a 160 MHz to 200 MHz range.

The digital and analog clocks arederived from the TimeMaster Clock.The digital subsystem generates twoclocks: a C0 clock, also referred to as adevice system clock, and a T0 clock,referred to as the data clock or thevector rate clock. The T0 clock drivesthe digital pattern cycle time.


The C0 clock is an integer divide fromthe TimeMaster Clock and the T0clock is an integer divide from the C0clock. Clock rates range from 50 MHzor 25 MHz depending on the systemconfiguration, down to 4.88 kHz. Forexample, when testing a microproces-sor, the C0 clock may operate at32 MHz and the T0 clock at 8 MHz.In this case, the digital patterns can becompressed in size and complexity by4:1, eliminating the need to repeatdata vectors.

The A585/A575/A565 series alsoprovides 1,023 timing sets for per-pin

timing changes on-the-fly while digitalpatterns are executing. The C0 andT0 clocks can be independentlymodified on-the-fly, permitting deviceread and write timing cycle changesthat may be necessary when testingon-board memory.

The analog clocks in the test systeminclude four integer clock dividersthat provide independent genera-tion of clocks from 2.5 kHz to 50MHz. These clocks distributetiming to all ac instruments. Each acinstrument can select any analogclock as its sampling reference.

The A0 clock includes a featurerequired when generating analogsignals that contain program controlledjitter. Microcode commands thatincrement and decrement the A0divide value can be issued from thedigital pattern. These commands,which can be issued to the A0 clock atdigital vector rate speeds of 50 MHz or25 MHz depending on systemconfiguration, allow generation oftriangular, sinusoidal, and multifre-quency jitter patterns.

10 MHZREF

TIMEMASTERCLOCK

1,023TIME SETS

TODATA CLOCK

CODEVICE CLOCK

SEQUENCE CONTROL MODULE (SCM)

DIGITAL CLOCKS AND DATA4.88 KHZ TO 50 MHZ

AC INSTRUMENT CLOCKS2.5 KHZ TO 50 MHZ< 1 HZ RESOLUTION

DIVIDERINC/DEC

A0 A1 A2 A3

160-200 MHZ (4 HZ RESOLUTION)

Figure 7TimeMaster Clock Synchronization


MULTISOURCE DATA MIXINGMixed-signal and VLSI device testingrequire that digital patterns exercisethe digital blocks. When performingtruth table tests, a digital pattern fromdigital design simulators can be usedto drive and compare deterministicdigital patterns.

In order to test devices containing D/Aand A/D converter components, thetest system must be able to generate orcapture digital representations ofanalog signals also referred to as digitalsignals. This data can be expressed asa sine wave at a specific frequency andlevel with a specific digital code formatsuch as sign plus magnitude.

Since the data associated with testingan A/D converter is non-deterministic,the system must be able to capture thedata rather than run a truth tablecomparison of the data. The captureddata is then processed by the DigitalSignal Processing (DSP) algorithms todetermine performance of the A/Dcomponent.

Because many manufacturers areintegrating SCAN technology forincreased digital fault coverage,mixed-signal systems must haveSCAN testing capabilities, whichrequire very deep serial patterns ofconfigurable pin width.

The Vector Bus III MultiSource DataMixing provides additional memoriesin the A585/A575 for efficientlyhandling SCAN requirements anddigital signal source and capture. Thememories are available to any digitalpin under program control. TheAlternate Data Bus allows each digitaltester pin to select digital pattern,digital signal, or digital SCAN capabil-ity, and provides the ability to switchthe selections on-the-fly. See figure 8.Access to different types of memorywith the Alternate Data Bus simplifiesdevice interface board design byeliminating the need for “special”digital pins.

Figure 8Mixing of SCAN, pattern and digital signal data selected per pin

DIGITALCHANNEL

CARD

VECTOR BUSMEMORY

TEST HEAD

PCM DATA

DIGITAL PATTERN SCAN DATAALTERNATE DATA BUS

DIGITAL PATTERNMEMORY


AND CONTROL



MIXED-SIGNALMICROCODE CONTROLWhen testing AVLSI system silicon,the ability to control when analoginstruments begin to generatewaveforms or capture signals iscritical. Mixed-Signal MicrocodeControl allows the digital pattern todeliver microcode commands to the

analog instruments on a vector byvector basis, as illustrated in figure 9.This capability is referred to asVector-Locking™.

Vector-Locking ensures repeatability.For example, as shown in figure 10,when testing an analog-in to analog-out function, an analog source could

begin after 100 clock cycles. Then,after a 20 clock cycle settling time, theanalog output could be captured witha waveform digitizer. Every time theprogram runs, the same waveform willbe sent on the 100th device clockcycle, and capture will begin on the120th clock cycle. This lockingprovides precise control of analog and

SEQUENCECONTROLMODULE


ALTERNATE DATA BUS

ANALOGWAVEFORM MEMORY

AND CONTROL


AND CONTROL

DIGITALCHANNEL

CARD


ANALOGCHANNEL

CARD


ANALOG FORMATCONVERSION

Figure 9Vector Bus III delivers the Mixed-Signal Microcodes directly to theanalog instrument memory controller.


Figure 10Mixed-signal microcode provides Vector-Lockingbetween the analog and digital instrumentation.

CLOCK

DATA

ANALOG SOURCE

DIGITIZE START

REPEAT19

REPEAT99

START

TRIG

digital waveforms and also enhancestest measurement repeatability,reducing guardbands.

Vector-Locking is also used whentesting a device that demodulatesanalog waveforms into digital bits, as ina FAX modem device. The digital

pattern performing the bit comparisondetects exactly when the analog signalbegan. If the analog source beganunder computer control, the startingphase would be different from thedevice clock phase. This phasediscrepancy will cause errors in the bitstream that is generated by the device.

As shown in figure 11, each analoginstrument has a unique set ofmicrocode that is available at everydigital vector.


Figure 11The Mixed-Signal Microcode is programmed in thedigital pattern to control the analog instruments ateach vector cycle.

PATTERN MICROCODE MIXED-SIGNAL MICROCODE DATA


MULTISYNC TIMEGENAs mixed-signal devices appear inincreasingly diverse applications, theymust function in asynchronousenvironments. In particular, communi-cations network devices must convertdata over a wide range of frequenciesto standardized frequencies fortelephones and data terminals. Thetester must simulate real worldasynchronous problems so that themanufacturer can identify and correctdevice faults.

As shown in figure 12, the A585/A575 test system Vector Bus IIIarchitecture can be configured as a

dual Vector Bus system. Essentially,two Vector Buses, two digitalsystems, and two sets of analoginstruments can be assigned todifferent parts of the device, provid-ing true asynchronous test capabil-ity. The two Vector Buses canhandshake with each other toresynchronize and help performfault diagnosis. This means the testsystem can perform as two separatemixed-signal test systems runningasynchronously or synchronously.

MultiSync TimeGen can economi-cally accommodate a multitude ofapplications. Some applications

require only asynchronous analogsignals while others require bothasynchronous analog and digitalsignals. MultiSync TimeGen can beconfigured to meet any of these needscost effectively, adding clocks or a dualdigital sequencer as needed.

As shown in figure 13, MultiSyncTimeGen may contain two masterclocks: a TimeMaster Clock and anAlternate TimeMaster Clock.Digital and analog clocks can beprogrammed to either TimeMasterclock, providing maximum fre-quency flexibility. In addition,two auxiliary analog clocks, pro-

SEQUENCE #2CONTROLMODULESEQUENCE #1

CONTROLMODULE



ANALOGWAVEFORM

MEMORY


AND CONTROL

ANALOGWAVEFORM

MEMORY

DIGITALCHANNEL

CARD

PROGRAMMABLEDUAL VECTOR BUS SYSTEM


ANALOGCHANNEL

CARD


AND CONTROL


ANALOG FORMAT

CONVERSION

Figure 12The A585 can perform synchronous and asynchro-nous testing using a dual Vector Bus system.


grammable from 40-200 MHz, areavailable for use with the ac instru-mentation. There is also an Auxil-iary TimeMaster Clock for use withthe Sampler only. In order toguarantee frequency coherency, all

clocks link to a common 10 MHzfrequency reference.

MultiSync TimeGen also has anadditional digital pattern sequencer.Groups of 64 digital pins can be

Figure 13MultiSync TimeGen provides multiple clocks and two independent time domainsystems for asynchronous testing.

TIMEMASTERCLOCK

10 MHZREF

COCO

T0 T0

A1 A2

ANALOG INSTRUMENTSDIGITAL PINS

A0

ALTERNATE TIMEMASTER

CLOCK

AUXPACS CLK1

AUXPACS CLK2

ADDITIONALSAMPLER CLK

SCM1 SCM2

MULTISELECT MULTISELECT

SELECT

A4 A1 A2A0 A4

programmed to select one of twosequencers. Each sequencer operatesasynchronously. The second se-quencer can use either the standardTimeMaster Clock or the AlternateTimeMaster Clock.


VECTOR BUSMEMORY

SETSMEMORY


ANALOG WAVEFORMMEMORY AND

CONTROL


AND CONTROL

DIGITALCHANNEL

CARD

ANALOGFORMAT

CONVERSION



ANALOGCHANNEL

CARD

MULTISTATE MEMORY STOREThe number of digital device pinsand the combinations of operatingconditions on analog pins areincreasing rapidly, and all must betested. A common AVLSI devicetest, four corner testing, requires afunctional test at minimum/maxi-

mum timing conditions over mini-mum/maximum voltage. MultiStateMemory Store, shown in figure 14,meets this requirement by providinga 1 Meg deep SETS memory thatcan perform high-speed reload ofthe digital channel card dc attributes(V

IH, V

IL, V

OL and V

OH ) and high

speed timing set reloads. Also, theVector Bus memory can providereload capability of pattern memory.

Figure 14MultiState Memory Store provides high-speedreload of timing and dc attributes of digital pins andpatterns for high pin count devices.


Advanced analog and high powerdevice testing requires synchroniza-tion and waveform linkages be-tween instrumentation. Teradyne’sUniversal Bus architecture meetsthis need. See figure 15. Timingcontrol of the DUT and testerinstrumentation is critical whentesting high power devices. Whilethe high speed digital pins in thetest system drive low power DUTcontrol pins, the trigger drivenpower instruments deliver synchro-nized power events to DUT poweroutputs. When operating in pulsemode, the power instruments attaina high instantaneous power level.Control is critical. Proper timingprevents device destruction whenevaluating parameters such asthermal die attach. Timing controlensures that measurements are not

influenced by device warming dueto power dissipation.

For example, consider testing the ONresistance of a FET switch that isembedded in a mixed-signal device. Ifa high current is sent through thedevice for too long, the FET ONvoltage will begin to rise due tothermal runaway. Measurements mustbe made before this occurs. Thepower instrumentation timing controlturns on the pulse for a predeterminedamount of time, strobes the meter, andpulses the current on only longenough to make the measurement.See figure 16. A test engineer can also“trap” on this test without damagingthe DIB circuitry.

The versatile Universal Bus architec-ture provides the control for high

Universal Bus Architecture

Figure 15The Universal Bus Architecture

TRIGGER BUS MEASURE BUS

MODULATION BUS THADS BUS

UNIVERSAL BUS ARCHITECTURE

ANALOGINSTRUMENT

ANALOGINSTRUMENT

ANALOGINSTRUMENT

DEVICEUNDERTEST


CONTROL

V

I

CURRENT (A)20

10

10 20 30 TIME (MS)

DUTVOLTAGE

METERSTROBE

V

Figure 17The Universal Bus Architecture has two timingelements — the Trigger Bus and the TimeMasterPulse Clock.

Figure 16When the device dissipates substantial power,thermal effects can alter its measurements.

STOP_AFTER_START

STARTSTOP

10 MHZ VECTOR BUS REFEXTERNAL CLOCK 1 & 2

TRIGGER BUS #

CPU

PULSEGENERATOR

TIMING TIMING

CLOCKGENERATOR

DUTY CYCLEGENERATOR

PART OFSYNCHRONIZED POWERSUBSYSTEM

TIMER 2PROG DELAYPROG WIDTH



CPU


CPU I/F



quality, maximum throughput testingof analog and power componentsembedded in mixed-signal devices. Itconsists of four essential elements:• Trigger Bus

• Measure Bus

• Modulation Bus

• Test Head Analog Distribution Bus(THADS)

TRIGGER BUSThe Trigger Bus is made up of aTimeMaster Pulse Clock and aninternal timing bus. TheTimeMasterPulse Clock provides multiple timingcontrols to the instruments in the testsystem. As shown in figure 17, thereare two parts to this clock: a set ofpulse generators for controlling powerinstruments and a repetitive pulse and

clock generator for controlling ad-vanced analog instrumentation.The pulse generators contain fourprogrammable delay and pulse widthtimers with timing ranges from 1.3 msto 1.6 s. Each timer has 200 ns pro-grammable resolution. The timers canreceive a start signal from the timingcontrol bus or from the CPU.

The repetitive pulse and clockgenerator can receive reference inputfrom a variety of sources. It can accessthe internal tester 10 MHz referencefrom the Vector Bus III, use one of twoexternally generated clock sources, orget a reference from another instru-ment connected to the Trigger Bus.Programmable dividers adjust thepulse width and frequency of thegenerated pulses. From the 10 MHz

reference, the TimeMaster Clock cangenerate pulse widths from 100 ns to6553.6 µs and frequencies from 10MHz to 153 Hz. The clock can besourced to a timing control bus as aclock signal, or can be gated on and offdirectly from the test program or fromother bus signals. A pulse counter canstop the clock after a predeterminednumber of pulses.

The Trigger Bus also contains aninternal timing control bus thatconnects all synchronization signalsbetween the instruments and theTimeMaster Pulse Clock througheight differential ECL lines. Seefigure 18. Every instrument thatinterfaces to the Trigger Bus canreceive or send synchronization signalsthrough one of the eight trigger lines.

Figure 18The Trigger Bus provides well-controlled,repeatable power testing by connecting the timingof all the power and analog instruments together.

TIMEMASTERPULSE CLOCK

88888888

ANALOGINSTRUMENTS

ANALOGINSTRUMENTS


DEVICEUNDERTEST

TRIGGER BUS


Instruments that contain a Trigger Businterface can generate controlled testpulses to the device and synchronizeevents between instruments bylistening to start and stop signals.The test computer can access any ofthe bus lines through theTimeMaster Pulse Clock. Thestandard test system dc meter alsointerfaces to the Trigger Bus.

MEASURE BUSThe Measure Bus, represented infigure 19, allows different instrumentsto access the meter system. Ratherthan internal A/D converters in each

instrument, a high-speed, high-accuracy meter in the system accesseseach instrument via the Measure Bus,providing a cost-effective solution withno impact on test time. For instru-ments so configured, the Trigger Buscontrols when an instrument isconnected to the Measure Bus andwhen the meter strobes the signal onthe bus.

MODULATION BUSWhen running power supply rejectionratio (PSRR) and common moderejection ratio (CMRR) tests on analogand mixed-signal devices, this bus

routes ac instruments to modulate V/Isupplies to determine if the devicecan reject ac signals.

The Modulation Bus provides a 180kHz bandwidth interface for many ofthe instruments in the system. Thebus is a shielded, differential pair ofsignal wires that allows multipleinstruments to be modulated from asource. Thus, multiple device pinscan be modulated simultaneously asrequired in some crosstalk testing.Individual pins can be modulated aswell, to determine device rejectioncharacteristics. The performance on

Figure 19Universal Bus Architecture measurement busallows shared metering.

ANALOGINSTRUMENT

ANALOGINSTRUMENT

ANALOGINSTRUMENT

DCMETER

DEVICEUNDERTEST


MEASURE BUS


any particular pin is limited by thecharacteristics of the modulatedinstrument.

TEST HEAD ANALOG DISTRIBU-TION SYSTEM (THADS) BUSThe Test Head Analog DistributionSystem (THADS) Bus is an ac matrixthat runs between each of the analoginstrument channel cards in the testhead. THADS is a shielded differen-tial bus that allows an instrument toaccess multiple device pins. Also, if adevice pin requires different types of

instruments in order to perform allrequired tests, the THADS bus can beused to deliver the instruments to thedevice pin.

For example, if a device has multipleinput pins to an on-board A/D con-verter, the tester analog source can beaccessed through the THADS Bus toeach input pin. This capabilityeliminates the need for the user tobuild a complex relay matrix to deliverthe source to each device pin on thedevice interface board.


The A585/A575/A565 series of testsystems uses a dual computer platformto meet the demands of mixed-signaltest. Dual SPARC® computers areused to provide maximum through-put. The dual computers process theadditional calculations necessary forfinal test results and instrument setupchanges, Ethernet and local disk drivecommunications. The dual computerscommunicate with each other over anEthernet link.

One computer interacts with theuser and the network providingtest program development sup-port, data analysis, management ofprogram loading, and data trans-fers during testing.

The second computer runs the testprogram without interruption from theoutside world. This maximizesthroughput and provides repeatabletest times for predictable test capacity,which is very important to ensureproduction schedules.

The SPARC user computer from SunMicrosystems provides the followingset of features:

• microSPARC-II processor 57SPECint92; 43.7 SPECfp92

• 32 megabyte standard memory,expandable to 256 megabyte

• 1.5 gigabyte standard disk drive,expandable with up to 2 gigabyte

• Ethernet controller

• RS232/RS422 serial port

• A high resolution 1562 x 900 17 inchgraphics terminal with mouse

Dual Computer Architecture

The second SPARC is the testcomputer, which has the following setof features:

• microSPARC-II processor

• 32 megabyte standard memory

• One RS232/RS423 serial port withoptional expansion available

• Optional IEEE interface

The A585/A575/A565 also contains ahigh-speed array processor to performall DSP calculations. The test com-puter sends a list of calculationinstructions for the array processor tooperate on multiple sets of data. Whilethe array processor performs thosetasks, the test computer continues toexecute the test program, virtuallyeliminating the DSP execution time.This pipeline approach is possiblebecause the array processor has its ownlarge data memory to store all the dataneeded for calculations.

The array processor used on the A585/A575/A565 is the Mercury MC860processor, which has 4 megabytes ofmemory, expandable to 16 megabytes.It performs 80 M floating pointoperations per second and can operatein either single or double precisionmodes. Devices that contain 20 bitresolution sigma-delta convertersrequire double precision operation toavoid introducing mathematicallygenerated noise to the test results.


COMPUTER NETWORKINGAll Teradyne device test systems canbe networked directly via Ethernetand to each other, as well as to simula-tors and other equipment. All systemsuse the standard TCP/IP protocol.Additional communications interfacesare supported by the software environ-ment for control of external equip-ment such as handlers and probers.These interfaces include:

• Parallel interface

• RS232 interface

• IEEE interface communication

SUN ETHERNET NETWORKINGA585/A575/A565 series hardware andsoftware tools allow you to reach the

Figure 20SUN/A500 Family networking

market 40 to 70% faster than other testsystems. Furthermore, 70% of testprogram development can be per-formed off-line at a stand-aloneworkstation using IMAGE™ software.To support this large amount of off-line test program development, theA585/A575/A565 series offers Ethernetnetworking. See figure 20. Thisnetwork feature supports the followingfunctions:

• Test program development

• Engineering and characterizationdata analysis

• Pre-production test program filelibrary management

• Complete data analysis

NETWORKING AND X WINDOWSThe Sun networking capability, incombination with the X Windowswindowing standard, provides an evenmore powerful test development andproduction environment. Remotelocations on a network can be viewedand operated from your local worksta-tion. This can be as basic as examiningdatalog results from the test floor or assophisticated as actually operating thetest system remotely.

A575

PRIVATE ETHERNET

PUBLIC ETHERNET

SERVER

A585 A575

A535

SIMULATOR WORKSTATIONS

A565


IMAGE Software System

Interactive Menu-Assisted GraphicsEnvironment (IMAGE) software forthe A585/A575/A565 series representsan innovative approach to ATEsoftware. IMAGE software uses thepower of the test system’s dualcomputer architecture and builds onthe strengths of the UNIX operatingsystem and the C language (bothindustry standards). An advanced win-dowing environment using the SunOpenWindows graphical user interfaceprovides graphics-oriented, computer-aided testing tools that are highlyinteractive and focused on the require-ments of AVLSI testing. The result isa test program development environ-ment which dramatically reducestime-to-market for AVLSI devices.

The computer-aided testing toolsprovided by IMAGE software for testprogram creation, debugging, andcharacterization all use this advancedwindow system. This powerfulcombination provides a highly-interactive environment where mostcommands are executed withouttyping at the keyboard. Hardwarestatus display windows, for example,use graphics windows to clearly showthe state of the test system hardware.This high-resolution graphics windowsystem makes test program develop-ment much faster than conventionaltext-editing, keyboard-orientedapproaches.

To further reduce test programdevelopment time, all of the docu-mentation for the A585/A575/A565series, as well as for IMAGE softwareand its components, is available on-

line from Teradyne’s IMAGE Answerson-line documentation. Updates of theIMAGE Answers documentation areprovided with each release of IMAGEsoftware. See figure 21.

CUSTOMIZED ATE DUAL-COMPUTER OPERATINGENVIRONMENTThe IMAGE software system custom-izes UNIX for ATE applications toprovide an operating environmentfocused on the needs of test programdevelopment and production testing.This operating environment makesthe dual-computer architecturetransparent to the user. The userinteracts with the system through asingle user interface on the usercomputer. Operation of the testcomputer is controlled automaticallyby the operating system.

ETHERNET TCP/IP NETWORKINGSOFTWARE WITH NETWORK FILESYSTEMThe IMAGE test system executiveprovides Ethernet TCP/IP network-ing software with Sun Microsystem’sNetwork File System (NFS) tosupport test program development,data analysis, and characterization on alocal network of Sun workstations.

IMAGE PROGRAMMINGIMAGE software corrects the weak-nesses of unstructured, tester-orientedlanguages and conventional compilersand interpreters. The IMAGE testlanguage is device pin-oriented andorganized into modular tests andfunctions. It is a superset of industry


Figure 21IMAGE Answers on-line documentation


Figure 22IMAGE production environment

standard C. Its interactive compilerprovides very fast turnaround by onlyrecompiling and linking sections of atest program that have been modified.The interactive compiler producesfully compiled code for very fastprogram execution.

In the IMAGE test language, theentire C language is fully supported. Cstatements are useful for such tasks asdeclaring variables, controlling pro-gram flow, and performing arithmetic

calculations. To control the test systemhardware and the DUT, the IMAGEtest language provides high-levelinstrument commands customized foreach test system instrument.

Instrumentation DriversEach test system instrument has asoftware driver written in C, anefficient language, for fast executionand high throughput. These softwaredrivers control the test system hard-

ware by implementing the high-levellanguage commands that are part ofthe test language. A test engineerprograms the hardware using easy-to-understand commands such as “set<instrument>” and “start <instru-ment>.” These commands aretranslated into instructions for eachsoftware driver. (Also see Device PinOriented Language, later in thissection.)


Digital Signal ProcessingSoftware LibraryTesting mixed-signal AVLSI deviceson the A585/A575/A565 series of testsystems is done using digital signalprocessing techniques for characteriz-ing analog ac waveforms and digitalsignals. A large selection of DSPalgorithms including Fast FourierTransforms (FFT), vector-vector,vector-scalar, and matrix operations isprovided. These algorithms run on a32-bit floating point array processor(operating at 80 MegaFLOPS), forunmatched device characterizationand high throughput. The arrayprocessor is available with either 4-Megabyte or 16-Megabyte memory.

TEST PROGRAM ORGANIZATIONThe structured organization of anIMAGE test program facilitates testprogram development, debugging,and maintenance. An IMAGE testprogram is organized in five mainsections making programs much easierto understand and maintain:

• Binning Strategy

• Pinmap

• Sequencers

• Tests

• Functions

Binning StrategyThe Binning Strategy section is asoftware association of soft bins (usefulin the summary) and pass/fail deter-minators to hard bins (sent to handler/prober). This allows multiple soft bins

SequencerThe sequencer defines and controlsthe flow of a test program. Seefigure 23. The main elements of asequencer are:

• Test name

• Test number

• High and low limits

• Test label

• Pass, fail, and close bin for down-grade binning when multiplebinning strategies are implementedfor a device type

A quick look at a sequencer immedi-ately shows, as in a specificationssheet, the tests performed, the order ofthe tests, the pass/fail conditions, andthe binning strategy. In contrast, testprograms on other testers force you toexamine the whole program tounderstand which tests are performedand to locate the test limits. Thismakes maintenance of test programs

(multiple device grades) to be mappedto a pass condition and multiple softbins (for yield analysis) to be mappedto a single hard bin. This section alsoallows the declaration of test condi-tions such as hot, cold, room, etc.,which can be set at program load time.

PinmapThe IMAGE Pinmap is a software“wiring diagram” that describes theconnection between the test systemchannels and the DUT pins. TheDUT pin names defined in thePinmap are used in the device pin-oriented programming language thatis described below.

Collections of pins can be grouped andgiven a symbolic name — this istypical of bus-oriented digital inter-faces. An entry can also be made in thepinmap to check the DIB ID code.This ensures that a program can onlybe executed if the correct loadboard isinstalled on the test system.

PIN NAME DIB/CONFIG CHANNELpinmap={

1 "D1" dib:h_7 hsd50_rcv:1,

2 "Ain" dib:14a1 plfsrc_hi,

3 "Vcc" dib:27a1 dutsrc,

4 "GND" local,

.

.

};

Table 1Example of actual syntax for device pinmap


section of a test program which issimilar to a subroutine or procedurein other languages. A test is a specialtype of function designed for use ina device test program. Tests arecalled from the sequencer wheretheir order of execution is defined.A test contains statements to controlthe hardware and to return testresults to the sequencer. Thisstructured organization allowsinteractive development anddebugging of test functions sinceonly modified tests must be recom-piled and linked to the rest of thetest program.

extremely difficult, especially bypeople who did not write them.

Unlike other test program softwaresystems, IMAGE test programs cancontain multiple sequencers. Onesequencer may be used for hot test,another for cold, probe, QA, etc. Allcan be contained in one test program,simplifying program maintenance.

Tests and FunctionsFunctions are the basic buildingblocks of a test program. A functionis an independent executable

Device Pin-Oriented LanguageA test engineer, when developing testprograms, thinks about the devicebeing tested, not the tester. TheIMAGE test language uses high-levelcommands that are device pin-oriented, not tester-oriented. Thisapproach allows great flexibility andmakes programming much easier.On the A585/A575/A565 series,device-to-system connections areprogrammed once. After this is done,instruments connected to the DUTcan be programmed using device pinterminology. For example, to program

Figure 23IMAGE station window with sequencer


Contrast this approach to a tester-oriented language where commandsmust refer to test system resources. Toduplicate the Vcc programming above,a test engineer must search throughthe test program to find which powersupply is connected to the Vcc pin andwrite a command to control thespecific hardware used. All this makesprogramming difficult and mainte-nance even worse, adding to the time

and resources required for programdevelopment.

The device pin-oriented languagesupports the dc instruments, acinstruments, and all digital channels onthe A585/A575/A565 series systemhardware using high-level commands.This is key to the IMAGE softwareenvironment providing full support forparallel device testing.

Figure 24IMAGE station window with trap and menu

the DUT source connected to thedevice pin named “Vcc” to 5 Vrequires the following programming:

set pin=Vcc src v=5volts;

Notice that the name or number of thesource is not needed in this program-ming statement. Only the name of thepin (Vcc) need be programmed.


INTERACTIVE TEST PROGRAMEDITOR AND DEBUGGERIMAGE software is the ideal tool fordeveloping test programs. It includesediting and debug tools. See figure 25.When you log onto the tester, a stationwindow opens. This represents theuser’s interface to the test system.Each station window is divided intoseveral sub regions. For instance, thestation window in figure 23 has acommand region and a button region.Any command can be executed by

Source-level Debuggerwith BreaktrapsAfter loading a test program, source-level debugging is begun by selectingthe debug command. A test programsource region opens automatically anda breaktrap can be selected using themouse at any time, indicated by agraphic stop sign (figure 24).

selecting that command using themouse (“clicking on” it) in the buttonregion. Each command can also betyped in the command region insteadof using the mouse.

Text from IMAGE Answers, such asprogramming examples, can be copieddirectly into the test program. Thishelps eliminate typing errors andfurther enhances the power of the on-line documentation environment.

Figure 25Debug displays


Incremental Compile forFast TurnaroundAfter using the editor to modify thetest program, the compiler is calledusing the mouse without leaving theediting environment.

The IMAGE compiler performsincremental compilation, which meansthat only the sections of the testprogram that were modified arecompiled. This technique providesfast turnaround. For example, if youonly change one test, you can compileand be ready to try out your changes inless than two seconds. This two-

second turnaround time does not varywith the size of the test program. Inaddition, the compiler outputs effi-cient, fully-compiled binary. There isno throughput penalty for interactiveresponse time.

Immediate Statement ExecutionImmediate commands are very usefulfor experimenting with the test systemhardware or with your device. Adedicated window is provided forimmediate statement execution. Youcan type any language statement ormultiple language statements and

Figure 26Pattern debugger showing column operation

have them incrementally compiledand executed immediately to tempo-rarily affect the state of the test systemhardware. You can even execute anentire function or file from thiswindow. A single-line immediatecommand executes in one second orless providing very fast turnaround. Itis very easy to edit an old immediatecommand or insert it into your sourceprogram. The immediate window hasediting capability built into it andkeeps a history of all immediatecommands you have executed.


INTERACTIVE DIGITAL AND ANALOGDESIGN AND DEBUG TOOLS IMAGE software includes manyinteractive, graphics-oriented toolsspecifically designed for developmentand debugging of digital vectors,digital signals, and analog waveforms.

Digital Pattern Editor andDebuggerThe IMAGE Digital Pattern Editorand Debugger provides a powerfuldevelopment environment custom-ized to the task of creating, modifying,and debugging high-speed digital

patterns in the shortest possible time.This editor allows you to easily specifythe device pin digital state data, vectorcontrol and Mixed-Signal Microcodecontrol instructions on a per-vectorbasis. The Pattern Editor displays thepattern in a spreadsheet-style. Editsare incrementally compiled on-the-flyfor very fast turnaround. Patterns canbe debugged on the hardware withoutleaving the editor environment. Seefigures 26 and 27.

When you complete a pattern editingsession, your pattern is saved to abinary file which can immediately be

loaded into pattern memory. Noseparate off-line compile step isrequired. The long compilation timesusually associated with digital patterndevelopment are eliminated. Theincremental compile capability of theDigital Pattern Editor makes patterndevelopment much faster than oncompetitive systems.

Another key feature of the PatternEditor allows you to select a device pinor group of pins and change their statedata without affecting other pinsdefined along the vector. Thesecolumn-oriented editing functions

Figure 27Digital pattern debug window


allow you, for example, to change thestate for one pin along the wholepattern with a single mouse operation.A pin or group of pins can be selectedand the data moved up and down bysome offset without affectingunselected pins.

Digital Pattern AdvancedLogic AnalyzerThe Digital Pattern AdvancedLogic Analyzer (figure 28) candisplay digital patterns at run-time.

Depending on the format used, theselection of timing sets and channelstate data, the “shape” of thewaveform going out of the digitaldriver and the expected windowsare displayed in the time domain.

The Digital Pattern Advanced LogicAnalyzer includes many featuresfound in advanced logic analyzers suchas pre- and post-triggering, functionswith “compression” of data usingdifferent radices such as hexadecimal,and a trace function to allow easy

debug of complex random patternswith conditional branches. The LogicAnalyzer can also “digitize” wave-forms using the comparator on thedigital channel card. This techniqueallows users to see exactly what thewaveform looks like at the comparatorand then to adjust the comparatorstrobe timing to get accurate andrepeatable test results.

Figure 28Digital Pattern Advanced Logic Analyzer


Digital Waveshape ToolsA major enhancement to the program-ming environment for the high-speeddigital subsystem is the suite of DigitalWaveshape tools (figures 29 and 30).

The Spec Table (figure 29) allowsdigital specification and test param-eters like setup/hold time to becaptured in an electronic “spec sheet.”Then the Timing and Levels Tool,

called DIGW, uses equations todescribe timing relationships in termsof these device specifications. This is avery powerful and flexible alternativeto describing the thousands of timing

Figure 29Digital waveshape tools – spec table window


relationships that are required in thedigital portion of a test program. Thisalso dramatically simplifies the devel-opment of characterization routines.

Analog Waveform DisplayFor creating, debugging, and modify-ing analog waveforms and digitalsignals, an interactive window-based

tool is available to display signals in thetime and frequency domains. Thedisplay window (figure 31) acceptsdata from multiple sources such as

Figure 30Digital waveshape tools – timing table window


digitizer capture memory, any wave-form segment, data array and files.Button commands are available tocontrol the displayed area. Smooth andzoom functions are available for a moreflexible display.

Using this tool, complex waveformscan be created, debugged, andmodified. The display functions areequivalent to a digital oscilloscope anda spectrum analyzer using digital signal

processing techniques. The tool canalso perform automatic waveformanalysis for faster characterizationturnaround.

Graphic InstrumentationStatus DisplaysThe A585/A575/A565 series contains avariety of instruments, each of whichhas many programmable features. Toprovide detailed information, eachinstrument has its own graphic display

in a separate window. At any time, youcan open or close a graphic icon of aninstrument for a detailed examinationof an instrument’s status. Instrumentsetup changes can be made by“clicking on” the graphic display; bypressing one button, the IMAGEcommands that program the setup canbe inserted into the program.

Figure 31Waveform displays for time and frequency domain


DATA ANALYSIS ANDCHARACTERIZATION SOFTWARE

Datalog ReportsIMAGE software provides powerfuldata collection and analysis tools. Datacollection can be set up duringcharacterization using IMAGEsoftware. Some datalog functions canalso be controlled by statements in thetest program. Datalog parametersinclude:

• Sequencer name

• Test number

• Test name

• Test value with pass/fail information

• Test limits

• Binning results

Summary ReportsWhile testing devices, the A585/A575/A565 series performs real-timeautomatic collection of test results,and, at any time, partial summaryreports can be displayed. At the end ofa lot, a final summary report is avail-able, which includes:

• Number of devices tested

• Bin categories with total number ofdevices

• Full report of failure history

Figure 32Wafer map

Real-Time HistogramsOn-line, real-time histogram andcorrelation software is available andcan perform analysis concurrently withdevice testing. Snapshot results andanalysis can be displayed using


statistical analysis tools. Figure 33shows a histogram analysis display.

Digital and ParametricShmoo PlotsShmoo plot parameters can be enteredand then executed from the testprogram or during debug (figure 34).Tracking parameters are possible on

Figure 33Data analysis tools – histogrammer, datalog,summary report

any axis, and mouse editing allowseasy development.

3-D Shmoo PlotsThe A585/A575/A565 series alsooffers an optional software productwith three-dimensional Shmooplotting. This powerful mixed-

signal analysis package allows twoparameters to be varied while athird parameter is measured. Theresulting “surface” can providemonths’ worth of characterizationdata in a matter of just a fewminutes, and the results are all onone graphic display (figure 35).


Figure 353-D Shmoo Plot

Figure 34Shmoo Plot


COMPUTER-AIDED TESTDEVELOPMENT

Additional IMAGE SoftwareTools: IMAGE ExPress™ andProGen™Optional software tools are designed toreduce test development time byautomating key steps in the creation oftest programs. The initial set of toolsincludes:

• IMAGE ExPress code-producingdisplay (figure 36), which allows testinstrument setup by simply “point-

ing and clicking” at a graphic displayusing a mouse. Then at the press ofa button, the program code toproduce the instrument setup canbe generated and inserted into thetest program.

• The ProGen test database manage-ment system, which simplifies themanagement of symbolic code testmodules and test program assembly.

• Device testing libraries in theProGen format, which provideproven test methods and waveform

data for a family of devices such asconverters, video, telecom, and diskdrive devices.

• Analyzer tools, which provide afamily-specific signal generationand analysis environment thatsimplifies device characterizationas well as program developmentand simulation.

Figure 36CATD tools - ProGen, IMAGE ExPress


Device Test LibrariesDedicated tools are available to helpthe test engineer when working withindustry standards for:

• Telecommunications devices (suchas filter/CODECs, ISDN and digitalcellular)

• Consumer devices (such as PAL,NTSC, or SECAM)

• Industrial and peripheral devices(such as disk drives and converters)

These tools provide the ability togenerate and analyze signals requiredto perform functional testing of mixed-signal devices. Also included are testprogram functions that allow you toeasily implement functional tests inyour test program (figure 37).

Sun Stand-Alone Workstationand Tester Simulation SoftwareIn the past, test programs weredeveloped using stand-alone systemsand software tools with limitedperformance. The A585/A575/A565series offers an off-line stand-alone

Figure 37Smith Chart and VectorScope


workstation with full tester simulationsoftware. This workstation uses thesame IMAGE software environmentand the same Sun computer as thetester. Thus, test engineers working atan A585/A575/A565 series workstationor at the test system use the samecommands for creating, editing,debugging, modifying, and maintain-ing test programs. This reduces testprogram development time andshortens the learning curve.

Using the Stand-AloneWorkstation While TestingDeveloping test programs on the Sunoff-line stand-alone workstation savesyou time in two ways. First, usingIMAGE software with its computer-aided software tools reduces programgeneration time by 50%. Second, in atypical production environment, about70% of test program development canbe performed on the Sun off-lineworkstation and 30% at the tester.This means that the stand-aloneworkstation reduces the time requiredat the tester for development (includ-ing editing, debugging, and mainte-nance) by up to 70%.

All A585/A575/A565 series hardware issimulated on this workstation andsome device responses can also beeasily simulated using data files forchecking and debugging the process-ing path of the test program. Forexample, digitized ac output datastored in the capture memory can besimulated using a known arrayrepresenting device output withknown defects. This data can beanalyzed using the test program DSPalgorithms supported by the Sunstand-alone DSP library. This methodallows you to debug the processingpath of the test program without usingtester time.

Digital Simulator SoftwareDigital patterns may come from CAE,CAD, or simulation tools with datapost-processed or handwritten. One ofthe most critical aspects of debuggingthese patterns is predicting any timingviolations that could reject gooddevices and pass failing ones.

The Sequence Control Modulecontrols random sequences ofvectors that may be conditional to

external events and to pass or failconditions. Jump operations, forexample, may have differentdestination addresses that may,depending on a timing set used,violate test system timing specifica-tions. The Sequence ControlModule simulation software makessure that timing hazards do notexist. This software tool runs on thestand-alone Sun workstation usingtools available with IMAGE soft-ware. When used with IMAGEsoftware, it can save as much as 40%to 60% of test program developmenttime for complex new devices. Infact, writing test programs for suchdevices may become impossiblewithout such computer-aidedtesting tools, just as designing suchdevices has become impossiblewithout CAD and CAE tools.


Simulation-Based DevelopmentUsing IMAGE ExChange™The goal of Test Simulation is toreduce the impact of test developmenton the time to market for new ICs.This can be achieved by enabling testdevelopment to begin earlier and inparallel with IC design. Test Simula-tion uses simulation technology toreduce the amount of debugging thatmust wait for the availability of devicesilicon and test time on the productiontest system. See figure 38.

The test engineer develops the entiretest package using a complete Test

Simulation environment. IMAGEExChange, which is at the center ofthis simulation environment, commu-nicates the state of the simulated testsystem to a design simulator whichsupports behavioral models of A585/A575/A565 series instrument models,DIB and DUT. See figures 38, 39 and40. This combination creates theability to actually debug the interac-tions of the test program, test instru-mentation, DIB and DUT.

The benefits of this approach include:

• Test development independent offirst silicon

• Test development independent ofavailable test system time

• Reduced load on production ATE

• Additional IC design verification viatest involvement

Figure 38Test development – today vs. tomorrow

TEST DEVELOPMENT

TIME SHIFT

TIME SAVINGS

TIME

DESIGN

TEST DEVELOPMENT


Figure 39IMAGE ExChange

EXCHANGE EVENTSIMAGE

EXCHANGE

IMAGETESTER

SIMULATOR

DESIGNSIMULATOR

TESTPROGRAM

IMAGETOOLS

A5 TESTSYSTEMMODELS

DATASCOPE

DUT MODEL

DIB MODEL

Figure 40DataScope


The Insight Analysis product line canhelp meet engineering and operationschallenges at each stage of the devel-opment and production cycle, fromfirst silicon to daily production.

Design InsightDesign Insight is used to characterizedevice performance over an unlimitednumber of operating conditions andequipment variations. When a deviceis tested over a set of different tem-peratures, voltages, or other param-eters, Design Insight provides thetools for completely characterizing theeffect of each setting, in isolation or in

combination with other conditions.With this information, design engi-neers can modify simulation modelsand improve their design methodolo-gies. The reports can help productengineers understand the performanceof first silicon so they can set manufac-turing guard bands.

Design Insight offers high-level“roadmap” reports, which can showhow every test responds to changes ineach of the variable testing conditions.Once these reports have quicklyisolated any problems, the many low-level graphs provide detailed charac-

Figure 41Design Insight – This N Trend Plot shows the effectof changes in voltage (VCC) and temperature (thetwo trend lines) on the test results for each device.One use of this report is to help isolate whichoperating conditions have a significant effect on adevice's behavior.

mA

INSIGHT ANALYSIS SOFTWAREAND OTHER TOOLSTo analyze test data, Teradyne offersthe Insight Analysis product line. EachInsight Analysis product deliversinnovative graphical solutions tospecific engineering and operationsproblems. The Insight graphs showthousands of pieces of information in asingle view, helping engineers to:

• Identify problems which may haveotherwise been missed

• Save weeks of engineering time byreducing thousands of separateanalyses to a single graph


terization of the device. For a samplereport, see figure 41.

Test InsightTest Insight helps engineers developtest programs that maximize yield andminimize test times. In the develop-ment of a test program, Test Insightcan identify critical parameters thatmay lower yield and can help verifythat the test program is testing the

distribution approaches or crosses thehigh or low test limit. Another usefulreport shows for each test, significantlot-to-lot variations in mean andstandard deviation, thereby uncover-ing repeatability problems betweenprocesses. Test Insight also offersdetailed analysis of single tests, such asdevice trend plots and histograms, todrill down on problems discovered bythe high-level reports. For a samplewafer map, see figure 42.

Figure 42Test Insight – The Mean and Sigma Shift reportcompares two lots and shows which tests displaythe greatest shift in the standard deviation and themean. This information is valuable for determiningmeasurement differences after a change inoperating conditions or between process splits.

device correctly. It can predict yieldsbefore the release to manufacturing, toassist in operations planning. For amature product, Test Insight canreveal ways to optimize test times inorder to maximize test system capacity.

Some Test Insight reports visuallysummarize information about all thetests in the test program, indicatingtests whose low Cp or Cpk predicts alow yield, or highlighting tests whose


actual die locations on the wafer.That is the power of wafer maps.

Wafer Insight offers a complete suiteof wafer maps. Traditionally, wafermaps have consisted of ASCII repre-sentations of bin sorts. Wafer Insightgoes beyond such bin maps to includemaps based on pass/fail results andmeasured parametric results for a

Figure 43Wafer Insight – The Analog Parametric Map showseach die as a box whose size is proportional to theparametric value of its test result. On this map,higher values are found on the right edge of thewafer, suggesting that there is non-uniformity in thewafer processing.

Wafer InsightWafer Insight organizes wafermanufacturing data into graphicreports that make wafer processingproblems immediately visible.Other reporting packages, such asTest Insight, can offer valuableviews of wafer data. However, tofind problems that are specific towafer processing, it is necessary totie parametric test results back to

single test. Its ASCII maps arecomplemented by several full-colorgraphic maps of bins and parametricresults. In addition to its maps of singlewafers, cumulative maps of a stack ofwafers can locate distribution prob-lems, mask defects, and other prob-lems that are common to the same dielocation across many wafers. For asample plot, see figure 43.


Figure 44Production Insight – This Test Mean Trend Plottracks the mean of four tests over several lots ofdata. Such a report can help identify processproblems that may arise over an extended periodof time.

Production InsightProduction Insight is most usefulwhen a device is in production andoperations management wants to lookat yields and test results over a longtime interval. Production Insightsummarizes the vast amounts ofproduction data into trend plots, paretoplots, control charts, and other reports.These high-level views let theengineer stand back and look for

trends in a sizable population, insteadof being distracted by aberrations thatmay appear only in a single lot.

The Production Insight control chartscan alert the production floor managerwhen a process is out of control. OtherProduction Insight reports can thenhelp analyze the out-of-controlprocess. Trend charts can indicatewhether yields are rising or falling. Bin

paretos can show what kinds of failuresare occurring over several lots. A yieldpareto by site or tester can be used tocorrelate results from different parts ofthe test floor. These reports can beused to identify and correct anyprocess problems that arise duringproduction. For a sample plot, seefigure 44.

Test Name Test Number Key


Manufacturing Data PipelineUnderlying the Insight Analysis toolsis the Manufacturing Data Pipeline, acomplete data architecture for auto-matically and reliably collecting datafrom the test floor, and for managingfast, easy access to the collected data.In addition to supplying data to theInsight product line, the Data Pipelinecan also be used in the developmentof in-house analysis tools to providethe low-level data collection andmanagement functions.

The Manufacturing Data Pipeline isdesigned to handle large volumes ofdata, and can take as input any datafile written in Standard Test DataFormat (STDF). Teradyne testsystems can directly write STDF files,and data from other test systems is

To make this log useful for utilizationanalysis, ATE Logger includes a toolthat generates reports of the testsystem activity data. Several graphicalreports show throughput, operatorusage, test program runs, failure andrepair times, and the duration of anytest system activities. A comprehen-sive utilization summary report is alsoavailable for periodic overviews. For asample plot, see figure 45.

In addition, ATE Logger also providesfor the automatic transfer of test resultdata files from the test system to theManufacturing Data Pipeline systemwhere data is stored and analysis isperformed. This connectivity betweenthe test system and the analysissystem is one of the most importantfeatures of ATE Logger.

readily convertible into STDF forinsertion into the Data Pipeline andeventual use by analysis tools.

Automatic Time & Event LoggerIn addition to the Insight Analysistools, Teradyne offers the AutomaticTime & Event Logger, also calledATE Logger. ATE Logger runsdirectly on the test system, with thegoal of making sure that the equip-ment is used to capacity. ATE Loggerautomatically time-stamps and recordssignificant equipment events such asinitialization, setup, start and end oflot, and maintenance procedures. Italso provides for manually reportingequipment failures and repairs andother equipment states. In this way, alog is maintained of all test systemactivity, both regular and unscheduled.

Figure 45ATE Logger – The Activity Times Report is atimeline that displays the changing state of eachselected test system activity. Such a reportshows where time is being spent on a testsystem, information that can help in maximizingresource utilization.


Analog VLSI DigitalTest Capabilities

As manufacturers integrate digitaldesigns into system silicon, testingdemands increase. In order to meetboth signal as well as pattern require-ments in these mixed-signal devices,the A585/A575/A565 series containsanalog VLSI capabilities as shown intable 2 below. The following pagesdescribe the A585/A575/A565 analogVLSI capabilities.

DIGITAL CHANNELCONFIGURATIONArchitected to support 512 pins, theA585 accommodates up to 192 AVLSIdigital pins. (Please refer to the SystemConfiguration section of this docu-ment for a summary of the differencesamong the A585, A575 and A565systems.) The digital channel consistsof two primary boards: the DigitalMainframe board (DMF) and thedigital channel card. Both boards areE/MOS designed and both supporteight channels. The E/MOS architec-ture provides a high level of systemperformance and reliability with

maximum function integration.The ECL components provide speedand accuracy while CMOS technologysupports high density logic functionsand maintains low power consump-tion. Because of this technology blend,the A585/A575/A565 systems consumeless power and floor space than anyother mixed-signal test systems whilemaintaining high performance levels.The A585/A575/A565 systems’modular configuration allows easy andcost-effective field upgrades becausebackplanes and power supplies can beadded as pin count increases.

The mainframe supports two testheads. When adding a second head,either at the time of purchase or afterinstallation, channel cards for the newtest head are the only necessary add-ons. The test heads are multiplexed,which allows one station to test whilethe other station indexes the nextdevice. Or, as some customers prefer,one test head can be configured forprobe operation and the second for

A585 A575 A565

Tester per-pin architecture Yes Yes Yes

Pins 192 128 64

Data Rate (MHz) 50/100/200 50/100/200 25/50

Edge Placement Accuracy ±350 ps ±350 ps ±1 ns±500 ps ±500 ps

Pattern Depth (max.) 1 Meg 1 Meg 1 Meg

Timing Sets 1,023 1,023 1,023

Table 2Tester per-pin architecture


engineering or handler operation.Each test head, in conjunction withIMAGE software, fully supportsmulti-site, parallel test. Running withtwo test heads is a flexible and cost-effective test floor strategy.

MULTIPLE MEMORYARCHITECTURE:PATTERN MEMORYAs shown in figure 46, the DigitalMainframe board integrates anumber of Vector Bus features andcontains the pattern memory forlogic testing, plus the formatter andtiming generator for edge genera-tion. The pattern memory consistsof two portions: a 1 Meg x 3 bit/pinSequential Access Memory (SAM)and a 16K x 4 bit/pin ProgrammableRandom Access Memory (PRAM).

The IMAGE software automaticallysplits a pattern between the SAMand PRAM. This split allows easyprocessing of design simulatorpatterns into A585/A575/A565patterns, providing maximumflexibility at minimum cost. Thesplit is invisible to the user who seesonly 1 Meg pattern memory depth.

The PRAM supports mixed-signalmicrocodes per instrument pervector, plus vectors that containpattern microcodes such as startloop, go to, and execute subroutines.In addition, the PRAM supports upto 32K repeat counts, 5 levels ofnested loops, and 8 levels of nestedsubroutines as well as conditionaljumps and match mode loops.

In some mixed-signal applications,additional timing and level parametersmay need to be modified; and somepatterns may require run-time modifi-cation due to device uncertainties.The SETS memory can easily reloadthese values or the test computer canmake the appropriate changes.

In traditional test systems, thepattern is interrupted during thesemodifications. However, the A585/A575/A565 has a 16 vector keep-alive memory that generates apattern on all the digital pins duringsetup conditions or pattern memorymodification. The keep-alivememory is essentially a secondpattern memory that can be enteredfrom the main pattern memory andthen, when specifically directed by

SEQUENCE CONTROLMODULE

VECTORBUS

MEMORY



AND CONTROL

PATTERN MEMORY• 1 MEG x 3 BITS/PIN SEQUENTIAL ACCESS MEMORY• 16K x 4 BITS/PIN PROGRAMMABLE RANDOM ACCESS MEMORY

DIGITAL SIGNAL I/O MEMORY• UP TO FOUR 64K x 20 BITS DIGITAL SIGNAL SOURCE MEMORIES• UP TO FOUR 1 MEG x 20 BITS DIGITAL SIGNAL CAPTURE MEMORIES

VECTOR BUS MEMORY• 4 MEG x 32 FOR PATTERN MEMORY SCAN

DIGITALCHANNEL

CARD


DIGITALFORMAT AND

TIMING

Figure 46The A585 Vector Bus provides multiple memorytypes behind each digital pin.


the computer, exited to the mainpattern memory for continuedtesting. Using the keep-alivememory helps maintain devicephase coherency and retains devicestate when reloading main patternmemory or timing information. Thekeep-alive memory operates at ratesup to 50 MHz.

The PRAM provides four bits per pinper vector and the SAM providesthree bits per pin per vector, whichallows eight pin states to be encodedinto the pattern memory. See figure47. The pattern directly and individu-ally controls those aspects of a pin thatchange most frequently such as data,direction, compare format, andrelevance. This means that pin control

resources will be plentiful when post-processing digital device patterns. Thenormal encoding for the three bit/pinvector is:

• H - Compare to logic high

• L - Compare to logic low

• M - Compare to midband

• V - Compare to valid logic levels

• X - Compare mask

• 1 - Drive logic high

• 0 - Drive logic low

• – - Run time repeat of the previousvector data

The compare to valid pin state iscrucial for mixed-signal testing. Analogsignals are fed into an A/D converterwhich generates a series of codes

representing the analog waveform.The specific bits are unknown andcannot be truth table compared whiletesting. However, using compare tovalid, the A585/A575/A565 verifiescorrect logic levels and stores the bitsfor later DSP analysis.

The repeat state simplifies program-ming. Pin state data that repeats onsuccessive vectors does not need to bereentered. The run-time repeat pinstate is also used in subroutine calls forpassing pin states to the routine.

Additional pin state codes include W(waveform), which uses the alternatedigital memory, not the digital patternmemory, to source data to theformatter. This function is controlled

DRIVE 0

101

0

DRIVE 1 1

COMPARE 0 L

COMPARE 1 H

COMPARE MID M

COMPARE VALID V

REPEAT -

DON’T CARE X

H L L L L L L L 1 O O OO - M M M M M M M M V V1 1 1

192 PINS

Figure 47Easy to use mnemonics define the data behindeach digital pin.


by the fourth bit in the PRAMarchitecture. Pin state code I also usesdata from alternate memory, butinverts it. Codes R and C take data outof alternate memory and use it forcompare. R compares to the data andC compares to inverted data.

Pin states can be reprogrammed toprovide other encodings such as dualdrive and single cycle I/O, whichprovide an additional level of flexibil-

ity and head room when testingcomplex mixed-signal devices. Dualdrive generates two data values per 50MHz cycle. The software and hard-ware recode the bits per pin to repre-sent four combinations of data: 00, 01,10, and 11.

Single cycle I/O can drive and com-pare data within a 50 MHz cyclewithout multiplexing pins. Theencoding of the 3 bits located in the

ALTERNATE DATA BUS

DIGITAL FORMAT AND

TIMING

DIGITAL PATTERN MEMORY DIGITAL

CHANNEL CARD

TEST HEADDIGITAL SIGNALWAVEFORM MEMORY

AND CONTROL

PCM DATA DIGITAL PATTERN

pattern data is modified to drive andcompare in combinations such as:

• 1 L - for drive one, compare low

• 0H - for drive zero, compare high

• X1 - for mask compare, drive on one

• And other combinations

When pin states are recoded, the 1Meg data memory is effectivelydoubled in both the dual drive andsingle cycle I/O operating modes.

Figure 48Digital Signal I/O sends and receives thedigital representation of analog signalswithin pattern bursts.


DIGITAL SIGNAL I/O MEMORYOne of the key features of the A585/A575/A565 Advanced Mixed-SignalTest Systems is the ability to providemultisource data mixing that generatesand captures digital signals represent-ing analog waveforms.

MultiSource data mixing differentiatesthe A585/A575/A565 digital capabilityfrom VLSI capability and redefinesthe digital capability as Analog VLSI(AVLSI). See figure 49. Digital signalI/O has three specific functions: asource memory (Smem), a capturememory (dig_cap), and a digital signalcontroller.

The Smem stores the digital signalrepresentation used when testing aD/A converter. The Smem provides64K by 20 bits of parallel or serial datastorage. The data is usually stored inparallel form to make as efficient use

of the memory as possible. Data canbe extracted from either the Smem orthe standard data pattern memorywith an on-the-fly per pin switchoperating at 50 MHz. The waveform(W) pin state code, provides thecontrol for selecting the data memory.Components such as ISDN devicesrequire the ability to mix digital signaldata representing voice informationwith pattern data representing framinginformation and computer data on thesame pin in real time. The dig_srccontains its own controller that cangenerate complex waveforms with aseries of waveform segments. Seefigure 49. The controller can RE-PEAT waveform samples and LOOPon waveform segments and subroutinewaveform segments.

The dig_cap captures digital signalsgenerated by components such as A/Dconverters, which generate codes that

are not predictable (due to anomaliessuch as device noise, linearity errors,gain and offset differences), and thenpasses the captured data to the arrayprocessor where the necessary acmeasurement parameters are deter-mined. The dig_cap can capture actualdata by using the compare to valid (V)pin state. The comparator simplychecks to verify that the deviceachieves valid logic levels and deter-mines the logic level value stored inthe dig_cap. Dig_cap can also capturefailed data. This learn mode operationcan be used for debugging or fordetermining the quality of devices thatrequire counting of specific failures orlocating specific failures in long patternsequences. Communications devicessuch as FAX modems and ISDNdevices require this type of testing.

The digital signal controller canchange the data from parallel to serial

Figure 49The Smem controller can control up to 512 differentwaveform segments that can be linked, looped, andnested to generate complex waveforms with aminimum use of memory.

DIG_SRC CONTROLLER0

512

CALL 1020 HZ PCMCALL 60 HZ PCMCALL MULTI PCM

SYSTEM DATA MEMORY SEGMENTS

MULTI PCM

60 HZ PCM

1020 HZ PCM

0

64 K


for serial sourcing, or from serial toparallel for serial capture. It can alsoshift data, handling most significant bit(msb) versus least significant bit (lsb)first formats in real-time. Specificcontrol of bit movement uses mixed-signal microcode such as the SEND,TRIG, SHIFT, STORE, and STARTcommands. These commands effi-ciently compact the data in memoryand can skip vectors within thepattern. They can also send a data bit

or data word, depending on whetherthe operation is serial or parallel.

The digital signal I/O can send serialdata at rates of 100 Mbits/second; 20bit wide words at up to 25 Msamples/second; ten bit words up to 50Msamples/second; or five bit words upto 100 Msamples/second. It cancapture data at up to 50 Mbits/secondor 25 Msamples/second for 20 bits; and50 Msamples/second for ten bits.

With the 32 bit wide Alternate DataBus, digital signal functions can beassigned to any digital pin in thesystem for either serial or parallelmode operation. See figure 50. Thisalternate bus also can source commondata from one source to multipledevice pins, allowing parallel testingon multiple devices without addingextra memories to the system. Eachdigital signal system I/O can beconnected to the digital pins.

DIGITAL SIGNALSOURCE

BUS

2019181716151413121110090807060504030201

64636261605958

22212019181716151413121110090807060504030201

DEVICE PIN

NUMBERS

ALTERNATE DATA BUS

Figure 50The Digital Signal I/O is programmable to anydevice pin.


A total of four digital signal I/Os can beconfigured into the A585 system.Figure 51 shows that each card cagecan contain two digital signal I/Os.Either digital signal I/O card cage canbe assigned to a block of 64 channelsunder program control.

The dig_src also can provide comparedata to the error and format logic in thecomparator channel, especially usefulwhen testing on-board ROM in adevice where a serial pin may accessthe data. If the ROM is 8 K deep andcontains 16 bit words, the data patternmemory requires 128 K vectors to testthe data. However, only 8 K of dig_srcmemory is required if the ROM data isstored in parallel in the dig_src and

serially shifted via the digital signalcontroller to the comparator. Since theROM data is stored in the dig_srcexactly as it is stored in the device,only one vector of normal patternmemory is required for testing embed-ded memories.

VECTOR BUS MEMORY FORSCANAnother type of memory, which isaccessible to every digital pin in thesystem, is the Vector Bus Memory forSCAN (VBMS). The VBMS memoryis 4 Meg by 32 bits deep, which cansupport SCAN operations 4 Megvectors deep and eight SCAN chainswide. The memory is configurable fordifferent depths versus chain width.

The VBMS can also be used to reloadPRAM memory. The SCAN opera-tion can run up to 50 MHz rate.

DIGITAL SEQUENCE CONTROLMODULEThe 50 MHz Sequence ControlModule (SCM) controls patternbranching and on-the-fly data memoryselection. See table 3. The sequencecontroller executes multiple patternmicrocode commands and delivers themixed-signal microcodes to the analoginstruments with up to 16 K memorydepth. The A585/A575 can also beconfigured with dual sequencers,allowing the tester to run both syn-chronous and asynchronous test underMultiSync TimeGen control.

Figure 51Multiple Digital Signal I/Os are available to eachdigital pin using the Alternate Data Bus.

DIGITAL SIGNAL WAVEFORMMEMORY AND CONTROL

CARD CAGE #1

DIGITAL CARD CAGE #1

CHANNELS1 TO 64


CHANNELS65 TO 128


CHANNELS129 TO 192

DIG_SIG SRC. # 1 64K x 20

DIGITAL SIGNAL CONTROLLER # 1

DIG_SIG CAP. # 1 1M x 20










32

3232

32

32

DIGITAL SIGNAL WAVEFORMMEMORY AND CONTROL

CARD CAGE #2


PATTERN MICROCODE FUNCTIONAL DESCRIPTION

- REPEAT <n> Repeats the current vector n times where n is between2 and 32K.

Subroutines

- CALL <label> Calls a subroutine at the specified label name. Up toeight subroutines can be nested.

- RETURN Returns from a subroutine.

- END_ARG Begins the execution of vector arguments that followimmediately after the CALL and is used again to markthe end of the vector arguments.

Pattern Maintenance

- HALT Stops pattern execution.

- NO_HALT Prevents the pattern from stopping if a failure occurs.

- ICYC Inhibits the SCM cycle counter for that vector.

- MASK Inhibits failures for the vector specified.

Looping

- SET_LOOP <n> END_LOOP Sets the loop counter between 1 and 64K. Up to fivenested loops are allowed.

- SET_LOOPi <n> END_LOOPi There are 3 loop counters, 0, 1, and 2. Only loop counter0 has a stack depth of three.

- POP_LOOP Pops the top of the stack unconditionally.

- EXIT_LOOP Pops the stack and continues execution at the label.Used for premature exit of a loop.

- JUMP <label> Unconditionally jumps to another vector at the labelspecified.

- IF (flag) <command> Conditionally executes a command or multiplecommands.

- ENABLE <logic> <flagl,...> Flags can be logically combined with AND, OR, NOT.

Clearing Flags

- CLR_COND Clears flags that are tested in the IF condition.

- CLR_FAIL Clears all fail flags.

- CLR_FLAG Clears conditions that have been enabled.

Global Register Addressing

- SET_GLO Sets the register to the label given.

- EXE_GLO Jumps to subroutine label after execution of the currentvector.

- JUMP_GLO Jumps to the label in the global address register.

- READCODE <n> Read codes can be set by the SCM and read by the testcomputer. Used to help identify where the pattern iscurrently executing. The n can be an integer between 0and 2,047.

- MATCH Used to define a loop that is looking for a specificsequence of data from the DUT. Allows the tester tosynchronize to the device.

- KEEP_ALIVE Jumps the pattern execution to the keep alive patternmemory for execution there.

Table 3Pattern microcodes available in the digitalsequence control module


Sequence Control Module functionsinclude pattern looping, repeat, jump,match loop, subroutine, and keep-alive control. The sequencer can alsoexecute conditional instructions. Forinstance, if a condition is true, theinstruction is executed; if false, thenext vector in the sequence is ex-ecuted. Combinations of conditionscan also be considered with NOT,AND, and OR functions. Conditionsinclude:

• FAIL - Execute command on failcondition

• CPU - Execute command on CPUcondition

• VBC - Execute command on VectorBus condition

• EXT - Execute command on anexternal condition that has beenconfigured by the user to capturefailures or DUT logic levels

The SCM also contains a 1 Megmemory for timing set informationso that each test vector can call oneof 1,023 different timing sets andrepeat counts.

TIMING AND FORMAT

Digital Clock and Data RatesThe A585/A575 are described as 50/100/200 MHz test systems becausethey can generate 200 Mbit/sec data.

In normal mode, both the sequencecontroller and the base rate of thetester are programmable to 50 MHzspeeds. Some of the methods thatallow the tester to go beyond 50 MHzare illustrated in figure 52.

One technique uses a 50 MHzsingle cycle I/O mode. This meansthat both drive and compare datacan be generated within a 50 MHzor 20 ns vector. The data for each ofthese states within the cycle isindependently programmable.Effectively, this is a 100 MHz datarate mode since two data values canbe run within a 50 MHz cycle. Driveand compare positioning within thecycle is interchangeable. In other

Figure 52Six edges/pin can generate data in each 20 nsvector cycle.

NORMAL MODE50 MHZ

SINGLE CYCLE I/O MODE50 MHZ

A500 HI_z MODE50 MHZ

DUAL DRIVE WITHMUX MODE 200 MHZ

DUAL DRIVE MODE100 MhZ

SINGLE CHANNEL

D0 D1 D2 D3

D0 D1 D2 D3 R1 R2

D0 D1 D2 D3 R1 R2

D1ODD R1ODD D1EVEN R1EVEN

D1 D2 D3 D0

R1 R2

R1 R2

SINGLE CHANNEL

SINGLE CHANNEL

CHANNEL PAIR

SINGLE CHANNELDT1 DT1 DT2DT1 DT2 DT2


words, either the drive or comparedata can be first in the cycle. Thisorder can also change on-the-fly,under control of the pattern, as longas timing conditions are not violated.

Another way to go beyond 50 MHz isto use a dual drive mode. In this mode,the drive and compare edges can drivetwo independently programmed datavalues to the device within a 50 MHzcycle. This means that 100 MHz datacan be generated and formatted withinthe timing capabilities of the systemwithout a trade-off in pin count ormemory depth.

A third technique that surpasses 50MHz uses the multiplex (MUX)mode. In MUX mode, two digitalchannels are combined at theformatter, not at the digital channelcard or on the Device InterfaceBoard. This technique generates upto 100 MHz of fully formatted I/Odata. In this mode, the combinedpattern data memory from the twochannels provides up to two mega-vectors of depth. The channels areindividually programmed for MUXmode operation, which, for example,allows one pin to operate at 100MHz and the rest of the 190 systempins to operate at 50 MHz or less.The only MUX mode trade-off isreduced pin count. All formats, data,and memory depth are available.

A fourth method combines the dualdrive and MUX modes. With thistechnique, 200 Mbit/second drive datarates are achievable. By programmingthe desired pin and its MUX’d pin in

dual drive mode, the drive andcompare edges from each pin combineto generate the 200 Mbit/second datastream. At 200 Mbit/second, the datauses non-return to zero (NRZ)formatting.

Two additional modes control thedriver transitions to Hi-Z mode. Aspecial mode called A500_hi_z,simulates the A500/A520/A540/A550digital operation. There is also a Hi-Z mode that supports a return to Hi-Z format. In this mode, the patterndrives to the data value and returnsto a Hi-Z state, which is sometimesrequired when testing bus interfacedevice pins.

The A565 digital capability is a 25/50 MHz test system with a maxi-mum base rate programmable to25 MHz. It is capable of normalmode at 25 MHz, single cycle I/Omode at 25 MHz, and dual drivemode at 50 MHz.

Edge AgilityThe A585/A575/A565 timing genera-tors are available on a per pin basis.Each pin in the system can generatesix independent edges, including:

• D1 and D2 - Drive edges

• D0 and D3 - Driver enable edges

• R1 and R2 - Receive window edges

The D1 and D2 edges generate thedrive waveform shown in figure 52.The D1 edge designates the begin-ning of the edge, and the D2 edgedefines the return edge. If the data isNRZ formatted, then only the D1

edge is used. If the format is return tozero (RZ), then the D2 edge returnsthe waveform to zero.

The D0 and the D3 edges enableand disable the driver respectively.The D0 edge designates when thedriver comes out of a Hi-Z state andbecomes active. The D3 edgedesignates when the driver goes intoa Hi-Z state. These edges can beactive within the drive cycle fornormal A585/A575/A565 operation,or within a compare cycle to emu-late the A500_ hi_z mode operation.

When generating a complementsurround format on an I/O pin, D0edge tells the driver when to comple-ment the data before the data value.D1 tells the driver when to drive to thedesignated value. D2 determineswhen to return to complement, andD3 determines when to go to Hi-Z fora compare cycle. This combination ofedges and complement surroundverifies device operation under propersetup and hold timing parameters forboth data and address pins.

The R1 and R2 edges strobe thecomparator to determine if the datacorrectly compares with the datacontained in pattern memory. (Theedges can also strobe data into thedigital signal capture memory.) Thecombination of R1 and R2 edgesgenerate an active window strobebetween the two edges. If a thresholdis violated at anytime during thewindow, a failure is recorded. Thisallows the window strobe to capturedevice glitches.


All edges have ±350 ps of placementaccuracy. This means that the maxi-mum error between any two drivechannels or any two comparatorchannels is ±350 ps. The error be-tween any driver and any comparatoris ±500 ps, which represents theoverall accuracy of the system. Thisaccuracy is specified at the device pin,so it includes the signal path on theDIB. Time Domain Reflectometry(TDR) calibrates all digital signalpaths in the test head and DIB. Alledges on the A565 have ±1 ns edgeplacement accuracy. (Refer to theSystem Configuration Section of thedocument for a summary of thedifferences among the A585/A575/A565 systems.)

Edge resolution is 1/64 of aTimeMaster clock cycle, or between78 and 100 ps for programmableTimeMaster clock frequencies from160-200 MHz. Deskew adjustmentprovides greater resolution, which isneeded for edge search functions andfor finer placement. Deskew adjusthas a resolution 1/256 of theTimeMaster clock period, equivalentto 19 ps at 200 MHz.

Timing Sets and Edge SetsThe A585/A575/A565 systems have1,023 timing sets, that allow on-the-flytime changes, a feature required byVLSI and mixed-signal devices. Thetest system uses a palette scheme for

time set addressing. Each channel isbacked by 32 edge sets. Each edge setcontains six values, one for each edgeper pin. The palette scheme increasesthe flexibility of these time setmemory edge sets.

There are 1,023 locations of time setmemory. Each location contains oneunique edge set address for each of thetest system’s digital pins. See figure 53.

The A585/A575/A565 systems alsoprovide edge masking. One edge setcan be defined as a mask. Edgemasking prevents the timing generatorfrom creating an edge and also affectsthe data format within the cycle. The

Figure 53Time sets provide an indirect addressing capabilityto the edge set offering maximum flexibility.PIN 1 EDGE SET MEMORY 32 DEEP

5

10TIME SET MEMORY

OP CODES TSET ADDRESS CHANNEL DATA

PATTERN MEMORY

PIN 1EDGE-SETADDRESSEDGE-SETADDRESSEDGE-SETADDRESS



1

2…

1023

D0 D1 D2 D3 R1 R2 1

D0 D1 D2 D3 R1 R2 2

D0 D1 D2 D3 R1 R2 3

D0 D1 D2 D3 R1 R2 4

D0 D1 D2 D3 R1 R2 5…

D0 D1 D2 D3 R1 R2 32

5

PIN 2 EDGE SET MEMORY 32 DEEP






PIN 9…EDGE-SETADDRESSEDGE-SETADDRESSEDGE-SETADDRESS


D0 D1 D2 D3 R1 R2 1

D0 D1 D2 D3 R1 R2 2

D0 D1 D2 D3 R1 R2 3

D0 D1 D2 D3 R1 R2 4

D0 D1 D2 D3 R1 R2 5…

D0 D1 D2 D3 R1 R2 32


receive window strobe is an exampleof edge masking. If the device has apin that changes state and is expectedto remain in that state for a largenumber of cycles, then the R1 edgecan be used to open a comparewindow; the R2 edge can be maskedso that the window will remain openfor as many cycles as desired. In thisinstance, masking helps guarantee that

when a device pin such as a status flagis enabled, it will remain enabledthroughout the required set of vectorsand will not glitch between states. Seefigure 54. The edge mask functionrequires only two edge sets, one todefine the R1 and R2 edges, and oneto mask the R2 edge.

Timing sets can change vector cycletime on-the-fly to verify on-boarddevice memory where read/write cycletimes may be different. The timingsets can also be used to change thedivider value that generates the T0and C0 clock rates at 50 MHz or 25MHz on the A565.

Figure 54With edge masking, a compare window can beopened over multiple vector cycles.

CURRENT CYCLE NEXT CYCLE NEXT CYCLE NEXT CYCLE

START AND STOP EDGE REGION

T0 T0R1 R2

T0 T0 T0


Drive and Compare FormatsThe A585/A575/A565 test systemsprovide 29 drive and compare formatsthat simplify the generation of differ-ent digital waveforms. See figure 55.Drive formats include:

• NRZ - Non return to zero and itscomplement

• RZ - Return to zero and its comple-ment

• RO - Return to one and its comple-ment

• CS - Complement surround and itscomplement

• CLKHI - Clock high in each vector

• CLKLO - Clock low in each vector

• OFF - Driver tristate

• FHI - Force driver to a static high

• FLO - Force driver to a static low

• DRVCLKHI - Clock high in drivecycles only

• DRVCLKLO - Clock low in drivecycles only

• DRVHI - Force a high in drivecycles only

• DRVLO - Force a low in drivecycles only

Compare formats include:

• CMPPAT - Compare to pattern data

• CMPHI - Compare to high in eachvector

• CMPLO - Compare to low in eachvector

• CMPMID - Compare to midband ineach vector

• CMPLOG - Compare to logic ineach vector

• CMPMASK - Mask compare resultsin each vector

• CMPOFF - Disable compare edges

• RCVHI - Compare high in receivecycles only

• RCVLO - Compare low in receivecycles only

• RCVMID - Compare midband inreceive cycles only

• RCVLOG - Compare logic inreceive cycles only

• RCVMASK - Mask compare resultsin receive cycles only

The static formats help simplify theprocess of debugging test programs.

Figure 55There are 29 drive and compare formats availableon the A585 Advanced Mixed-Signal Test System.

D0 D1 D2 D3 D0 D1 D2 D3 D2 D3D0 D1 D0 D1 D2 D3

R2R1D3D2D1D0R2R1D3D2D1D0

D1 D2 D1 D2 D1 D2 D1 D2 D1 D2

T01 0 1 1 X

T0 T0 T0 T0

R2R1D3D2D1D2D1D2D1D2D1

CHANNEL DATA

COMPLEMENT SURROUND (CS)

RETURN TO ZERO (RZ) DUAL-DRIVECHANNEL MODE

CLOCK HIGH (CLKHI)

DRIVE CLOCK HIGH (DCLKHI)


HISTORY RAM FOR FAILUREANALYSIS

For full debugging capability, thedigital channels have a 4K deephistory RAM that records failureinformation on each pin. The historyRAM can operate in numerous modesand can capture both drive and receivedata on all pins for all cycles. Using apattern microcode to define the cycles,it can capture qualified cycles, whichare predetermined by the user. It canalso capture only failures. Thisfunction is 63 failures deep. Thehistory RAM can begin capture on theNth predetermined cycle. Thecaptured data can be defined on a perpin basis as either pass/fail informationor as logic data. Finally, this RAM alsocaptures sequence control informationsuch as cycle count, vector number,and flag status.

In each operating mode, a number offeatures can isolate any type ofproblem in any size pattern. Some ofthe features that provide this powerfuldebugging capability include:

• Global mask of compare for N cycles

• Capture until full

• Compress repeat cycles

• Halt after N cycles

• Halt on fail

• Inhibit halt on fails

• Inhibit halt on N cycles

DIGITAL CHANNEL CARDThe Digital Mainframe board and thedigital channel card are the two keyelements of the A585/A575/A565digital channel. The digital channelcard, which interfaces the device pinto the test system, includes the driver,

a comparator, dynamic load, access tothe dc matrix, access to Time DomainReflectometer calibration, and a PerPin Parametric Measurement Unit(PPMU). As shown in figure 56,each channel is programmable on aper pin basis.

The 50 Ohm driver provides threevoltage ranges that cover -4.0 V to+7.0 V operation. The comparator hasan operating range of -4.0 V to +7.0 Vas well. The levels for V

IH, V

IL, V

OH,

and VOL

can be programmed with 1mV of resolution. The dynamic loadprovides an operating range of -4.0 Vto + 7.0 V for the commutation pointvoltage (VCP) and can providedynamic load currents up to 50 mAwith 5 µA resolution. Similarly, theA565 voltage ranges cover -2.0 V to+7.0 V operation.

Figure 56The Digital Channel Card provides access to allfunctions such as dc matrix, Time Measurement,Per Pin Measurement and TDR for calibration.

VOH

IOH

IOL

VOL

VIH

VIL

50 Ohms

3.0 ns 50 Ohms

VCPDC MATRIX

DUT

TDR

PPMU

50 Ohms

FS


The dynamic load can act as a trans-mission line termination of 50 Ohms.This mode allows the A585/A575/A565 to terminate devices with I/Opins. An I/O pin can be terminated to adifferent voltage than one of the twodriver levels. For example, a line couldbe terminated to 2.5 V to keep theload on a CMOS device outputsymmetrical. The driver levels couldthen be set to the correct V

IH and V

ILlevels of 0 V and 5 V, respectively.(The A585/A575/A565 digital channelcard also supports the traditional modeof operation, which terminates onlyoutput pins and uses the driver toforce a low voltage.)

The load seen by the DUT is bestmodeled as a transmission line. All ofthe capacitance in the pin electronicsand in the path to the device isdistributed. A TDR of the path usinga 1 ns rise time shows the lumpedcapacitance along the path is less than2 pF. The device loading model thatbest represents the tester is a 50 Ohmtransmission line that is 3 ns in length.To calculate the actual length, add theelectrical length of the wiring on theDIB to the 3 ns path length from theIso-Pins™ to the pin electronics. Theelectrical length of wiring on the DIBcan be estimated at 1.77 ns/foot or0.147 ns/inch. A typical 6 inch pc trace

yields a total path length of 3.9 ns.

Every digital channel providesaccess to the Time MeasurementSubsystem. This instrument canmake single shot time measure-ments on single channel signalssuch as duty cycle, frequency, andrise/fall time. The Time Measure-ment Subsystem can also makemeasurements between digitalchannels and between analog todigital channels for propagationdelay and skew.

Every digital channel also has accessto the dc matrix, which allows thedigital pin to use the standard V/I,the Analog Pin Unit (APU), theAdvanced Analog Pin Unit (AAPU),the High Current Unit (HCU), andany other instrument connected tothe dc matrix. The ability to access awide variety of resources on a perpin basis is built into the digitalchannel card, simplifying the designof the Device Interface Board.

For continuity, leakage, and outputvoltage parametric measurements, theA585/A575/A565 has a four-quadrantparametric measurement IC on everydigital pin. The Pin ParametricMeasurement Unit (PPMU) canperform dc parametric measurements

in parallel, while forcing voltage andmeasuring current, or while forcingcurrent and measuring voltage. ThePPMU operates over a -4 V to +7 Vrange in the A585/A575, -2.0 V to+7.0 V range for the A565, and offerscurrent ranges from 200 nA to 2 mA.The settling time for measurement onall pins can be programmed to achievethe fastest possible parametric testing.

Opens and shorts testing is accom-plished automatically using simplesoftware commands that can ex-ecute a continuity test with onlyone statement.

140 MHZ HIGH-SPEED DIGITALCHANNEL OPTIONAs an option in the A585 and A575models only, 140 MHz high speeddigital channels can be substitutedfor the standard digital channels.The high speed option allows theuse of return formats above 100MHz and up to 140 MHz withimproved pulse width specifications.Please refer to the specificationssection later in this document.

SUPERCLOCK OPTIONIn the A585 and A575 models, theSuperclock provides a high speedclock signal with an operating fre-

ALIGNMENTAND

GATINGHSD CHANNEL

–2.0 V TO +4.0 V

GAAS

VECTOR BUS10 MHZ

REFERENCE

CLOCK10 TO 400 MHZ

Figure 57The Superclock option provides a synchronized400 MHz clock source for high-speed devicetesting.


quency range of 10 to 400 MHz. Theclock voltage swings are program-mable over a 500 mV to 4.0 V range,with levels between -2.0 V to +5.0 V.The duty cycle is programmable overa 40% to 60% range. The drive onlyclock output can be used either single-ended or differentially. In a free-running mode, the clock signal isavailable asynchronously to the systemclock T0. The Superclock signal canbe gated ON/OFF by a dedicateddigital channel, which will thensynchronize the Superclock outputwith the system T0 clock. TheSuperclock option consists of amainframe synthesizer and a test headchannel card. Refer to figure 57.

SUPER SPEED SERIAL PINThe maximum serial data rate withthe standard digital channels is 200

ric measurements can be made onthe HI and LO drive and receivelines of each device pin as needed.

The SSSP can support ATM/Sonet622 MBits/second data rates bymultiplexing two SSSPs at the DIB.The SSSP can be used in conjunc-tion with the Digital Signal I/OMemory, with data loaded directlyinto the Smem, rather than encodedinto the pattern. Received data canbe captured directly to the DigitalSignal I/O dig_cap. The SSSPchannel card has direct internalconnections to the Superclock andthe Time Jitter MeasurementSystem. A maximum of 8 driver/receiver pin pairs at 400 Mbits/second data rate can be installed inthe A585.

Figure 58Super Speed Serial Pin Channel Card option

8:1ENCODER

8T0

VTERM

GaAs

–2.0 V to +5.0 V

TO HSDMAINFRAME

CHANNEL BOARD

INTERNALSUPERCLOCK

FROM HSDMAINFRAME

CHANNEL BOARD

8-BIT SERIAL TO PARALLELSHIFT REGISTER

HOLD REGISTER

PROG. DELAY

PROG. DELAY

MBits/second, when the dual drive,multiplexed mode is used, asdescribed previously. To signifi-cantly increase the data rate in theA585 and A575 models to accommo-date the demands of disk drive(PRML) and ATM devices,Teradyne has developed the SuperSpeed Serial Pin (SSSP). See figure58. The SSSP replaces a standarddigital channel card in the test head.The SSSP card provides a differen-tial drive pin and differential receivepin, operating simultaneously at amaximum serial data rate of 400Mbits/second. The drive pins have a50 Ohm backmatched termination;the receive pins are terminated to aprogrammable voltage through 50Ohms. Each wire of each differen-tial pair has Per Pin ParametricMeasurement Unit (PPMU) cir-cuitry attached to it, so full paramet-


Mixed-signal devices have multipleapplications in automotive, television,telephone, computer, cellular tele-phone, and many other end products.Each of these applications interfaces tothe analog world and each requires aunique type of analog signal tosimulate the actual operating environ-ment. These devices require mixed-signal test systems that can generateand measure signals ranging from highprecision, ultra-low distortion fortesting compact disk player devices, toultra-high radio frequency for cellularapplications.

Some of the A585/A575/A565 analoginstrumentation that meets thesediverse demands are shown in figure59, including:

• Precision low frequency sources anddigitizers, Very High Frequency(VHF) arbitrary waveform genera-tors, and continuous waveformgenerators

• High frequency real time digitizersand high speed samplers

• Microwave waveform instruments

AC Instrumentation andTest Capabilities

Figure 59A full spectrum of high performance analog instruments ranging from precision dc toRF/microwave frequencies are available on the A585/A575/A565 series of test systems.

VHFMEASURE MODULELFAC100

LOW FREQUENCYDIGITIZER

LFAC100LOW FREQUENCY

SOURCE

DC 1 MHz 100 MHz10 MHz 1 GHz 10 GHz

PRECISIONLOW FREQUENCY

DIGITIZER

HIGH FREQUENCYDIGITIZER

HIGH SPEEDSAMPLER

MICROWAVE MEASURE

VHFCW SOURCE

PRECISIONLOW FREQUENCY

SOURCE

MICROWAVE CW SOURCE

400 MHZ VHFARBITRARY WAVEFORM

GENERATOR

VHFARBITRARY WAVEFORM

GENERATOR


The Vector Bus III architectureensures complete synchronizationwith digital patterns for these highperformance analog instruments. TheVector Bus clocking architecture allowsinstruments to operate asynchronouslywith each other or relative to digitalpatterns, if desired.

ANALOG INSTRUMENTARCHITECTUREThe analog instrument architecture issimilar to the architecture of the A585/A575/A565 AVLSI digital pins. Eachinstrument consists of a source orcapture memory with a controller, aformatter referred to as the conversion

and filtering unit, and a test headchannel card that provides a controlledimpedance environment to the deviceas well as programmable control ofsignal levels between the device andtester. See figure 60. The source andcapture memories are similar to thedigital signal I/O memories. The


DIGITALFORMATTER

and PATTERN

DIGITALCHANNEL

CARD

ANALOGCHANNEL

CARD

ANALOG WAVEFORMMEMORY AND CONTROL

TEST HEAD

ANALOGCONVERSION

ANDFILTERING

VECTOR BUS III

Figure 60The architecture of the memory-based analoginstruments is very similar to the VLSI architectureof the digital pins.


source memory (Smem) stores thewaveform and waveform segmentsused for testing the device.

For testing video devices, the control-ler can create complex waveformsfrom simple segments for testingdevices like those used in videoapplications. These complicatedwaveforms are nearly impossible todescribe with a single mathematical

function. However, when brokendown into segments, they can bedescribed with simple sine waves asshown in figure 61.

The data, which can originate in a filedownloaded from the disk drive, ispre-calculated in the system computeror array processor and loaded intoSmem. Smem clocks the data samplesfrom its memory to the D/A converter

in the instrument at the rate definedby the TimeMaster Analog (A0-A3)clocks. In addition, mixed-signalmicrocodes from the digital patternmemory control the instrument,allowing it to Vector-Lock to the digitalpattern. This means a waveform doesnot have to begin with computercontrol. Instead, it can be triggered bythe digital pattern so that every timethe device program runs, the wave-

0

SMEM MEMORY CONTROL

SMEM DATAMEMORY SEGMENTS

CALL SYNCCALL BURSTCALL BLUE-REPEAT 2CALL RED-REPEAT 3

4096

0

BURST

GREEN

RED

BLUE

SYNC

256 K

Figure 61Smem controller generating a video line. Loopingon this series of subroutines generates a completevideo frame.


form starts at precisely the same clockcycle as the device. Some of theavailable microcodes are shown infigure 62, including:

• Start waveform and continue to run

• Start waveform and run once

• Start new waveform at the end ofcurrent waveform to provide phasecontinuous switching of signals

• Start new waveform at the end of thecurrent waveform and execute once

their edges for repeatable phasealignment

This level of control makesapplications repeatable every timethe program is run and providesreliable correlation from system tosystem. It also makes it easier togenerate complex waveformssynchronously with digital pat-terns as required by ISDN, diskdrive, and FAX modem devices.

• Go to the next waveform at the endof the current waveform

• Go to the next waveform andexecute it once

• Stop immediately

• Stop at the end of the currentwaveform

• Trigger to start the digitizer capturingdata

• Resync to allow the T0 digitalclock and the analog clocks to align

Figure 62A variety of mixed-signal microcode commandscontrol switching between waveforms. Theaction can be performed immediately or phasecontinuously.

START

WAVE 1

WAVE 2

START1

START

START

START

START

NEXT1

NEXT


THADS B

DIFF AMP

MATRIX CHANNEL A

COARSE AMPAND

DC BASELINE

F

S

+1

-1

SHIELD

PIN B

AC DGSPIN A

MATRIX CHANNEL BF

S

AC IN LO

AC IN HI

SHIELD

THADS A

ANALOG INSTRUMENTATION

Analog Instrument Channel CardEvery analog instrument channel cardis custom designed for each instru-ment type. Precision Low FrequencySource, Precision Low FrequencyDigitizer, Very High FrequencyArbitrary Waveform Generator, HighFrequency Digitizer, and MicrowaveContinuous Wave Source channelcards are matched to the mainframeinstrument. The channel cards used in

source instruments provide imped-ance matching to the device, signalamplitude control, plus time measure-ment system and dc matrix access.The capture instrument channel cardsprovide selectable input impedances,voltage ranging (amplification), andaccess to the time measurementsystem and dc matrix. These functionsprovide a high performance level atthe DUT and reduce the applicationshardware required on the deviceinterface board such as amplifiers,

attenuators and relay matrixes areunnecessary, as shown in figure 63.

AC instrument channel cards canalso access the Test Head AnalogDistribution System (THADS) Bus.The THADS Bus allows an acinstrument to be rerouted to otherdevice pins without using additionalrelays on the device interface board(DIB), giving true tester-per-pincapability for ac signals.

Figure 63The Precision Low Frequency Source (PLFS) analog channel card provides access totime measurement functions, to an ac distribution bus in the test head (THADS) and todc matrix functions.


Precision Low Frequency SourceThe Precision Low Frequency Source(PLFS) is a memory-based instrumentdesigned for applications requiringultra-low distortion performance in anoperating bandwidth of up to 500 kHz.See figure 64. It is used to test preci-sion converters, telecommunicationsand audio devices.

The PLFS is based on a proprietarysigma-delta 20-bit architecture. Thememory is 64 K deep by 20-bits with alocal 512 waveform segment control-ler. There is also an optional l Meg by20-bit memory with the same wave-form controller. Waveforms can be

differential or single-ended at ±11.0V

PK. A selectable output impedance of

25 Ohms or < l Ohm allows theinstrument to match a variety ofapplications and minimize errorsources. To provide optimum dynamicrange, dc offset is programmed with adc baseline generator on the channelcard added to the signal in the PLFSchannel card. The PLF Source cangenerate a l kHz sine wave at betterthan -115 dB total harmonic distortion(THD) and better than -ll0 dB of totalsignal-to-noise over a 20 kHz range.

The PLFS contains a real time digitalintegrator that can generate ramp and

triangle waveforms to better than 2ppm linearity for testing precisionconverter devices and complex systemsilicon containing A/D converters. Italso contains built-in linearity calibra-tion correction that is applied to everysample sent to the D/A converter.Fine amplitude adjustment in thedigital domain helps reduce theamount of analog signal processing inthe signal path and provides an ultra-low-noise signal to the DUT. ThePLFS can also access the UniversalBus architecture.

Figure 64The Precision Low Frequency Source providesultra-low distortion performance for testingmixed-signal devices.

64 K X 20-BIT SAMPLESOURCE MEMORY

AND512 WAVEFORM

SEGMENT CONTROLLER(1M X 20-BIT OPTIONAL)

20-BITSIGMA-DELTA

DAC ARCHITECTURE

TOTAL NOISE (20 KHZ)<-110 DB

THD <-115 DB

SIGNAL: 1 KHZ 20 KHZ

SOURCE PERFORMANCE SPECTRUM

CHANNEL CARD

BANDWIDTH 500 KHZ

11.0 VPK OUTPUT

SINGLE/DIFFERENTIALDC BASELINE GENERATOR

OUTPUT IMPEDANCE:25 OHMS/<1 OHM


Figure 65The Precision Low Frequency Digitizer includes sample memory,Vector Bus and conversion on a single board.

Precision Low Frequency DigitizerAudio, telecommunications, precisionDACs, and data communicationsdevices require very low distortionmeasurements. The Precision LowFrequency Digitizer (PLFD) with its23-bit sigma-delta architecture wasdesigned for these and other applica-tions. See figure 65. The PLFD canmake l kHz signal measurements withbetter than -110 dB of total harmonicdistortion and better than -95 dB signalto noise over a 20 kHz bandwidth.

The total bandwidth of the instrumentis 500 kHz. The capture memory is256 K samples deep.

The PLFD channel card is verysimilar to the PLFS channel card.The dc offset generation capabilityremoves dc components from thesignal before gain is applied tomaximize ac dynamic range. ThePLFD can operate single-ended ordifferentially and can handle up to±11.0 V

PK input signals.

The PLFD also provides program-mable real-time digital filters that aretime or frequency domain optimized.Depending on the type of measure-ment, it may be necessary to use atime domain based filter with lowringing characteristics to analyze anISDN waveform against a pulse shapetemplate. A frequency domain filteranalyzes frequency response with verylow ripple response in the passband.The PLFD also interfaces to theUniversal Bus architecture.

256 K X 23-BITSAMPLE CAPTURE

MEMORY

23-BITSIGMA-DELTA

ADC ARCHITECTURE

TOTAL NOISE (20 KHZ)<-95 DB

THD <-110 DB

SIGNAL: 1 KHZ 20 KHZ

MEASUREMENT PERFORMANCE SPECTRUM

CHANNEL CARD

BANDWIDTH 500 KHZ

11.0 VPK INPUT

SINGLE/DIFFERENTIALDC BASELINE REMOVAL

INPUT IMPEDANCE:10 MOHMS


LFAC100The Low Frequency AC Source andDigitizer (LFAC100) are memory-based instruments designed forapplications requiring low distortionperformance in an operating band-width of up to 100 kHz, such astelecommunications, audio andautomotive. They feature high-level,simplified programming.

LFAC100 Source(Low Frequency AC Source)The Low Frequency AC Sourcecombines the features of functiongenerator programming and arbitrarywaveform generator in one module.Functions that can be programmedinclude ramps with control of rate andend points or period and amplitude ofsawtooth; square wave with control of

duty cycle and amplitude; sine wavewith frequency, amplitude and phasecontrol; and multitone with control offrequency components and amplitude.The arbitrary waveform functionprovide controls for what data array isinput, number of samples, sample rate,maximum amplitude, and program-mable filters. The arbitrary waveformgenerator has a 16-bit resolution. The

Figure 66The Low Frequency AC Source

FUNCTION GENERATORSINE, TRIANGLE, SQUARE

RAMP, MULTITONE

AWG1 MEG MEMORY512 WAVEFORM

CONTROLLER

16-BIT RESOLUTION

FS < 1 MHZ

TOTAL NOISE (1 MHZ)<-85 DB

THD <-85 DB

SIGNAL: 1 KHZ

SOURCE PERFORMANCE SPECTRUM

CHANNEL CARD

BANDWIDTH 100 KHZ

11.0 VPK OUTPUT

SINGLE/DIFFERENTIAL

OUTPUT IMPEDANCE:25 OHMS/<1 OHM


Low Frequency AC Source provides±11.0 VPK output with ±11.0 V dcoffset, better than -85 dB performance,and a 100 kHz bandwidth. The outputof the source can be either single-ended or differential, with a selectableoutput impedance. See figure 66.

LFAC100 Digitizer(Low Frequency AC Digitizer)The Low Frequency AC Digitizerfeatures 16-bit resolution and 100 kHzbandwidth. The input to the digitizeraccepts differential inputs up to ±11.0VPK and provides ±11.0 VPK of dc

baseline removal. It has a 256 Ksample capture memory depth. Seefigure 67.

Figure 67The Low Frequency AC Digitizer

METERRMS, PEAK

DIGITIZER256 K MEMORY

16-BIT RESOLUTION

FS < 1 MHZ

TOTAL NOISE (1 MHZ)<-85 DB

THD <-85 DB

SIGNAL: 1 KHZ 5 KHZ


CHANNEL CARD

BANDWIDTH 100 KHZ

11.0 VPK INPUT

SINGLE/DIFFERENTIAL

INPUT IMPEDANCE:>10 MOHMS


Figure 68The Very High Frequency Arbitrary Waveform Generator produces signals fordisk drive testing. The VHFAWG400 provides sample rates up to 400 MHz.

Very High Frequency ArbitraryWaveform GeneratorThe Very High Frequency ArbitraryWaveform Generator (VHFAWG)shown in figure 68 contains a 256 K by12-bit source memory or, optionally, a1 M by 12-bit source memory, with acontroller that can handle 4,096waveform segments. An internalGaAs-based DAC provides 12-bitwaveform resolution at up to 200 MHzsample rates. The bandwidth forarbitrary waveform generation is 80MHz, which is necessary for testingcurrent and future disk drive,Ethernet, and video devices. Theinstrument can also operate in acontinuous waveform generation

mode up to 200 MHz by generatingsine waves that can be directly usedfor bandwidth measurements.

Inside the VHFAWG, a 4x clockmultiplier and integer dividergenerates the appropriate samplingclocks based on the TimeMasterclock input. This allows for maxi-mum flexibility on the TimeMasterClock programmability.

The channel card provides amplitudecontrol of ±2 V and the ability to addup to ±2 V of dc offset, assuming a 50Ohm load. Level compensation to theDUT provides better than ±0.25 dBamplitude accuracy. If the device load

is not equivalent to 50 Ohms, a simplecommand defines the load equivalent,and software makes the necessaryadjustments to achieve the desiredlevel at the DUT.

The instrument filters provideexcellent step response characteris-tics for obtaining the clean andprecise waveforms required forapplications with demanding timedomain characteristics such as video,Ethernet and disk drives. Forexample, the 80 MHz filter has arise time specification of <8 ns and<8% over/undershoot characteristics.

256 K X 12-BIT (1 MEG OPTIONAL)SAMPLE SOURCE

MEMORY AND4,096 WAVEFORM

SEGMENT CONTROLLER

12-BIT DAC ARCHITECTURE

FS <200 MHZ

CW MODE80 TO 200 MHZ

LORENTIAL DISK DRIVE WAVEFORM

CHANNEL CARD

2.0 VPK OUTPUT

2.0 VPK DC BASELINE

OUTPUT IMPEDANCE:50 OHMS


VHFAWG400A 400 MHz version of the VHFAWG,called the VHFAWG400 is also avail-able. The VHFAWG400 has a maxi-mum sample rate of 400 MHz and anoutput bandwidth of 160 MHz fortesting ATM and disk drive devices.

High Frequency DigitizerThe High Frequency Digitizer(HFD) illustrated in figure 69 is a 12-bit instrument that samples waveformsin real-time at up to 20 MHz samplerates. It has a l Meg sample memory

20 bits wide and can digitize signalsover a ±20 V range with ±12 V of dcbaseline removal. A l MHz signal canbe digitized with less than -60 dBharmonic distortion and less than-77 dB noise.

Numerous low pass filters for antialias-ing in the HFD include a phase linear6.l MHz filter required for testingvideo devices. A 256 kHz high passfilter allows analysis of distortioncomponents in signals less than128 kHz through a technique referred

to as filter/amplify/digitize. Thistechnique allows an additional 20 dBof dynamic range improvement. TheHFD can also interface to the Univer-sal Bus architecture.

1 MEG X 20-BITSAMPLE CAPTURE

MEMORY

12-BITADC ARCHITECTURE

FS < 20 MHZ

SYSTEM NOISE<-77 DB

2ND/3RD HD<-60 DB

SIGNAL: 1 MHZ 5 MHZ


CHANNEL CARD

BANDWIDTH 10 MHZ

20.0 VPK INPUT

12.288 V DCBASELINE REMOVAL

INPUT IMPEDANCE:50 OHMS/10 KOHMS

Figure 69The High Frequency Digitizer analyzes performanceof devices such as video, disk drive, and ISDNcomponents.


The channel card provides amplitudecontrol of ±2 V and the ability to addup to ±2 V of dc offset, assuming a 50Ohm load. Level compensation to theDUT provides better than ±0.25 dBamplitude accuracy. If the device loadis not equivalent to 50 Ohms, a simplecommand defines the load equivalent,and software makes the adjustmentsnecessary to achieve the desired levelat the DUT.

Very High Frequency ContinuousWaveform SourceFor linearity tests on high frequencydevices such as flash converters, it isnecessary to generate very linear, lowharmonic distortion sinewaves. Seefigure 70. The Very High FrequencyContinuous Waveform Source(VHFCW) generates signals from lMHz to 250 MHz with l Hz resolu-tion. These signals are generated withless than -70 dBc harmonic distortion.

The VHFCW Source has a program-mable frequency synthesizer withexcellent frequency accuracy andresolution that derives its reference forsynthesizing waveforms directly fromthe Vector Bus III so it is alwayssynchronized to the entire test system.

1 MHZ - 250 MHZCONTINUOUS WAVE

SOURCE

1 HZ RESOLUTION

2ND/3RD HD(1-185 MHZ SIGNAL FREQ.)

<-70 DBC

SOURCE PERFORMANCE SPECTRUM185 MHZ

CHANNEL CARD

CW BANDWIDTH 250 MHZ

2.0 VPK OUTPUT(50 OHM LOAD)

2.0 VPK DC BASELINE

OUTPUT IMPEDANCE:50 OHMS

Figure 70The VHFCW Source is an excellent input source formeasuring linearity performance of flash ADCs.


High Speed Sampler (HSS)The High Speed Sampler provides anunder-sampling capability that handlesapplications requiring the capture ofvery high frequency waveforms andpulses such as those generated bypalette DACs, disk drive, andEthernet devices.

The HSS has a 256 K by l6-bit capturememory, a sampling head, and achannel card with a SuccessiveApproximation Register (SAR) basedreference DAC and timing control forsampling. The sampling head hasselectable input impedance of 37.5, 50,

75, and l0 kOhms. The sampler headcan be located on a channel card or onthe DIB. The close location of thesampler head on the DIB to thedevice under test, eliminates fre-quency domain calibration becausetransmission line loss is not an issueand impedance can be appropriatelymatched. This location also providessignificant noise reduction, so averag-ing of multiple acquisitions is unneces-sary, directly impacting test time. Thesampler has less than l00 µVrms ofnoise over the entire l GHz band-width, which translates to 11 nV/rt Hz.

The HSS provides a l GHz inputbandwidth and can capture signalswith an effective sampling rate of up tol00 GHz as shown in figure 71. Theinstrument resolution is programmablebetween 2- and 16-bits, with theSuccessive Approximation Register(SAR) architecture. The ability toadjust resolution ultimately affectsoverall timing since reduced resolutionequates to reduced test time. Lowerresolution conversions can be used forfaster test speed when high accuracy isnot required.

Figure 71The High Speed Sampler captures very high speed waveforms.

2- TO 16-BITSAR ARCHITECTURE

FS EFFECT < 100 GHZ

A5 DS I/O MODE

CHANNEL CARD SAMPLE HEAD

2.048 VPK INPUT

<350 PS RISETIME

INPUT IMPEDANCE:10K, 75, 50, 37.5 OHMS

256 K X 16-BITSAMPLE CAPTURE

MEMORY

DIGITAL CHANNEL

ADD.MCLK

1 MEG X 20-BITSAMPLE CAPTURE

MEMORY(DS I/O)


Very High FrequencyMeasure ModuleThe Very High Frequency MeasureModule extends the measurementcapability of the A585/A575/A565series of test systems to 250 MHz. Itdoes this in two ways. The VHFMMcontains a down conversion modulethat converts signals from 250 MHzdown to a 1 MHz bandwidth. Theinstrument has its own programmableLocal Oscillator with 1 Hz program-mable resolution. The VHFMM alsocontains a sampler head that can beused to undersample signals up to 250MHz. The VHFMM is extensivelyused in disk drive applications formaking all types of analog measure-ments including frequency responseand harmonic measurements. Seefigure 72.

TIME AND JITTERMEASUREMENTSOf major importance in most moderndevice testing is the ability to measurethe elapsed time between two eventsand the variation in timing of theedges of an event. Whether the twoevents are DUT generated or one isgenerated by the DUT in response toa stimulus from the test system, themeasurement of the time between thetwo events must be measured pre-cisely. Unlike other test systems whichmust measure time by using digitaledge search techniques that aredifficult to implement and consumetest time, Teradyne’s A585/A575/A565test systems have precision instru-ments that measure the time betweentwo events directly, using the signals

themselves to control the timemeasurement. Variations between areference edge and a DUT edge canalso be measured directly. Both ofthese time measurement capabilitiesdramatically increase test systemthroughput and accuracy.

Advanced Time MeasurementSubsystemEvery device pin has access to theA585/A575/A565 Advanced TimeMeasurement Subsystem (ATMS).The unique, multiple patentedATMS design provides a limitlessmeasurement range. The instru-ment can access every device pinunder program control through thedigital, dc and analog channels to

Figure 72VHF Measure Module

10 MHZREFERENCE

VECTOR BUS

PTS5 MHZ TO 250 MHZ

THADS


LO

100 KHZ TO 900 KHZ

TO HFDIG PLFD

DOWN CONVERTERAND FILTER

SAMPLER HEAD50 OHM


make propagation delay, skew,frequency, rise/fall time, and othermeasurements. It is highly accuratewith less than l ns error, and provides aflexible timer enabling system withthe following features:

• Precounter/timer – selects a singleevent to start a measurement from aseries of possible events

• Postcounter/timer – selects a singleevent to stop a measurement from aseries of possible events

• Stop after start interlock – to forcepositive time measurements

When measuring skew between twopins, the stop after start interlock canbe disabled so either pin can act as thestart signal.

The ATMS has two primary modes:time and event. In time mode, theATMS makes frequency, period, dutycycle, rise time, pulse width, and prop-agation delay measurements. In eventmode, the ATMS counts the numberof occurring voltage events and pro-vides total counts or ratios of countedevents to number of start events. TheATMS can make multiple successivemeasurements with its local l Kmeasurement memory and can auto-matically perform averaging functions.

Time Jitter DigitizerThe Time Jitter Digitizer (TJD)provides the A585/A575/A565 Seriesof Advanced Mixed-Signal TestSystems with the ability to precisely

capture the time at which two user-specified events occur. The twoevents (A and B events in figure 73)can be specified based on devicesignal voltage level (threshold) anddirection (slope). The TJD time-stamps each event or “writes down”the time at which each of the eventsoccurs, within its capture rate ability.The TJD looks like a 16-bit counterrunning at 128 GHz, due to interpola-tion. The TJD has a better than 10 psresolution. The TJD’s capabilities areideally suited to disk-drive and ATMclock and data jitter testing becausethe clock rates are fast and datapatterns are known in advance.

Figure 73The Time Jitter Digitizer measures elapsed timebetween two events for direct measurement ofphase, duty cycle or edge jitter.

CH1

CH2

CH3

SSSP1

SSSP2

A

E

B

TIME STAMP AMEMORY

TIME STAMP BMEMORY

A

B

AB

E

TIME BUSINTERFACE

TRIGGER BUSINTERFACE

EVEN

T SE

LECT

MUX


The A and B event inputs can comefrom the same channel, as in apulsewidth or period jitter measure-ment, or they can be from two differ-ent channels as in a phase jittermeasurement. The TJD can capturesuccessive events up to 28 MHz foreach time stamper into a 16 Kmemory. Therefore, the two timestampers can be interleaved for

56␣ MHz operation. A third, enable,channel is provided to enable thetime-stamping of either the A or Bevent. The TJD can also makefrequency measurements greater than350 MHz.

Figure 74 shows a simple example ofan application for the TJD, where thewidth of a pulse is being measured. In

this example, two events have beendefined. Channel 1, rising through 1 Vis defined as the A event, and channel1 falling through 1 V is the B event.

TIME STAMP A

TIME STAMP B

16 KMEMORY

16 KMEMORY

Figure 74Pulse width measurement using Time Jitter Digitizer


MICROWAVE INSTRUMENTSThis section provides an overview ofthe hardware and software modulesthat are used in Teradyne’s mixed-signal microwave test capability.Microwave capability is added to theA585/A575/A565 Series of AdvancedMixed-Signal Test Systems by theaddition of “front-end” modules thatextend operating frequencies to themicrowave region. These front-endmodules up-convert signals from theac sources, or down-convert signalsfrom the DUT to drive the digitizersand measurement instrumentsdescribed above. Refer to figure 75 foran interconnection diagram of themicrowave front-end modules. Formore details on Teradyne’s microwavemixed-signal test capabilities, refer tothe Teradyne document “A Blueprintfor Mixed-Signal Microwave Test”(document number 05983A-0795).

Microwave CW SourceThe Microwave CW Source consistsof a Teradyne-designed, two-cardset, one that plugs into the main-frame card cage of the test systemand a companion channel card thatplugs into the test head. It is anextremely fast and clean microwavesource. This module is completelymicrowave-tight. It operates over a4.5 MHz to 4 GHz range.

IF Modulation SourceThe IF Modulation Source extendsthe frequency range of the VHFAWGto accommodate microwave devicesby the addition of a frequency transla-tion card set. The card set extends thefrequency range to 5-180 MHz IF.The final output waveform is a pro-duct of the VHFAWG translated infrequency to a higher spectrum. The

new frequency range signals are fullysynchronized with ac measurements,other ac sources and digitizer modules.

Microwave Measure ModuleThe extension of the input frequencyrange of the measurement instru-ments to accommodate microwavedevices is achieved by the MicrowaveMeasure Module. The MicrowaveMeasure Module accepts signals from10 MHz to 6 GHz, over a +13 to -100dBm dynamic range, and provides anIF output to feed either the High-Frequency or Precision Low-Fre-quency Digitizers. Up to 30 MHzinformation bandwidth is supportedby the Microwave Measure Modulefor testing AM, FM, FSK, PSK,QPSK, π/4DQPSK, GMSK and I/Qdemodulation modes.

IF/MICROWAVEMODULATION SOURCE

MICROWAVEFRONT-END

MICROWAVEFRONT-END

MICROWAVE ADD-ONS DUT

VHFAWG

MICROWAVECW SOURCE

HIGHFREQUENCY

DIGITIZERDIGITALPATTERNMEMORY

CAPTUREMEMORY

SOURCEMEMORY

DIGITALFORMATTER

DIGITALCHANNEL

CARD

HF DIGITIZERCHANNEL

CARD

TERADYNE ADVANCED MIXED-SIGNAL TEST SYSTEM

VECTOR BUSFigure 75Mixed-Signal Microwave Test Capability


Microwave Vector NetworkAnalyzer ModuleThe Microwave Vector NetworkAnalyzer Module provides the built-incapability to extend automatic leveland network calibration right to thepins of the DUT. It incorporates thefunctions of routing sources to andmeasurements from each of four pins,through two ports, minimizing oreliminating applications circuitry onthe DIB. The Microwave VNAModule provides vector networkmeasurement (S-parameter) capabilityand provides accurate calibration ofload and reflection errors caused bythe interconnects between the testsystem and the DUT.

The Microwave VNA Module movesthe multiplexing and routing of signalsfrom the DIB where it can pose manycalibration problems, to the test head,where these problems are eliminated

by making them part of the calibrationpath. The input section supports androutes two microwave or modulatedsources to other sections of the moduleand, ultimately, to the DUT pins. Also,the module extends the source rangeby an additional -64 dBm to -114 dBm.A summing node within this section ofthe module provides Intermod testsignals without DIB-based compo-nents, again simplifying calibrationand DIB design. Internal calibrationstandards for open, short, load, andthrough termination are includedwithin the module and are traceable toNIST standards. External calibrationstandards from the DIB out throughthe handler contactor or probe needlesis fully supported. The dc matrix canalso be accessed from the module.

Teradyne’s MicrowaveSoftware LibraryThe extensive device test applica-tion library is continuously expand-ing to include new devices. Existingtest routines include a variety ofmodulation techniques includingAM, FM, FSK, PSK, QPSK, π/4DQPSK, GMSK and I/Q andstandard tests such as S-Parameters,Third Order Intercept, NoiseFigure, Isolation, Phase Noise, andError Vector Magnitude.


DC Instrumentation andTest Capabilities

The dc instrumentation and testcapabilities consist of the dc crosspointmatrix and the dc instruments de-scribed below.

DC CROSSPOINT MATRIXThe DC Crosspoint Matrix delivers dcsignals from a series of instruments inthe mainframe cabinet to multipledevice pins. The digital and analogchannel cards in the test head alsohave direct access to the dc matrix.

Figure 76 shows the 8 line by 48 pinfully guarded Kelvin (DC Crosspoint)matrix. Each pin includes a force and asense pin and pins can have their

guards grounded for applications thatrequire low noise and minimumcrosstalk. If the guard is driven, thenoverall system leakage in the signalpaths can be reduced. The instru-ments connected to matrix lines canbe disconnected, allowing the matrixto serve as a signal bus betweenmultiple DUT pins. In addition, eachmatrix pin can have a dedicatedAnalog Pin Unit behind it.

DC SUBSYSTEM

Standard V/l SourcesOn the A585, up to five dc sourcesoperating at 60 volts and 200 mA canbe connected to the matrix. These

V/I

AAPU

V/I

V/I

V/I

V/I

UP TO 68 AAPUs (A565)UP TO 48 AAPUs (A575)

UP TO 48 APUs (A585)

TOTAL: 48 DC PINS (A585/A575) 68 DC PINS (A565)

DIFFERENTIALVOLTMETER

KELVIN, FULLY

GUARDEDMATRIX

APU

AAPU

APU

AAPU

APU

AAPU

APU

AAPU

APU

AAPU

APU

UP TO 5 V/Is (A585)UP TO 4 V/Is (A575, A565)

Figure 76The A585 series dc matrix provides every device pinwith APUs and standard dc instruments. The A575/A565series dc matrix provides every device pin with AAPUsand standard dc instruments.


Figure 77A full spectrum of V/I instruments address themost demanding applications.10V 100V 1000V

10A

100 A

1A

100mA

HCCS

HPVI

HCU

HCVS

VI

POWER V/I

POWER V/I

APU

access the device through theDUTSRC path. A disconnect cardlocated in the test head allowssoftware to disconnect the device fromthe sources.

Through the Universal Bus, the V/Isources access the Measure Bus andthe Modulation Bus. The systemvoltmeter makes the voltage andcurrent measurements. The sourceprovides the current to voltageconversion, and the Modulation Busprovides the ability for an ac or dcsource to modulate a device powersupply for power supply rejectionratio tests. Refer to figure 77 for anoverview of the capabilities of the dcinstruments.

Differential VoltmeterThe dc matrix Differential Volt-meter can operate in a single-ended mode also and includes thefollowing features:

• Dual ±60 V single-ended voltmetersor a 120 V differential voltmeter

• Sample and difference module withxl, x10, x100 gain

• Noise reduction filter

• Driven guards with matrixconnectivity

The measurement system is calibratedagainst the same internal referencestandard used for the sources. Meteraccuracy is within 0.05%.

sources are four quadrant V/I instru-ments with solid-state switching forfast setup and low transients. Sourcesare calibrated under software control toan internal reference standard. Withthis reference standard, each V/Isource can force and measure voltageaccurate to within 0.05% and currentaccurate to within 0.1%. For highcurrent requirements, these sourcesconnect in parallel over the matrix oron the DIB.

The dc source can also connect to theDUT in a direct mode. The systemcan be configured to contain fouradditional sources on the A585 (3sources for the A565 and A575) thatconnect directly to the Device Inter-face Board. These DUT sources


Analog Pin Unit The A585 Analog Pin Unit (APU)can be configured to contain a total of48 pins in increments of three pins.These V/Is are also four-quadrantinstruments that measure currentwhile forcing voltage, and measurevoltage while forcing current. The V/Irange is ±24 V, ±30 mA.

Each group of 24 APUs is controlledby an MC68000 microprocessorresiding on a dedicated controllerboard that also contains 64 bytes ofRAM and 64 bytes of EPROM. Thememory stores instrument setup andcontrol instruction states and cancapture voltage readings from the local12-bit measurement A/D converterconnected to an APU measurementbus. The converter can make mea-surements at a 125 kHz rate, and thecontrollers can operate in parallel for

maximum test throughput. The APUsalso interface to the Modulation andMeasure Buses in order to access thesystem meter.

Advanced Analog Pin UnitThe A575 and A565 can be equippedwith a 30 V Advanced Analog Pin Unit(AAPU) as shown in figure 78. Up to48 AAPUs (A575) or 68 AAPUs (A565)can be configured in increments offour pins. These V/Is are four-quadrantinstruments that measure currentwhile forcing voltage, and measurevoltage while forcing current. TheAAPU has a programmable ±30 Vsource and a programmable currentclamp to ±30 mA in the force voltagemode. As a programmable currentsource, the AAPU has a programmable±30 mA force current, with program-mable compliance voltage to ±30 V.The AAPUs are implemented as rider

boards that install on the dc crosspointmatrix boards. The AAPUs providedirect connection to the Measure Bus.

High Current UnitThe 60 V/200 mA sources can beparalleled to provide greater currentsfor mixed-signal devices in high pincount packages. Additionally, theA585/A575/A565 series can be config-ured with four High Current Units(HCU) operating in four quadrantswith the ability to force and measurevoltages over a range of ±30 V and ±1A through the matrix.

The HCU can also be configured toconnect directly through theDUTSRC path instead of through thematrix. In this mode, the HCUprovides up to ±2 A and replaces thestandard 60 V/200 mA V/I.

DACMATRIX

AAPU CHANNEL CARD

AAPUCONTROLLER AAPU 1

STATION 1

AAPU 1STATION 2

MEASURE BUSLINES 1 & 2

(TO MEASURE BUS)

MATRIX LINES 1 TO 8(TO BACKPLANE AND DC SUBSYSTEM)

14AAPU 1GATE

ARRAY

MATRIXAND MUX

GATE ARRAY

UNIVERSALBUS

INTERFACE

DACAAPU 2STATION 1

AAPU 2STATION 2

14AAPU 2GATE

ARRAY

DACAAPU 3STATION 1

AAPU 3STATION 2

14AAPU 3GATE

ARRAY

DAC

V/I

V/I

V/I

V/IAAPU 4STATION 1

AAPU 4STATION 2

14AAPU 4GATE

ARRAY

MUX

Figure 78The Advanced Analog Pin Unit


Quad Power V/IThe Quad Power V/I provides fourindependent, fully floating powersupplies. The supplies float to ±300 Vabove ground and operate in either 2-or 4-quadrant modes. Maximumoutput current from any supply is 30 Aplulsed; however, for increased outputcapacity, the outputs can be paralleled.Maximum output voltage from anysupply is 50 V; however, the suppliesmay be stacked for greater voltages.

PRECISION DC INSTRUMENTATION

Precision Multimeter ModuleThe Precision Multimeter Module(PMM) option provides high accuracydc, ac, and resistance measurementsfor device test applications such as fullscale gain and offset measurements onhigh precision A/D converters andhigh accuracy voltage measurementson system silicon. The PMM, whichincludes a mainframe module and achannel card in the test head, can alsobe used as a reference meter forcalibrating analog instrumentation.For the device to channel card path,the instrument provides numerousoptions including driven guard for lowcapacitance. The PMM can also accessthe dc matrix and the Test HeadAnalog Distribution System(THADS) Bus in the test head.Through these connections, the PMMhas access to every device pin undersoftware control including digitalVLSI, analog, and dc pins. The PMMhas a programmable resolution of 23bits including sign and can makevoltage measurements with betterthan 3 ppm accuracy.

Reference SourceThe Reference Source is a low noisevoltage source. Many devices suchas precision ADCs, microcontrollerswith on-board ADCs, and DACsrequire an externally generatedreference voltage. The referencevoltage must be extremely stablewith very low noise, in order toaccurately measure the linearity andnoise performance of the converter.

The Precision Reference Source cangenerate up to ±11 V on one channelor, differentially, on two channels, ±11V each with 17 bits of resolution. It hasa rapid settling time of <2 ms to 1 ppmof final value for high throughputtesting and remains stable to <5.5 µVof drift over 5 seconds, which isnecessary when testing linearity ofhigh resolution converters. TheReference Source has less than 3.5 µVrms noise over a 20 kHz range, whichis required to accurately determine thedevice signal-to-noise ratio perfor-mance with the Precision LowFrequency Source and Precision LowFrequency Digitizer.

Quad Op Amp LoopWith the continued integration ofApplication Specific Standard Prod-ucts (ASSP) in the consumer, commu-nications, automotive, and instrumen-tation markets, high performanceanalog components are continuallyadded to the system silicon. Thecomponents, which include precisionoperational amplifiers, analog switches,comparators and line drivers, requirehigh performance instruments in theproduction environment wherethroughput and measurement guard-banding are critical for improved yield.

Many of the A585/A575/A565 seriesadvanced analog instrumentsintegrated into the Universal Busarchitecture, provide synchronousmeasurements to a common, highperformance meter.

The Quad Op Amp Loop (QOA)shown in figure 79 is used for gain,VOS, and rejection ratio testing ofoperational amplifiers and for deviceswith on-board op amps. The QOAemploys four parallel measurement

Figure 79A single Op Amp Loop testing one component. Threewires are the only required connections.

DUT

VSET

INTEGRATOR

LOOP OUTPROGRAMMABLE

SUMMERFILTERLCA

LCA


loops, allowing measurement of allstandard dc parameters. When makingV

OS based measurements, the QOA

provides ranges from 970 nV to 99 mV.Accuracy is 0.25% in x100 and x1,000gains, and 0.5% in x10,000 gain setting.Each loop provides selectable internalgain of x100, x1,000, and x10,000 withswitchable polarity. Input Vos nullingup to ±20 mV provides improvedresolution for making AVOL, PSRR,and CMRR measurements.

Both continuity testing at 220 µA andsolid-state switching for short-circuitcurrent testing are provided. Built-inalarms detect device oscillation, loopsaturation, and open loop conditions.

Although the Quad Op Amp Loop is asingle board instrument in the testhead, multiple boards can be added tohandle additional parallel devicetesting. The QOA accesses theUniversal Bus elements including theTrigger Bus, Measure Bus, and theModulation Bus for complete opera-tional amplifier testing.

Low Current AmmeterThe Low Current Ammeter (LCA) isa test head channel card instrument forbias and leakage current measurementof high performance Op Amps andMOS switches embedded on mixed-signal devices. The LCA depicted in

Figure 80The Low Current Ammeter tests eight devicepins in parallel.

figure 80 provides measurementcapability down to the sub-picoAmpregion and can act as a stand-aloneinstrument or as a companion instru-ment to the QOA. The LCA containsparallel I/Vs that operate in eitherresistive or integration mode whenmeasuring ultra low currents.

In resistive mode, three ranges areavailable: 100 nA, 1 µA, and 10 µA. Inintegrate mode, additional rangesinclude l0 nA, 1 nA, 100 pA, and 10pA. Measurements are made rapidlywith an on-board commutator selectorand multiplexer, which are synchro-nized by the Universal Bus.

GUARD

REF

V8(t)C

GUARD

REF

V7(t)C

GUARD

COMMUTATIONSELECTOR AND MUX

LOW CURRENT AMMETER(3 OF 8 CHANNELS SHOWN)

REF

V6(t) V6(t)

t

t

t

C

–

+

–

+

–

+

V7(t)

V8(t)1 2 3 4 5 6 7 8 9

••

V8(t)V7(t)V6(t)V8(t)V7(t)V6(t)

••



The signal delivery path to theinstrument is critical for successfullymaking low current measurements.The advanced mixed-signal testhead provides a Teflon® insulatedpath to minimize leakage due todielectric absorption.

The LCA interface includes theUniversal Bus elements of the Mea-sure Bus and the Trigger Bus.

Pulse DriverTesting high speed Op Amps withvery fast rise and settling time charac-

teristics requires an input signal that ishigher quality than the device itself.The Pulse Driver can generate pulsesfrom 100 ns to 4 ms in width with arise time <20 ns, settling to 1% of finalvalue in less than 50 ns. The program-mable swing of the driver is ±5.5 V.

This channel card-based instru-ment has multiple output signalpaths to the DUT. A 50 Ohm RFconnection provides a high qualitysignal path. A 95 Ohm analogsignal path offering voltage swingsto ±11 V with selectable 35 ns or

85 ns risetime and 250 ns or 100 nssettling time is available, as well asdifferential ECL outputs.

Pulse generation can be triggered fromthe Universal Bus through the TriggerBus interface. See figure 81.

Figure 81Multiple output channels are provided for thepulse driver.

START

THADS TO DIBDC MATRIX TO DIB

TIME MEASUREMENT BUS

STOP

PULSE_ECL

PULSE_RF

TO DUT

PULSE CHANNELS

PULSE_B2

PULSE_B1

PULSE_A2

PULSE_A1PULSE GENERATOR

OUTPUTSWITCHING



SYNCHRONIZED POWERINSTRUMENTATIONA variety of high power voltage andcurrent instruments used in automo-tive and power management testapplications are available for use in theA585 and A565 series test systems.Designed by Teradyne, these instru-ments have:

• An optimized ATE environmentstrategy with fast switching andcontrol for production test

• High performance that meets andexceeds the most difficult devicedemands

• Internal instrument protection thatmaximizes Mean Time BetweenFailures (MTBF) by preventing

sessions. These include:

• Limit Alarms – occur if a voltageclamp or current clamp is reached

• Open Loop Alarms – occur when acontrol loop is unstable

• Overload Alarms – occur if excessivecurrent is flowing in the instrumentsense lead

• Over Voltage Alarms – occur in theevent of overvoltage condition acrossthe instrument output

• Heat Sink Alarms – occur if thethermal sensor on the internal heatsinks senses that a temperature istoo high

Figure 82All power instruments can be two stationmultiplexed and interfaced to the Universal BusArchitecture.

instrument failures caused by abad device

• IMAGE software control, debugdisplays, and operating environment

• Intelligent software routines thatprevent test programs from hotswitching

• Crowbar circuits that provideadditional protection

These mainframe-based instrumentsare shielded and enclosed withmultiple signal interlocks to protectengineers, operators, and servicepersonnel from accidental injury.

Internal system alarms help preventsystem failures during debugging

HPVI BVCS

•••

HCCS

HVA

DC METER

DC_MATRIX:1

DC_MATRIX:2DC_MATRIX:3

DC_MATRIX: 12

HCCS_INHCCS_OUT

HPVI_HIHPVI_LOW

HP_MATRIX:1

HP_MATRIX:2HP_MATRIX:3

HP_MATRIX:12

TWO

STATION

MUX

POWERCHANNEL

CARD



• Temperature Warning Alarms –occur if a temperature shutdownlevel is being approached

• Over Current Alarms – occur ifgreater than 200 mA is flowing whenmaking a range change, connect ordisconnect

• Junction Temperature Alarms –occur if an instrument outputtransistor junction temperaturebecomes too high

The power instruments cover a fullspectrum of voltage and currentrequirements ranging ±750 V and±100 A. Refer to figure 76. Theseinstruments access the Universal Busarchitecture as illustrated in figure 82.

support 40 A (80 A pulsed) and twosupport 20 A (40 pulsed). Each pin onthe 20 A dc line supports up to 5 A dcor up to 10 A pulsed. Each pin on the40 A dc line supports up to 10 A dc orup to 20 A pulsed. The maximumvoltage rating is 1000 V. Connectionsto the standard dc matrix are protectedwith 1 A fast-blow fuses and 65 V trippoint crowbar circuits. A second HPMprovides a total of 24 high powermatrix pins to the DUT. Pulsed poweris used for testing devices that requirehigh current and device packageprotection from heat, which could alterthe device characteristics.

High Power V/lThe High Power V/I (HPVI) can forcevoltage and measure current, and forcecurrent and measure voltage over arange of 750 V and 10 A. It provides anauto crossover into the power sinkingquadrant (+V, -I) and can rapidlydischarge reactive loads. The instru-ment is fully floating. By reversing itsconnection signals, it can also operatein the -V quadrants.

High Power MatrixThe standard dc matrix handles 1 Athrough its relays and signal paths.The optional High Power Matrix(HPM) supports an additional 4 linesand 12 pins. See figure 83. Two lines

Figure 83The High Power Matrix extends the standardsystem matrix and provides the ability for powerinstruments to access multiple device pins whilereducing load board electronics.

CROWBAR 10 A 10 A

40 A 40 A 20 A 20 A

L1 L2 L3 L4

5 A 5 A HP_MATRIX1DC_MATRIX

CROWBARHP_MATRIX2

HP_MATRIX3

••

••

DC_MATRIX

CROWBARDC_MATRIX

CROWBARHP_MATRIX12DC_MATRIX

AAPUAAPU

APU APU


High Current Current SourceThe High Current Current Source(HCCS) is commonly used forRdsON and Vcesat measurements orin applications that require a largecurrent load. It can source or sinkcurrent up to 100 A at 14 V in pulsedmode and independently measurevoltage or current. In non-pulsedmode, it is capable of 25 V and 15 A,continuous. When operating as a load,it can have as much as 100 V acrossand float to 1000 V referenced toground. In either source or load mode,the HCCS connects to the DIBthrough the high power matrix.

High Current Voltage SourceThe High Current Voltage Source(HCVS) is another instrument forapplications requiring pulsed powerup to 12 V at 100 A or 110 V at 25 A.

This instrument is commonly usedin automotive applications wherethe automotive battery is simulatedto test devices such as high sideswitches. The HCVS forces voltageand measures current. It floats withreference to ground. HCVS providesauto crossover to the power sinkingquadrant (+V, -I) and can rapidlydischarge reactive loads. The HCVSconnects to the DIB through thehigh power matrix.

High Voltage AmmeterThe High Voltage Ammeter has fullfloating capability for performingleakage measurements and H-bridgetesting. Leakage current is minimizedin the signal path by employing adriven guard design. The HVAconnects to the DIB through the HighPower Matrix. This instrument

measures current up to 100 mA andprovides ±20 nA accuracy. It can floatto 1000 V common mode voltage.

Breakdown VoltageCurrent SourceThe Breakdown Voltage CurrentSource (BVCS) makes very lowcurrent breakdown voltage measure-ments. The BVCS is a test head-basedchannel card used in conjunction withthe High Power V/I. The instrumentcan float to the voltage level of thesourcing instrument with a minimumcurrent forcing range of 10 µA. TheBVCS also has a voltage source modefor leakage measurements andcontains both voltage and currentmetering capability.


Because of the greater integration fromboth the analog and digital ends of thespectrum, today’s devices demand awide range of mixed-signal test instru-mentation performance. This widerange of test instrument performancerequires a test head that can provide avariety of signal paths between thedevice and system instrumentation.The A585/A575/A565 Series ofAdvanced Mixed-Signal Test Systemsmeets these increased demands withtwo implementations of test head andtest head/mainframe interconnections,each tailored to the test systemcapabilities that they support. Instru-ment channel card electronics close tothe device and signal delivery pathsfrom the channel card to the deviceinterface board provide a full spectrumof instrument performance.

Each instrument requires a uniquesignal path in order to guaranteeperformance at the DUT:

• Ultra-low (sub-picoAmpere) currentmeasurements require conductorswith very low dielectric absorptionand triboelectric effects. This isprovided by a Teflon-isolateddelivery path

• To minimize resistance, high voltageand current instruments need heavygauge conductors

• Precision Low Frequency Sourcerequirements exceed 115 dBharmonic distortion. To guaranteethis exceptional performance, signalstravel through shielded, twisted pairsfrom the channel card to the inter-connections of the interface area

• The 25/50/100/200 MHz digitalsignals travel through a 50 Ohmcoaxial environment

• RF and very high frequency wave-forms travel through a 50 Ohmsemirigid coax conductor

To meet the instrument specificationsand reduce application complexity, theadvanced mixed-signal test headfeatures include:

• Signal paths custom-configured foreach instrument type

• Guaranteed instrument performanceat the device interface area

• Channel cards with programmableflexibility, minimizing the amount ofnecessary applications circuitry

• Device interface area with maxi-mum space for users to add theirown circuitry

• Ability to dock to a variety ofhandlers and probers

DIRECT-DOCKING: ADVANCEDMIXED-SIGNAL TEST HEADThe A585 Advanced Mixed-SignalTest System can accommodate up to192 digital I/O pins, and the A575 canaccommodate up to 128. Both can beconfigured with up to 40 analog pinsand a minimum of 48 dc pins. A totalof 384 shielded Iso-Pin connectionscan connect to the DUT.

The left side of the test head has 24slots for digital channel cards, the righthas 15 for analog instrumentationchannel cards. The remaining slotscontain utility support functions, dc

Production Interface


• Relay disconnect cards for multiplex-ing a single instrument to multipledevice pins

Configuration BoardThe configuration board (signaldelivery board) connects the channelcards to the Iso-Pin connections. Seefigures 85, 86 and 87. Two configura-tion boards contact the channel cardsand the test head Iso-Pins. The digitalconfiguration board connects thedigital pins to the Iso-Pins and carries

the 5O Ohm coaxial wire. The analogconfiguration board connects theanalog channel card signals to the Iso-Pins and contains the appropriatesignal paths for the system and testhead instrumentation.

It is the configuration board thatprovides the ability to adapt thesignal delivery system to a widerange of instrumentation withoutrequiring a different interfaceenvironment. Standard configura-

matrix, dc resource, and time measure-ment support. Figure 84 depicts atypical channel card configuration.

The digital and utility support func-tion slots are fixed. The configurableanalog slots accommodate:

• High performance analog instrumen-tation channel cards

• High performance advanced analoginstrumentation

• User designed channel cards

Figure 84Direct-docking test head layout with a typicalchannel card configuration

FAN

FAN

TOP VIEW

CABLE EXIT(TO MAINFRAME)

5352515049484746454443424140

39

38

37

36

35343332313029282726252423

SLOT NUMBER

AD936 DIG CHAN SUPP BD#3AD935 DIGITAL CHANNEL CARD #3_1AD935 DIGITAL CHANNEL CARD #3_2AD935 DIGITAL CHANNEL CARD #3_3AD935 DIGITAL CHANNEL CARD #3_4AD935 DIGITAL CHANNEL CARD #3_5AD935 DIGITAL CHANNEL CARD #3_6AD935 DIGITAL CHANNEL CARD #3_7AD935 DIGITAL CHANNEL CARD #3_8AD936 DIG CHAN SUPP BD#1AD935 DIGITAL CHANNEL CARD #1_1AD935 DIGITAL CHANNEL CARD #1_2AD935 DIGITAL CHANNEL CARD #1_3AD935 DIGITAL CHANNEL CARD #1_4

AD943 TEST HEAD TDR I/F

AD935 DIGITAL CHANNEL CARD #1_5AD935 DIGITAL CHANNEL CARD #1_6AD935 DIGITAL CHANNEL CARD #1_7AD935 DIGITAL CHANNEL CARD #1_8AD936 DIG CHAN SUPP BD#2AD935 DIGITAL CHANNEL CARD #2_1AD935 DIGITAL CHANNEL CARD #2_2AD935 DIGITAL CHANNEL CARD #2_3AD935 DIGITAL CHANNEL CARD #2_4AD935 DIGITAL CHANNEL CARD #2_5AD935 DIGITAL CHANNEL CARD #2_6AD935 DIGITAL CHANNEL CARD #2_7AD935 DIGITAL CHANNEL CARD #2_8

READY DISCONNECT CARD

REFERENCE SOURCE

PLF SOURCE #1

PLF DIGITIZER #1

HIGH FREQUENCY DIGITIZER #1

SAMPLER (M)

PMN

TMS

HEAD ACCESS CARD

TRIGGER ACCESS CARD HEAD

CAL STROBE BUFFER

HEAD UTILITY CARD

ANALOG TEST HEAD DATA BUFFER



PLF SOURCE 2 OR SAMPLER (S) #2

VHFAWG #1

UHFCW

VHFACW #1

VHFACW #2

VHFAWG #2

OPEN

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

SLOT NUMBER


analog and digital signals over conven-tional, unshielded environments. Seefigure 86 and 87.

Device Interface BoardsA variety of device interface boardsaccommodating a number of uniqueinterface schemes are available for useon the test floor. The standard boardprovides over 60 square inches for

ISO-PIN CARRIER

DIB BOARD

CONFIGURATION BOARD A(ANALOG)

CONFIGURATION BOARD B(DIGITAL)

CHANNEL CARDS

TEST HEAD STATION BASE

CHANNEL CARDS

CARD CAGES

CABLE ENTRANCE

SUPPORT CARDS

Figure 85Exploded view of the A585 Series AdvancedMixed-Signal test head elements

tion boards designed by Teradyneaccommodate most typical instru-ment configurations.

Iso-Pin ConnectionsThe Iso-Pins are spring pins thatconnect the configuration board to thedevice interface board (DIB). TheTeradyne patented Iso-Pin designmaintains a shielded environment tothe DIB and provides a 40-50 dBcrosstalk reduction between the

user-specified applications interfacecircuitry. Typically, the interface boardcarries only the appropriate bypasscapacitors required by the device andthe signal connections from the DUTpin to the tester Iso-Pin. The channelcards eliminate the need for applica-tions circuitry required by a conven-tional test system.


WIRE TO DUT PINDIB VIA ISO-PIN VIA

ISO-PIN CONTACT PAD

ISO-PINPC TRACE

ISO-PIN CONTACT PAD

DIB

ISO-PIN CARRIER

CONFIGURATION BOARD

ISO-PIN VIA

NOTE: THE CONNECTING WIRE WILL EITHER BE A COAXIAL CABLE OR A PC TRACE, BUT NEVER BOTH.

CONFIG VIA

COAXIAL CABLE

PC TRACESPRING PIN

SPRING VIA

SPRING PIN CONTACT PAD

CHANNELCARD

Figure 87The Teradyne patented Iso-Pins deliver fullinstrument performance in a shielded environ-ment while withstanding the rigors of theproduction floor.

ISO-PIN VIAS

SIGNAL SHIELD

DEVICE INTERFACE BOARD

TEFLON DIELECTRIC ISO-PIN CONTACT PAD

SO-PIN CONTACT PAD

ISO-PIN CARRIER

SHIELD BARREL

LINK TO SHIELD

ISO-PIN CONTACT PAD

SIGNAL SHIELD

CONFIGURATION BOARD

ISO-PIN VIAS

ISO-

PIN

ISO-

PIN

Figure 86The Configuration Board carries the requiredsignals for all the instruments.


CABLE INTERFACE: PRODUCTIONANALOG TEST HEAD (PATH II)The A565 Advanced Mixed-SignalTest System can also be configuredwith the Production Analog Test Head(PATH II). The test head has eightslots for digital channel cards andseven for analog instrumentationchannel cards and two for power V/I

channel cards. The remaining slotscontain utility support functions, dcmatrix, dc resource, and time measure-ment support. Figure 88 depicts atypical channel card configuration.

The PATH II test head is muchsmaller than the direct-dockingAdvanced Mixed-Signal Test Head.

See figure 89. Because it eliminatesthe need for precision mechanicaldocking assemblies, the PATH II headreduces cost both in terms of materialsand floor-space, optimizing it fortesting highly cost-sensitive devices.Connection to test-floor equipment isachieved via a cable interface betweenthe configuration board and the device

Figure 88PATH II test head layout with a typical channelcard configurationTOP VIEW

OPTIONS

DIGITAL

CHANNEL

ZONE

RF

ZONE

DEFAULT SLOT ASSIGNMENT

AD943 TEST HEAD TDR I/F

AD936 DIGITAL CHANNEL SUPPLY BOARD

HIGH SPEED DIGITAL 1-8








RDC48

HEAD ACCESS CARD

TRIGGER ACCESS CARD

CALIBRATION STROBE BUFFER

HEAD UTILITY CARD

ANALOG TEST HEAD DATA BUFFER

HIGH FREQUENCY DIGITIZER

LOW FREQUENCY SOURCE

LOW FREQUENCY DIGITIZER

VHF ARBITRARY WAVEFORM GENERATOR

VHF ARBITRARY WAVEFORM GENERATOR

MW CHANNEL CARD

POWER SOURCE CHANNEL CARD

POWER SOURCE CHANNEL CARD

TIME MEASUREMENT SUBSYSTEM

DEDICATED

DEDICATED

DIGITAL CARD

DIGITAL CARD

DIGITAL CARD

DIGITAL CARD

DIGITAL CARD

DIGITAL CARD

DIGITAL CARD

DIGITAL CARD

DEDICATED

DEDICATED

AC CARD

AC CARD

AC CARD

AC OR RF CARD

AC OR RF CARD

AC OR RF CARD

POWER V/I CARD

POWER V/I CARD

AC CARD

DEDICATED

DEDICATED

DEDICATED

DEDICATED

SLOT NUMBER

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25


board. See figure 90. Either the cableinterface or the configuration board/cable assembly can be quickly andeasily changed.

The PATH II configuration supports72 dc channels, 64 digital channels,

and has eight analog channel card slotsfor precision ac and other head-basedanalog instruments. There are twotime measurement channels in PATHII. The instruments are specified atthe end of 39" (1 meter of cable).Physically the PATH II measures 28"

wide by 18" deep by 18" high (71 cm x45 cm x 45 cm).

The PATH II is software compatiblewith the Advanced Mixed-Signal(AMS) test head. Programs developedon PATH II can be leveraged to other

Figure 89The PATH II cable interface easily connects to testfloor equipment like the Tokyo Seimitsu probershown here, without requiring expensive, custom-designed docking assemblies.


A585/A575/A565 series test systems byattaching the cable interface to thedevice interface board on the Ad-vanced Mixed-Signal test head.

HANDLER AND PROBERINTERFACINGAppropriate mechanical, electrical andcommunications interfaces must

integrate with handlers and probers onthe production floor. A wide variety ofhandlers and probers are supported bythe A585, A575 and A565 Mixed-Signal Test Systems.

The A585 and A575 systems use adirect docking method of interfacingthat minimizes signal path length

between the silicon and the testerchannel. The robust design of thedocking mechanics withstands therigors of the production floor.

Figure 90PATH II Configuration Board installed in an A585/A575 Advanced Mixed-Signal Test Head allows onetest system in engineering to be used to developtest programs for AMS or PATH test heads.


Figure 91A585 Footprint

A summary of the primary systemmodel configurations within the A585/A575/A565 Series of Advanced Mixed-Signal Test Systems is provided below.The A585/A575/A565 series modelsare designed to be compatible subsetsof one another, sharing the sameinstrumentation, but differing in

baseline configurations. Test programsdeveloped on one can be imple-mented on the other. Please refer totable 4 that follows for a tabularcomparison of each system, and tofigures 91, 92 and 93 for a footprintcomparison.

System Configurations

12"(30.5 cm)

124"(315 cm)

41"(104 cm)

35"(89 cm)

44"(112 cm)

76"(193 cm)

29"(74 cm)

USERCOMPUTER

MIXED-SIGNALTEST HEAD 1


A585 MAINFRAMEDIGITAL ANALOG

A585 Mainframe


TEST SYSTEM FOOTPRINTThe A585/A575/A565 instrumenta-tion provides high performance andreliability in a compact systemfootprint. The highly integratedE/MOS design of the digital pinshelps to minimize the size of the

system by reducing the number ofprinted circuit boards and back-planes. A fully configured 192 pinA585 test system mainframe occu-pies only 37 square feet. A fullyconfigured 128 pin A575 test systemmainframe occupies only 23 square

feet, and the A565 with 64 digitalchannels, occupies 17 square feet.

The test systems can be configuredwith two direct-docking AMS testheads. See figures 91 and 92. Main-frame instrumentation is multiplexed


12"(30.5 cm)

75"(190 cm)

41"(104 cm)

35"(89 cm)

44"(112 cm)

76"(193 cm)

29"(74 cm)

USERCOMPUTER



A575 MAINFRAME

32"(81.2 cm)

18"(45.7 cm)

POWERVAULT



12"(30.5 cm)

64.25"(165 cm)

28.3"(71.8 cm)

32"(81.2 cm)

38"(96.5 cm)

39"(99 cm)

16"(40.6 cm)

18"(45.7 cm)

29.5"(74.9 cm)

USERCOMPUTER

PATH IITEST HEAD 1

PATH IITEST HEAD 2

A565 MAINFRAME

POWERVAULT

to both stations, allowing for up totwice the test throughput for theincremental cost and floorspacerequirements of the second test head.

Each head can have a different slotassignment and a different number ofcards. For example, if the first headhas 192 digital pins, the second head

can be targeted for devices with lowerpin count, thus requiring fewer pins.


The A565 base configurationsupports analog/dc parametrictesting. The first extension of A565configuration adds either the pre–cision ac instrumentation andassociated card cage and powersupply, or the digital instrumenta-tion and its associated card cage andpower supply. The A565 can befurther extended to be configured asa mixed-signal test system, withadditional mixed-signal capabilities.

A565 ADVANCED MIXED-SIGNALTEST SYSTEMThe A565, another member of theA585/A575/A565 Series of AdvancedMixed-Signal Test Systems, is de-signed for testing high volume, lowASP devices. The A565 features theperformance of the A585 instrumenta-tion in a system that can be moreflexibly configured for test applicationshighly sensitive to cost. Like the A585and A575, the A565 supports paralleltesting to further increase throughputand reduce cost-to-test. The A565uses the PATH II test head or optionaladvanced mixed signal test head.

A585 ADVANCED MIXED-SIGNALTEST SYSTEMThe A585 is the high pin countmodel of the A585/A575/A565Series of Advanced Mixed-SignalTest Systems. The A585 is able tosupport two Advanced Mixed-Signal test heads, with virtually allavailable options. The A585 can beconfigured to support both diskdrive device and RF device testingin a single test head, with somelimitations on expansion in that testhead. Over time, as needs change,instruments can be added, movedand a second test head can beinstalled.

A575 ADVANCED MIXED-SIGNALTEST SYSTEMThe A575 is a lower-cost, reducedconfiguration version of the A585. Itfeatures the precision and flexibility ofthe A585, but with limitations on thetotal digital pin count.


Feature and Specification Comparison among the A585/A575/A565 Series Test Systems

SUBSYSTEM A585 A575 A565DC Instrumentation60 V/200 mA V/IMatrix 5 max. 4 max. 4 max.DUT_SRC 4 max. 3 max. 3 max.Analog Pin Unit O N/A N/AAdvanced Analog Pin Unit N/A O O

Digital InstrumentationMaximum Pin Count 192 128 64

Data Rate (MHz)PATH II HSD25 — — 25/50AMS HSD50–25 25/50/100 25/50/100 25/50/100

HSD50–51 50/100/200 50/100/200 50/100/200HSD50–50 50/100/200 50/100/200 50/100/200

Top Speed (Mbps)PATH II HSD25 — — 50AMS HSD50–25 100 100 100

HSD50–51 200 200 200HSD50–50 200 200 200

Edge Placement AccuracyPATH II HSD25 — — ±1 nsAMS HSD50–25 ±500 ps ±500 ps ±500 ps

HSD50–51 ±500 ps ±500 ps ±500 psHSD50–50 ±350 ps ±350 ps ±350 ps

Pattern DepthPATH II HSD25 — — 64 K/1 Meg optionAMS HSD50–25 1 Meg 1 Meg 1 Meg

HSD50–51 510 K/1 Meg option 510 K/1 Meg option 510 K/1 Meg optionHSD50–50 1 Meg 1 Meg 1 Meg

Second Sequencer Opt. Opt. N/ADual Sequence Function Full Limited N/A

AsynchDSI/O

Digital Signal I/O (Serial) Opt. Opt. Opt.Vector Bus Memory for SCAN Opt. Opt. N/A140 MHz Channels Opt. Opt. N/ASuperclock Opt. Opt. N/ASuper Speed Serial Pins Opt. Opt. N/ATime Jitter Digitizer Opt. Opt. N/ARelative Analog Mainframe Space Units 40 22 18/49

Test HeadPATH II N/A N/A SAdvanced Mixed Signal S S Opt.

PhysicalFloor Space (sq. ft.)

Mainframe 37 23 17Test Head Plus Manipulator 22 22 3

Cabinets 2 1 1

S = Standard;Opt. = Available Optional;N/A = Not Available for this system

Please contact your Teradyne salesperson for detailed configuration information.Table 4Feature and Specification Comparison amongthe A585/A575/A565 Series Test Systems


Instrument Specifications

KEY INSTRUMENTSPECIFICATIONS AND FEATURESKey specifications and features areprovided here for each of the instru-ments presently available for the A585/A575/A565 Series of Advanced Mixed-Signal Test Systems. These specifica-tions are subject to change. Pleasecontact your Teradyne sales engineerfor current specifications. Somespecifications will vary based on thetest head used.


DIGITAL INSTRUMENTATION

High Speed Digital (HSD25)Feature Specification

Maximum channel count 64 channels

Vector rate (non-multiplexed)Basic vector rate 25 MHzSingle cycle I/O 50 MHzDual drive 50 MHz

Minimum vector rate 5 kHz

Pattern depth 64 K; 1 Meg optional

Pattern depth @ single cycle I/O 128 K; 2 Meg with option

Pattern depth @ dual drive 128 K; 2 Meg with option

Keep alive pattern memory 16 vectors

History memory 4 K vectors

Cycle counter 32 bits

Digital signal source memory 64 K x 20 bits

Digital signal capture memory 1 Meg x 20 bits

Edge placement accuracy ±1 ns

Edge resolution 78 ps

Edges per pin 6 (dl, d2, d0, d3, rl, r2)

Edge sets per edge per pin 32

Global timing sets 1,023

Drive formats nrz ,nrzc, rz, rzc, ro, rocl, cs,csc, clkhi, clklo, fhi, flo, off,drvclkhi, drvclklo, drvhi, drvlo

Compare formats cmplo, cmphi, cmplog,cmpmid, cmppat, cmpmask,cmpoff, rcvhi, rcvlo, rcvmid,rcvmask

Driver characteristics (with cable)VIH/VIL range -2 V to +7 VResolution 1 mVOutput impedance 50 OhmMinimum pulse width (3 V swing) 10 nsRise/fall time (3 V swing) < 5 nsRise/fall time (9 V swing) < 10 ns


High Speed Digital (HSD25) (continued)Feature Specification

Comparator characteristics (with cable)VOH/VOL range -2 V to +7 VResolution 1 mVInput impedance @ dc 4 MOhmTransmission line characteristics 7.0 ns delay @ 50 OhmCapacitance <2 pFMinimum pulse width detection

12 ns @ 500 mV overdrive

Dynamic load characteristicsIOH/IOL range 50 mAResolution 5 µAVcp range -2 V to +7 VVcp resolution 1 mVI/O channel termination mode 50 Ohms

Per pin parametric measure unit characteristicsVoltage forcing/measuring -2 V to +7 VVoltage forcing resolution 275 µVVoltage forcing accuracy ±(0.16% + 14 mV)Voltage measuring resolution 3.66 mVVoltage measuring accuracy ±(0.43% + 18 mV)Current forcing ±2 mA, ±200 µA (2 ranges)Current measuring ±2 mA, ±200 nA (5 ranges)

Current measuring resolution±200 nA range 293 pA

Current measuring accuracy±200 nA range ±(1.4% + 2.1 nA)

These specifications are subject to change. Please contact your Teradyne sales engineer for currentspecifications. Some specifications will vary based on the test head used.


High Speed Digital (HSD50-50)Feature Specification

Maximum channel count 192 channels

Vector rate (non-multiplexed)Basic vector rate 50 MHzSingle cycle I/O 100 MHzDual drive 100 MHz

Vector rate (multiplexed)Basic vector rate 100 MHzDual drive 200 M bits

Minimum vector rate Approx. 5 kHz

Pattern depth @ basic vector rate 1 Meg

Pattern depth @ single cycle I/O 2 Meg

Pattern depth @ dual drive < 100 MHz 2 Meg

Pattern depth @ multiplexed mode 2 Meg

Pattern depth @ multiplexed, dual drive 4 Meg

Keep alive pattern memory 16 vectors

History memory 4 K vectors

Cycle counter 32 bits

Digital signal source memory 64 K x 20 bits

Digital signal capture memory 1 Meg x 20 bits

Edge placement accuracy ±350 ps

Overall tester accuracy ±500 ps

Edge resolution 78 ps

Fine edge resolution control 19 ps

Edges per pin 6 (dl, d2, d0, d3, rl, r2)

Edge sets per edge per pin 32

Global timing sets 1,023

Drive formats nrz ,nrzc, rz, rzc, ro, rocl, cs,csc, clkhi, clklo, fhi, flo, off,drvclkhi, drvclklo, drvhi, drvlo

Compare formats cmplo, cmphi, cmplog,cmpmid, cmppat, cmpmask,cmpoff, rcvhi, rcvlo, rcvmid,rcvmask

Driver characteristicsVIH/VIL range -4 V to +7 V (3 ranges)Resolution 1 mVOutput impedance 50 OhmMinimum pulse width < 5 nsRise/fall time (3 V swing) 1.35 ns ±500 psRise/fall time (5 V swing) 2.20 ns ±500 ps


High Speed Digital (HSD50-50) (continued)Feature Specification

Comparator characteristicsVOH/VOL range -4 V to +7 V (3 ranges)Resolution 1 mVInput impedance @ dc 4 MOhmTransmission line characteristics 3.0 ns delay @ 50 OhmCapacitance <2 pFMinimum pulse width detection 4 ns @ 500 mV overdrive

Dynamic load characteristicsIOH/IOL range 50 mAResolution 5 µAVcp range -4 V to +7 V (3 ranges)Vcp resolution 1 mVI/O channel termination mode 50 Ohms

Per pin parametric measure unit characteristicsVoltage forcing/measuring -4 V to +7 V (3 ranges)Voltage forcing resolution 275 µVVoltage forcing accuracy ±(0.16% + 14 mV)Voltage measuring resolution 3.66 mVVoltage measuring accuracy ±(0.43% + 18 mV)Current forcing ±2 mA, ±200 µA (2 ranges)

Current forcing resolution (±200 µA range) 22 nACurrent forcing accuracy (±200 µA range) ±(0.2% + 1.7 µa)

Current measuringCurrent measuring resolution (±200 nA range) 293 pACurrent measuring accuracy (±200 nA range) ±(1.4% + 2.1 nA)



Superclock (SCL)Feature Specification

Drive-only clock with differential output signal

Programmable frequency

Programmable clock pulse duty cycle

Programmable voltage levels

Requires dedicated PTS frequency synthesizer in mainframe

Frequency range 50 MHz to 400 MHz

Frequency resolution 1 HzFrequency accuracy 1 ppm + 1 ppm/year

DC output voltage (VIH/VIL, no load)Levels –2.0 V to +5.0 VResolution 1.22 mV nominalMaximum voltage swing

50 MHz to 100 MHz 5 VPK-PK100 MHz to 400 MHz 3.3 VPK-PK

Minimum voltage swing 0.5 VPK-PKRise/fall time (20% to 80%) <500 psUndershoot/overshoot <15%Output impedance 50 Ohms, nominal

TimingTiming resolution 20 ps nominalEdge accuracy

Alignment to HSDD1 to HSD ±350 ps or ±500 ps,

depending on system dashnumber

Duty cycleD1 to D2 accuracy ±150 psProgramming range 40% to 60%

Edge jitter 10 ps rms typical



Super Speed Serial Pins (SSSP)Feature Specification

Simultaneous drive and receive on a single channel card

Dual edge strobe mode to detect invalid data

Internal connections to Superclock (required)

Internal direct connections to Time Jitter Digitizer

Per Pin Parametric Measure Module on each wire of differential pair

Supports Digital Signal I/O

Two SSSPs can be multiplexed to one pair of pins for double data rate

Maximum of eight SSSPs per system

DriverData rate 100 Mbits/s to 400 Mbits/sOutput configuration DifferentialOutput impedance 50 OhmsRise/fall time <500 ps; 20% - 80%Overshoot/undershoot <15%Output voltage

Range -2.0 V to +5.0 VMinimum voltage swing 0.5 VPK-PK

Maximum voltage swing 5.0 VPK-PK, to 200 Mb/s3.3 VPK-PK, to 400 Mb/s

Data drive format NRZ

Receiver/ComparatorConfiguration DifferentialCompare strobe type Edge strobeData rate 100 Mbits/s to 400 Mbits/sDifferential inputs voltage levels 5.0 VInput voltage levels relative to ground -2.0 V to +5.0 VComparator termination

Programmable voltage level, relative to ground -2.0 V to +5.0 VVoltage resolution 1 mV; nominalImpedance 50 Ohms

Compare formats cmplo, cmphi, cmppat, cmplog,cmpmask, cmpoff

Edge jitterSquare wave 10 ps rmsPseudorandom pattern 40 ps rms



AC INSTRUMENTATION

Precision Low Frequence Source (PLFS)Feature Specification

Peak output voltage (ac + dc) ±11.0 VPK

Waveform resolution 20 bits

Maximum sample rate 25 MHz

Waveform memory size (standard) 64 K samples

Waveform memory segments (standard) 512

Waveform memory size (optional) 1 M samples

Waveform memory segments (optional) 512

DC baseline range ±11.0 V

DC baseline resolution 17 bits

Output impedance 25 Ohm, < 1 Ohm

Lowpass filters 2 k, 20 k, 100 k, 500 kHz

Waveform integrator sample rate < 20 MHz

Waveform linearity ±2 ppm

Total harmonic distortion50 Hz to 2 kHz 115 dB50 Hz to 20 kHz 110 dB50 Hz to 100 kHz 95 dB500 Hz to 250 kHz 75 dB250 Hz to 500 kHz 55 dB

Total noise (bandwidth)50 Hz to 2 kHz (50 Hz to 20 kHz) 110 dB50 Hz to 20 kHz (50 Hz to 100 kHz) 95 dB50 Hz to 100 kHz (50 Hz to 100 kHz) 80 dB500 Hz to 250 kHz (1 MHz) 60 dB250 kHz to 500 kHz (1 MHz) 55 dB



Precision Low Frequency Digitizer (PLFD)Feature Specification

Peak input voltage (ac + dc) ±11.0 VPK



Capture memory size 256 K samples



Input impedance > 10 MOhm

Input capacitance <200 pF

Frequency ranges 2 k, 5 k, 20 k, 100 k, 500 kHz

Digital filters194 selectable filters (time domain and frequencydomain)

Waveform linearity error ±2.0 ppm

Common mode rejection, amplitude range dependentdc to 100 Hz >105 dB100 Hz to 1 kHz >85 dB1 kHz to 20 kHz >60 dB20 kHz to 100 kHz >50 dB100 kHz to 500 kHz >35 dB

Total harmonic distortion≤ 400 Hz (2 kHz range) 115 dB400 Hz to 1 kHz (2 kHz range) 110 dB50 Hz to 5 kHz (5 kHz range) 105 dB50 Hz to 20 kHz (20 kHz range) 100 dB50 Hz to 100 kHz (100 kHz range) 80 dB50 Hz to 500 kHz (500 kHz range) 60 dB

Total noise (bandwidth)50 Hz to 5 kHz (50 Hz to 5 kHz) 105 dB50 Hz to 20 kHz (50 Hz to 20 kHz) 95 dB50 Hz to 100 kHz (50 Hz to 100 kHz) 80 dB500 Hz to 500 kHz (50 Hz to 500 kHz) 60 dB



Low Frequency AC Source (LFAC100 SRC)Feature Specification

Peak output voltage (ac + dc) ±11.0 VPK


Waveform memory 1 meg



Waveform amplitude range (dc to 100 kHz) <10.24 VPK

Waveform amplitude resolution <1 mdB

Output impedance (dc - 100 kHz) 25 Ohms, <1 Ohm

Waveform linearity error ±30 ppm

Total harmonic distortion50 Hz - 2 kHz 85 dB50 Hz - 20 kHz 85 dB50 Hz - 100 kHz 75 dB

Total noise (bandwidth)50 Hz - 1 MHz 85 dB50 Hz - 100 kHz 75 dB50 Hz - 1 MHz 65 dB



Low Frequency AC Digitizer (LFAC100 DIG)Feature Specification

Differential input voltage ±11.0 VPK

DC baseline range ±11.0 VPK


Input impedance >10 MOhm

Capture memory depth 256 K samples

Total harmonic distortion50 Hz - 20 kHz 85 dB50 Hz - 100 kHz 75 dB

Total noise (bandwidth)50 Hz - 20 kHz 85 dB50 Hz - 100 kHz 75 dB



VHF Measurement Module (VHFMM)Feature Specification

Modes Down-converter, Sampler

Measurement frequency range 5 MHz to 250 MHz

Measurement frequency resolution 1 Hz

Input signalDown-converter modeInput amplitude +10 dBm to -75 dBm

+10 dBm to -90 dBm, typicalRelative amplitude accuracy ±(0.2 dB + 0.05 dB/dB change)

Sampler mode See High Frequency Samplerspecifications.

Input impedance 50 Ohms nominal

Input VSWR <2:1, typical

Spectrum2nd Order intercept +50 dBm

+60 dBm, typical3rd Order intercept +23 dBm

+30 dBm, typicalLO-IF leakage <-70 dBmLO-RF leakage <-34 dBmImage rejection 0 dB

IF OutputIF nominal center frequency 500 kHzIF passband 100 kHz to 900 kHzIF flatness

100 kHz to 900 kHz <±1.2 dB400 kHz to 600 kHz <±0.75 dB

IF distortion <-42 dBcIF spurious

for input signals < 2.0 dBm <-50 dBmfor input signals > 2.0 dBm <-56 dBc



VHF Arbitrary Waveform Generator (VHFAWG)Feature Specification

Peak output voltage (ac + dc) ±2.0 VPK into 50 Ohm LoadWaveform resolution 12 bits


Waveform memory size 256 K samples1 M samples optional

Waveform memory segments 4,096

DC baseline range ±2.0 V into 50 Ohms


Output impedance 50 Ohm

Lowpass filters 0.5 M, 1.0 M, 2 M, 4 M, 5.5 M,6 M, 10 M, 15 M, 20 M,30 M, 45 M, 65 M, 80 MHz

Slew rate (filter bypass) 2000 V/µs typical

Step response filter characteristicsRisetime

6 MHz filter < 70 ns, typical30 MHz filter < 22 ns, typical45 MHz filter < 18 ns, typical65 MHz filter < 9.5 ns, typical80 MHz filter < 8 ns, typical

Overshoot/undershoot6 MHz filter < 2%, typical30 MHz filter < 2%, typical45 MHz filter < 2%, typical65 MHz filter < 8%, typical80 MHz filter < 8%, typical

Sinewave amplitude absolute accuracydc to 200 MHz ±0.25 dB @ 10 dBm

2nd & 3rd harmonic componentsdc to 4 MHz –60 dBcdc to 10 MHz –55 dBcdc to 30 MHz –45 dBcdc to 200 MHz –40 dBc

Noise density (bandwidth)dc to 80 MHz (100 Hz to 200 MHz) < 20 µVrms (30 kHz BW)80 MHz to 200 MHz (100 Hz to 500 MHz) < 65 µVrms (300 kHz BW)



VHF Continuous Waveform Source (VHFCW)Feature Specification

Peak output voltage (ac + dc) ±2.0 VPK into 50 Ohm Load

DC baseline range ±2.0 V into 50 Ohm Load


Output impedance 50 Ohm

Frequency range 1 M to 250 MHz

Frequency resolution 1 Hz

AC amplitude level range +16 to –31 dBm

AC amplitude level accuracy ±0.25 dB @ +10 dBm

2nd - 5th harmonic components –70 dBc (1 to 185 MHz)

Non-harmonic spurious –70 dBc (1 to 185 MHz)–60 dBc (185 to 250 MHz)



High Frequency Digitizer (HFD)Feature Specification




Capture memory size 1 M samples



Input impedance 50 Ohm, 10 kOhm

Lowpass filters 400 k, 2 M, 3.6 M, 6.1 M,10.0 MHz

Highpass filter 256 kHz

Differential phase (NTSC) + 0.5 degrees

Differential gain (NTSC) + 0.5%

Sinewave amplitude accuracy100 Hz to 1 MHz ±0.3 dB1 MHz to 5 MHz ±0.5 dB5 MHz to 9.5 MHz ±1.0 dB

2nd & 3rd harmonic components100 Hz to 1 MHz –60 dB1 MHz to 5 MHz –50 dB5 MHz to 9.5 MHz –45 dB

Noise density (bandwidth)100 Hz to 1 MHz (100 Hz to 5 MHz) 77 dB (30 kHz BW)1 MHz to 5 MHz (100 Hz to 10 MHz) 77 dB (30 kHz BW)5 MHz to 9.5 MHz (100 Hz to 10 MHz) 74 dB (30 kHz BW)



High Speed Sampler (HSS)Feature Specification


Waveform resolution 2 - 16 bits programmable

Maximum effective sample rate 100 GHz

Capture memory size (T_mem) 256 K samples

Capture memory size (DSI/O) 1 M samples

Input bandwidth dc to 1 GHz

Input impedance (selectable) 37.5, 50, 75, > 10 kOhm

Input capacitance < 5 pF

Settling time to ±1.5 mV of final value < 4 ns

Total noise (dc to 1 GHz) < 100 µVrms

Total harmonic distortiondc to 15 MHz –52 dB typicaldc to 40 MHz –47 dB typicaldc to 100 MHz –45 dB typical

Sweep window range 40 ns to 4 µs

Strobe repetition rate 1.3 µs



Advanced Time Measurement Subsystem (ATMS)Feature Specification

Timer/CounterTime measurements

Range No inherent limitsResolution <8 psAccuracy < 1 ns typicalTime base error 2 ppm max. over 1 year

operationEvent count

Range No limitResolution 1 countAccuracy ±1 count

Maximum count rate 100 MHzInput selection digital channels, analog

channels, dc channels,TMS channels, trigger bus

Multiple measurement memoryRange 2 to 1024 measurementsMinimum cycle time

High resolution <20 µsHigh speed <400 ns

Measurement modes Period, frequency, dutycycle, risetime, pulsewidthpropagation delay, event count,ratio count, time interval

Start/Stop enable systemPre/post counters

Range 0 to 16,777,215 countsResolution 1 countAccuracy ±0 countsMaximum Count Rate 100 MHz

Pre/post timersRange 0 to 134 msResolution 8 nsAccuracy ±10 ns

Analog Inputs (TMS and THADS)Input capacitance < 150 pF (TMS channel)Threshold specifications±6 V input range

Maximum operation ±6.4 VThreshold resolution 760 µV nominalInput amplifier noise (En) <4.0 mV rmsHysteresis Accuracy ±(20% + 3 mV)

±30 V input range (1 Meg input only)Maximum operation ±32.0 VThreshold resolution 3.8 mVHysteresis Accuracy ±(20% + 15 mV)


Advanced Time Measurement Subsystem (ATMS) (continued)Feature Specification

Analog Inputs (TMS and THADS) (continued)

±200 V input range (1 Meg input only)Maximum operation ±220.0 VThreshold resolution 38 mVHysteresis Accuracy ±(20% + 150 mV)



Time Jitter Digitizer (TJD)Feature Specification

Input channels 3 - analog2 - SSSP

Independent event selectorsA event from ch1, ch3, SSSP1 or SSSP2B event from ch1, ch3, SSSP1 or SSSP2E event from ch1, ch2, ch3, SSSP1 or

SSSP2

Independent time-stampers with independentevent enabling

Automatic enable after CPU ARMAfter A enable TSb to stamp an event after

TSa has stamped an eventAfter E enable TSa or TSb after an E

eventExternal enable TJD after external enable

signalSynchronous

A event enable TSa after a TSa input eventB event enable TSb after a TSb input event

Independent TSa and TSb stamp continuouslyand independently

Capture range 0 to 512 ns

Timing resolution 7.8 ps

Time stamp jitter <10 ps rms

Jitter plus linearity < 30 ps rms

Time stamp accuracy 1 ppm

Frequency measurement >350 MHz

Time stamp memory depth 16 k values per time stamper

Capture rate 27.8 MHz

Analog front-endRange ±10 V, ±2.5 VResolution 1.22 mV



MICROWAVE CONTINUOUS WAVEFORM SOURCE

Feature Specification

Frequency range 4.5 M to 4000 MHz

Frequency resolution4.5 MHz to 500 MHz 1 Hz500 MHz to 1000 MHz 2 Hz1000 MHz to 2000 MHz 4 Hz2000 MHz to 4000 MHz 8 HzOutput impedance 50 OhmLevel range +13 to –50 dBmLevel accuracy

absolute @ +10 dBm ±0.35 dB (4.5 to 50 MHz) ±0.25 dB (50 to 1300 MHz)±0.35 dB (1300 M to 3000 MHz)±0.45 dB (3000 M to 4000 MHz)

Level settling time < 2 ms to 0.02 dBFrequency settling time < 500 µs to 0.1 rad

Modulation modes CW, AM, FM, Phase, Pulse,0.3 GMSK, Pi/4DQPSK,Arbitrary (with optional IFModulated Source capability)

Frequency range w/modulation: 5 MHz to 180 MHz(with optional IF ModulatedSource capability)

SSB phase noise (@ offset from carrier)>-30 dBm output level

4.5 MHz to 1000 MHz -104 dBc @ 1 kHz-114 dBc @ 10 kHz-120 dBc @ 10 MHz

1000 MHz to 2000 MHz -98 dBc @ 1 kHz-118 dBc @ 10 kHz-114 dBc @ 10 MHz


SSB phase noise (@ offset from carrier)-30 dBm to -50 dBm output level

4.5 MHz to 1000 MHz -103 dBc @ 1 kHz-107 dBc @ 10 kHz-108 dBc @ 10 MHz




MICROWAVE CONTINUOUS WAVEFORM SOURCE (CONTINUED)Feature Specification

Harmonic Spurious (@ output power level)4.5 MHz to 1000 MHz -27 dBc @ 12-13 dBm

-27 dBc @ 11-12 dBm-29 dBc @ 10-11 dBm-29 dBc @ 5-10 dBm-29 dBc @ 0-5 dBm-30 dBc @ <0 dBm

1000 MHz to 2000 MHz -25 dBc @ 12-13 dBm-27 dBc @ 11-12 dBm-28 dBc @ 10-11 dBm-29 dBc @ 5-10 dBm-32 dBc @ 0-5 dBm-35 dBc @ <0 dBm

2000 MHz to 4000 MHz -30 dBc @ 12-13 dBm-31 dBc @ 11-12 dBm-32 dBc @ 10-11 dBm-33 dBc @ 5-10 dBm-35 dBc @ 0-5 dBm-35 dBc @ <0 dBm

Non-harmonic spurious4.5 MHz to 1000 MHz -54 dBc1000 MHz to 2000 MHz -50 dBc2000 MHz to 4000 MHz -46 dBc

Residual FM (in 300 Hz to 15 kHz BW)4.5 MHz to 1000 MHz <7 Hz1000 MHz to 2000 MHz <13 Hz2000 MHz to 4000 MHz <25 Hz

Output VSWR4.5 MHz to 1000 MHz <1.5:1 output, typical1000 MHz to 2000 MHz <1.7:1 output, typical2000 MHz to 3000 MHz <2.0:1 output, typical3000 MHz to 4000 MHz <2.2:1 output, typical



DC INSTRUMENTATION

DC Subsystem (V/l): 60 V/200 mA V/l SourcesFeature Specification

Voltage forcing accuracy (16-bit resolution; nominal)±200 V range ±(0.1% or 100 mV);

6.250 mV resolution100 V range ±(0.1% or 50 mV);



625.0 µV resolution10 V range ±(0.05% or 2.5 mV);



62.50 µV resolution1 V range ±1.0 mV;

31.25 µV resolution0.5 V range ±1.0 mV;

15.63 µV resolution

Voltage measuring accuracy (14-bit resolution; nominal)±200 V range ±(0.1% or 100 mV);

25 mV resolution100 V range ±(0.1% or 50 mV);



3.125 mV resolution10 V range ±(0.05% or 2.5 mV);



312.50 µV resolution1 V range ±1.0 mV;


62.50 µV resolution

Current forcing accuracy (12-bit resolution; nominal)±200 mA range ±(0.1% + 200 µA);

100 µA resolution20 mA range ±(0.1% + 20.0 µA);

10.0 µA resolution2 mA range ±(0.1% + 2.0 µA);

1.0 µA resolution


DC Subsystem (V/l): 60 V/200 mA V/l Sources (continued)Feature Specification

Current forcing accuracy (12-bit resolution; nominal) (continued)200 µA range ±(0.1% + 300 nA + 1 nA/V);

100 nA resolution20 µA range ±(0.1% + 120 nA + 1 nA/V);

10 nA resolution

Current measurinting accuracy (14-bit resolution; nominal)±200 mA ±(0.1% + 100 µA)

25 µA resolution100 mA ±(0.1% + 50 µA)

12.50 µA resolution50 mA ±(0.1% + 25 µA)

6.25 µA resolution20 mA ±(0.1% + 10 µA)

2.50 µA resolution10 mA ±(0.1% +5 µA)

1.25 µA resolution5 mA ±(0.1% + 2.5 µA)

625 nA resolution2 mA ±(0.1% + 1 µA)

250 nA resolution1 mA ±(0.1 % + 600 nA + 1 nA/V)

125 nA resolution500 µA ±(0.1% + 350 nA + 1 nA/V)

62.50 nA resolution200 µA ±(0.1 % + 200 nA + 1 nA/V)

25 nA resolution100 µA ±0.1% + 150 nA + 1 nA/V)

12.50 nA resolution50 µA ±(0.1% + 125 nA + 1 nA/V)

6.25 nA resolution20 µA ±(0.1 % + 110 nA + 1 nA/V)



625 pA resolution



DC Subsystem: DC Differential VoltmeterFeature Specification

Voltage metering accuracy (14-bit resolution; nominal)±200 V range ±(0.1% or 100 mV);

25 mV resolution100 V range ±(0.1% or 50 mV);




1.563 mV resolution5 V range ±(0.05% or 1.0 mV); ␣ ␣ ␣ ␣1 V range ±1.0 mV;


62.50 µV resolutionCommon mode rejection ratio 80 dB @ dcMaximum allowable voltage ±65 V dc to ground

Sample and differenceGain x1, x10, xl00 measured rangeAccuracy

Xl, X10 ±(0.5% + 0.1% F.S.)X100 ±(l.0% + 1.0% F.S.)



Analog Pin Unit (APU)Feature Specification

APU per-pin architectureNumber of pins 48 pins maximum

2 head multiplexMatrix access 8 lines per APUController MC68000 microprocessor

per group of 24 APUsMemory per 24 pins 4,096 locations x 12 bits

APU functions/modesFunctions/modes Force V, Measure I

Force I, Measure VMaximum operating voltage ±24 VMaximum operating current ±30 mA

Voltage forcing accuracy (12-bit resolution; nominal)2 V range ±(0.1% + 1.5 mV);

1.00 mV resolution5 V range ±(0.1% + 3.7 mV);


5.00 mV resolution24 V range ±(0.1% + 18 mV);

12.00 mV resolution

Voltage measuringSystem A/D converter accuracy (14-bit resolution; nominal)2 V range ±(0.1% + 1.2 mV);

250 µV resolution5 V range ±(0.1% + 3.0 mV);

625 µV resolution10 V range ±(0.1% + 6.0 mV);


3.00 mV resolution

Voltage measuringLocal A/D converter accuracy (12-bit resolution; nominal)2 V range ±(0.1% + 2.8 mV);




12.00 mV resolution


Analog Pin Unit (APU) (continued)Feature Specification

Current forcing accuracy (12-bit resolution; nominal)200 µA range ±(0.1% + 0.3 µA + 2 nA/V);

100 nA resolution1 mA range ±(0.1% + 1.1 µA);


2.50 µA resolution30 mA range ±(0.1% + 30.0 µA);

15.0 µA resolution

Current measuringSystem A/D converter accuracy (14-bit resolution; nominal)2 µA range ±(0.5% + 110 nA + 1 nA/V);

0.25 nA resolution10 µA range ±(0.2% + 110 nA + 1 nA/V);


6.25 nA resolution200 µA range ±(0.1% + 0.25 µA + 2 nA/V);




3.75 µA resolution

Local A/D converter accuracy (12-bit resolution; nominal)2 µA range ±(0.5% + 110 nA + 1 nA/V);



25 nA resolution200 µA range ±(0.1% + 0.4 µA + 2 nA/V);


0.5 µA resolution5 mA range ±(0.1% + 7.5µA);

2.5 µA resolution30 mA range ±(0.1% + 45 µA);

15 µA resolution



Advanced Analog Pin Unit (AAPU)Feature Specification

AAPU per-pin architectureNumber of pins 68 pins maximum

2 head multiplexMatrix access 8 lines per AAPUController Custom gate array controller

per group of 4 AAPUs

AAPU voltage measure mode (high-Z) Force V, Measure IForce I, Measure V

Maximum operating voltage ±30 VMaximum operating current ±30 mAProgrammable current clamp (Force V mode) ±30 mAProgrammable voltage clamp (Force I mode) ±30 V

Voltage forcing accuracy (14-bit resolution; nominal)2 V range ±(0.1% + 1.5 mV);



1.25 mV resolution30 V range ±(0.1% + 18 mV);

3.75 mV resolution

Voltage measuringSystem A/D converter accuracy (14-bit resolution; nominal)2 V range ±(0.1% + 1.5 mV);




3.75 mV resolution

Current forcing accuracy (14-bit resolution; nominal)200 µA range ±(0.1% + 0.25 µA + 1 nA/V);


0.125 nA resolution5 mA range ±(0.1% + 4.0 µA);

0.625 nA resolution30 mA range ±(0.1% + 24.0 µA);

3.75 nA resolution

Current measuring (14-bit resolution; nominal)2 µA range ±(0.5% + 110 nA + 1 nA/V);



6.25 nA resolution


Advanced Analog Pin Unit (AAPU) (continued)Feature

Specification

Current measuring (14-bit resolution; nominal)200 µA range ±(0.1% + 0.3 µA + 1 nA/V);



625 nA resolution30 mA range ±(0.1% + 30 µA);

3.75 µA resolution



High Current Unit (HCU)Feature Specification

Voltage forcing ±30 V (14-bit resolution)2 V range

Resolution 250 µVAccuracy ±(0.1% +1.5 mV)

30 V rangeResolution 3.75 mVAccuracy ±(0.1% +15 mV)

Current forcing ±2 A (12-bit resolution)20 mA range

Resolution 5 µAAccuracy ±(0.1% + 20 µA)

200 mA rangeResolution 50 µAAccuracy ±(0.1% + 200 µA)

2 A rangeResolution 500 µAAccuracy ±(0.2% + 2 mA)

Current measuring ±2 A (14-bit resolution)20 mA range

Resolution 5 µAAccuracy ±(0.1% + 20 µA)

200 mA rangeResolution 50 µAAccuracy ±(0.1% + 200 µA)

2 A rangeResolution 500 µAAccuracy ±(0.2% + 2 mA)



Quad Power V/I (QPVI)Feature Specification

Four independent 50 V/30 A floating supplies that can be serially stacked for higher voltages oroperated in parallel for higher currents

Two-/Four-quadrant operation with voltage polarity switching (I and IV or II and III)

Modulation support for duty cycle and pulse mode

Fully floating to ±300 V to ground

ZOUT = Low for 0 V when gated off, or ZOUT = High for 0 A when gated off

Voltage forcingRanges 2 V, 10 V, 50 VResolution 11 bits plus sign

Voltage meteringRanges 2 V, 10 V, 50 VResolution 13 bits plus sign

Current forcingRanges 40 mA, 200 mA, 1 A, 5 A, 30 AResolution 11 bits plus sign

Current meteringRanges 40 mA, 200 mA, 1 A, 5 A, 30 AResolution 13 bits plus sign


Quad Op Amp Loop (QOA)Feature Specification

Number of parallel Op Amps 4

Selectable loop gain polarity

Loop gain settings 100, 1000, 10000

VOS measurementRanges ±970 nV to ±99 mVAccuracy

Gain of 100 0.25% of settingGain of 1,000 0.25% of settingGain of 10,000 0.5% of setting

Output load resistors 600, 2 k, 10 kOhm

Oscillation detector threshold 20 mV to 3.32 V, programmable

Commutation 256 time slots driven by one of eighttrigger bus lines



Low Current Ammeter (LCA)Feature Specification

Number of parallel measurements 8

Resistive mode accuracy10 uA range ±1.5% of reading ±50 nA1 µA range ±1.5% of reading ±5 nA100 nA range ± 2.0% of reading ±500 pA

Integrate mode measurement accuracy10 nA range (1 power line cycle) ±2.0% of reading ±50 pA1 nA range (1 power line cycle) ±2.5% of reading ±5 pA

+ Fixture error100 pA range (1 power line cycle) ±3.5% of reading ±2 pA

+ Fixture error10 pA range (10 power line cycle) ±3.5% of reading ±2 pA

+ Fixture error



Pulse DriverFeature Specification

Pulse settingsDelay and width ranges 100 ns, 400 ns, 1.6 µs, 6.4 µs, 25 µs,

100 µs, 400 µs, 1.6 ms, 4 ms

RF output channel performanceImpedance 50 OhmRise time (10 V swing) < 15 nsSettling time @ 1% < 50 nsMaximum unloaded swing ±5.5 V

Pogo output channel performanceImpedance 95 OhmRise time (selectable) (20 V swing) 35 ns, 85 nsSettling time @ 1% (selectable) < 100 ns, < 250 nsMaximum unloaded swing ±11 V



Precision Multimeter (PMM)Feature Specification

DC voltage measurement1.0 dc Volts; 1.1 accuracyUnits are ppm of reading + ppm of range.Specifications are for 100 periodic line cycles.

100 mV range 2.5 + 85; typical, 24 hours3.5 + 90; 90 day

1 V range 1.5 + 8.5; typical, 24 hours3.1 + 9; 90 day

10 V range 0.5 +0.85; typical, 24 hours2.6 +1; 90 day

100 V range 2.5 + 0.38; typical, 24 hours4.5 + 0.38; 90 day

DC current measurement2.0 dc current; 2.1 accuracyUnits are ppm of reading + ppm of range, unless otherwise noted.Specifications are for 100 periodic line cycles.

100 nA range 10 +3; typical, 24 hours30 + 3; 90 day

1 µA range 10 + 0.3; typical, 24 hours15 + 0.3; 90 day

10 µA range 10 + 300; typical, 24 hours15 + 310; 90 day

100 µA range 10 + 35; typical, 24 hours15 + 38; 90 day

1 mA range 10 + 6; typical, 24 hours15 + 8; 90 day

10 mA range 10 + 3.3; typical, 24 hours15 + 5.3; 90 day

100 mA range 25 + 3; typical, 24 hours30 + 5; 90 day

1 A range 100 + 10; typical, 24 hours100 + 10; 90 day

Resistance measurement accuracyUnits are ppm of reading + ppm of rangeSpecification applies for measurements over 100 periodic line cycles.

4-Wire mode10 Ohm range 6 + 3; typical, 24 hours

16 + 5; 90 day100 Ohm range 9 + 3; typical, 24 hours

16 +5; 90 day1 kOhm range 8 + 0.2; typical, 24 hours

14+ 0.5; 90 day10 kOhm range 62 + 0.2; typical, 24 hours

68 + 0.5; 90 day100 kOhm range 120 + 0.2; typical, 24 hours

130 + 0.5; 90 day


Precision Multimeter (PMM) (continued)Feature Specification

Resistance measurement accuracyUnits are ppm of reading + ppm of rangeSpecification applies for measurements over 100 periodic line cycles.

2-Wire mode1 MOhm range 610 + 8; typical, 24 hours

610 + 9; 90 day10 MOhm range 0.6% + 5.7; typical, 24 hours

0.6% + 11; 90 day100 MOhm range 0.65% + 10; typical, 24 hours

0.65% + 10; 90 day1 GOhm range 1.1 % + 10; typical, 24 hours

1.1 % + 10; 90 day

AC voltage measurement accuracyUnits are % of reading + % of range - for inputs 1/20th F.S. rms to F.S. rms

Range 10 - 20 Hz 20 - 40 Hz 40 Hz - 1 kHz 1 - 20 kHz1 V 0.117 + 0.024 0.041 + 0.01 0.022 + 0.0034 0.029 + 0.003410 V 0.117 + 0.024 0.041 + 0.01 0.022 + 0.0034 0.029 + 0.0034100 V 0.13 + 0.024 0.054 + 0.01 0.036 + 0.004 0.036 + 0.015

Range 20 - 50 kHz 50 - 100 kHz I00 - 200 kHz 200 - 300 kHz1 V 0.1 + 0.004 0.5 + 0.01 2 + 0.03 3.5 + 0.0510 V 0.1 + 0.004 0.5 + 0.006 2 + 0.03 3.5 + 0.06100V 0.12 + 0.025 0.56 + 0.012 2 + 0.12 3.5 + 0.12

Range 300 - 400 kHz 400 - 500 kHz1 V 5.5 + 0.05 8.5 + 0.0510 V 5.5 + 0.06 8.5 + 0.06100 V 5.5 + 0.12 8.5 + 0.12



Precision Reference SourceFeature Specification

Voltage Range ±11.0 V

Voltage Resolution 17 Bits, 168 µV

Noise over 20 kHz Bandwidth < 20 µVrms

Settling Time to 1 ppm of Final Value < 2 ms



SYNCHRONIZED POWER INSTRUMENTATION

High Current Current Source (HCCS)Feature Specification

HCCS functions/modes

100 A/30 V current source - A current source with programmable voltage clamp

100 A/100 V current load - A current load with programmable voltage clamp

Floating for high-side applications

Force zero volts for short circuit testing

Independent voltage and current measuring

Trigger Bus control for gate signal

Two-station multiplexed via High Power Matrix (HPM)

Current source mode accuracy (nominal resolution)Range1 A ±(0.5% + 5 mA)

30.5 µA resolution5 A ±(0.5% + 12.5 mA)

152.5 µA resolution10 A ±(0.5% + 25 mA)

305 µA resolution100 A ±(0.5% + 250 mA)

3.05 mA resolution

Settling time (non-reactive load)

Compliance Points30 V Range DC 100 ms 1 msSource 25 V/15 A 17 V/50 A 14 V/100 A-30 V Range DC 100 ms 1 msLoad -25 V/15 A -17 V/50 A -14 V/100 A

To specification < 500 µsat 100 µs ±3% of final value

Current measuring accuracyNote: Resolution is that of the instrument used on the Measure Bus,typically system dc voltmeterRange

1 A ±(0.5% + 5 mA)5 A ±(0.5% + 12.5 mA)10 A ±(0.5% + 25 mA)100 A ±(0.5% + 250 mA)


High Current Current Source (HCCS) (continued)Feature Specification

Voltage measuring accuracyNote: Resolution is that of the instrument used on the Measure Bus,typically system dc voltmeterRange

100 V ±(0.5% + 100 mV)20 V ±(0.5% + 20 mV)10 V ±(0.5% + 10 mV)2 V ±(0.5% + 5 mV)

Voltage ClampingRange

100 V ±(l.5% + 1.0 V) + (1.5 V*(Iactual/Irange)

Resolution 12.5 mV



High Current Voltage Source (HCVS)Feature Specification

HCVS functions/modes120 V/100 A - A voltage source with programmable current clampFloating for negative supply applicationsAutomatic crossover to power sinking quadrant for capacitive dischargeIndependent voltage and current measuringTrigger Bus control for gate signalTwo-station multiplexed via High Power Matrix (HPM)

Compliance (<10% duty cycle)V Range DC 10 ms 1 ms30 V 25 V/12 A 15 V/50 A 12 V/100 A60 V 50 V/6 A 40 V/40 A 45V/65 A90 V 80 V/3 A 70 V/20 A 75 V/40 A120 V 110 V/2 A 100 V/12 A 110 V/25 A

Voltage forcing accuracyRange30, 60, 90, 120 V ±(0.5% + 150 mV)Resolution 1.83 mV (nominal)

Settling time (non-reactive load)To specification < 500 µsat 100 µs ±3% of final value

Voltage measuring accuracyRange

150 V ±(0.5% + 150 mV)

Current measuring accuracyRange

100 A ±(1.0% + 250 mA)10 A ±(1.0% + 25 mA)1 A ±(1.0% + 5 mA)



High Power V/l (HPVI)Feature Specification

High Power V/I Functions/Modes

750 V/10 A - A voltage source with programmable current clamp

750 V/10 A - A current source with programmable voltage clamp

Floating for negative supply applications

Automatic crossover to power sinking quadrant for capacitive discharge

Independent voltage and current measuring

Trigger Bus control for gate signal

Two-station multiplexed via High Power Matrix (HPM)

Compliance points (<10% duty cycle. 40% F.S. <VOUT <F.S.)VRange DC 100 ms 10 ms 1 ms85 V 4.0 A 8.0 A 10.0 A 10.0 A170 V 2.0 A 5.0 A 7.0 A 10.0 A225 V 1.4 A 4.0 A 4.5 A 8.5 A340 V 1.0 A 3.5 A 4.0 A 7.0 A510 V 700 mA 2.0 A 2.2 A 4.2 A750 V 500 mA 1.9 A 2.0 A 3.5 A

Voltage forcing accuracyRange

85 V ±(0.5% + 250 mV)6.25 mV resolution




510 V ±(l.0% + 1.0 V)12.5 mV resolution

750 V ±(1.0% + 1.0 V)12.5 mV resolution

Voltage forcing settling time (non-reactive load)To specification <500 µsat 100 µs ±3% of final value

Voltage measuring accuracyRange

800 V ±(0.5% + 1.0 V)


High Power V/l (HPVI) (continued)Feature Specification

Current forcing accuracyRange; V Range100 mA; 510 V, 750 V ±(l.5% + 1 mA)

25 µA resolution100 mA; 85– 340 V ±(l.5% + 2 mA)

50 µA resolution10 A; 510 V, 750 V ±(l.5% + 25 mA)

2.5 mA resolution10 A; 85 –340 V ±(3.0% + 50 mA)

5 mA resolution

Current forcing settling time (non-reactive load)To specification < 1 msat 100 µs ±3% of final value

Current measuring accuracyRange

10 A ±(l.0% + 12.5 mA)1 A ±(l.0% + 8.5 mA)100 mA ±(l.0% + 125 µA)10 mA ±(l.0% + 85 µA)1 mA ±( 1.5% + 2 .0 µA)100 µA ±( 1.5% +2.0 µA)



High Power Matrix (HPM)Feature Specification

HPM Functions/ModesFour lines (two instruments) by 12 pinsTwo high current lines (10 A per pin)Two medium current lines (5 A per pin)1,000 V operating voltageGuarded Kelvin connections (force, sense, guard)Parallel pins for currents up to 80 A pulsedPer-pin access to low power matrix for dc parametricsCrowbar protection for dc matrix connectionsSeparate series and parallel access for HV AmmeterUp to 2 HPMs (24 hp pins) per SP card cageTwo-station multiplexed

High Current Lines (1 & 2)Pulsed current is defined as <10 ms and <10% duty cycleMaximum current per pin, dc, not switched 10 AMaximum current per pin, switched 1 AMaximum current per pin, pulsed 20 AMaximum current per line, dc 40 AMaximum current per line, pulsed 80 A

Medium Current Lines (3 & 4)Pulsed current is defined as <10 ms and <10% duty cycleMaximum current per pin, dc, not switched 5 AMaximum current per pin, switched 1 AMaximum current per pin, pulsed 10 AMaximum current per line, dc 20 AMaximum current per line, pulsed 40 A

Maximum VoltageAll nodes, non switching 1,000 V

DC Matrix InterfaceMaximum current 1 AMaximum voltage (crowbar off) ±200 V (nominal)Maximum voltage (crowbar on) ±60 V (nominal)Maximum leakage (crowbar off) ±l µA (typical)Maximum leakage (crowbar on) ±10 µA (typical)



High Voltage Ammeter (HVA)Feature Specification

HVA Functions/Modes1 µA to 100 mA current rangesFloating 1,400 V for high-side measurements (pin to pin)High Power Matrix outputTwo-station multiplexed

HVA ConnectionsHP Matrix connections In series with line 4;

In parallel with lines 1 & 2

Current Measuring Accuracy (14 bits nominal)Note: Resolution is that of the instrument used on the Measure Bus,typically system dc voltmeterRange

100 mA ±(0.2% + 120 µA)10 mA ±(0.2% + 12 uA)1 mA ±(0.2% + 1.2 µA)100 µA ±(0.2% + 120 nA)10 µA ±(0.2% + 30 nA)1 µA ±(0.5% + 20 nA)



Breakdown Voltage Current Source (BVCS)Feature Specification

Forcing current source accuracyRange

10 µA ±(0.5% + 50 nA)305 pA resolution (nominal)

100 µA ±(0.5% + 500 nA)3.05 nA resolution (nominal)

1 mA ±(0.5% + 5 µA)30.5 nA resolution (nominal)

10 mA ±(0.5% + 50 µA)305 nA resolution (nominal)

Maximum programmable output currentBVCS as current source 10 mA

Maximum programmable output voltageHigh power V/I as voltage supply 750 VHigh voltage source as voltage supply 800 V

Voltage measurement accuracyRange

50 V ±0.5% + 0.50 V)200 V ±(0.5% + 1.00 V)1000 V ±0.5% + 1.25 V)

Output resistance (Rout)Irange = 10 mA 249.7 OhmsIrange = 1 mA 453.5 OhmsIrange = 100 µA 493.8 OhmsIrange = 10 µA 498.3 OhmsIrange = 1 µA 498.8 Ohms

Maximum programmable output voltageHigh power V/I as voltage supply 750 VMaximum programmable output current 10 mA

Current measurement accuracy (% of reading + offset)Range

1 µA ±(0.5% + 10 nA)10 µA ±(0.5% + 50 nA)100 µA ±(0.5% + 500 nA)1 mA ±(0.5% + 5 µA)10 mA ±(0.5% + 50 µA)

Ammeter settling time <100 µs typicalMaximum allowable current 10 mA



Figures & Tables

FIGURE CONTENT/TITLE PAGE

A585 Advanced Mixed-Signal Test System ....................................................................................... 6A575 Advanced Mixed-Signal Test System ....................................................................................... 6A565 Advanced Mixed-Signal Test System ....................................................................................... 6

1 Block Diagram of a DSP programmable filter with 256 filter selections ............................................. 82 The Evolution of the A500 Family and the A585/A575/A565 Series of Advanced Mixed-Signal… ... 93 Digital mixed-signal test system architecture ................................................................................... 104 Analog mixed-signal test system architecture ................................................................................... 115 Evolution of analog/analog-with-digital/mixed-signal test ................................................................ 146 The A585/A575/A565 series Vector Bus III architecture ................................................................... 167 TimeMaster Clock Synchronization ................................................................................................ 178 Mixing of SCAN, pattern and digital signal data selected per pin .................................................... 189 Vector Bus III delivers the Mixed-Signal Microcodes directly to the analog instrument… ............... 1910 Mixed-signal microcode provides Vector-Locking between the analog and digital instrumentation . 2011 The Mixed-Signal Microcode is programmed in the digital pattern to control the analog…............. 2112 The A585 can perform synchronous and asynchronous testing using a dual Vector Bus system ....... 2213 MultiSync TimeGen provides multiple clocks and two independent time domain systems for… ... 2314 MultiState Memory Store provides high-speed reload of timing and dc attributes of digital pins… . 2415 The Universal Bus Architecture ...................................................................................................... 2516 When the device dissipates substantial power, thermal effects can alter its measurements .............. 2617 The Universal Bus Architecture has two timing elements — the Trigger Bus and the… ................. 2618 The Trigger Bus provides well-controlled, repeatable power testing by connecting the timing….... 2719 Universal Bus Architecture measurement bus allows shared metering. ............................................ 2820 SUN/A500 family networking ......................................................................................................... 3121 IMAGE Answers on-line documentation ........................................................................................ 3322 IMAGE production environment .................................................................................................... 3423 IMAGE station window with sequencer .......................................................................................... 3624 IMAGE station window with trap and menu ................................................................................... 3725 Debug displays ................................................................................................................................ 3826 Pattern debugger showing column operation ................................................................................... 3927 Digital pattern debug window ......................................................................................................... 4028 Digital Pattern Advanced Logic Analyzer ........................................................................................ 4129 Digital waveshape tools – spec table window ................................................................................... 4230 Digital waveshape tools – timing table window ............................................................................... 4331 Waveform displays for time and frequency domain .......................................................................... 4432 Wafer map ....................................................................................................................................... 4533 Data analysis tools - histogrammer, datalog, summary report ............................................................ 4634 Shmoo Plot ...................................................................................................................................... 4735 3-D Shmoo Plot ............................................................................................................................... 4736 CATD tools – ProGen, IMAGE ExPress ........................................................................................ 4837 Smith Chart and VectorScope .......................................................................................................... 4938 Test development – today vs tomorrow ........................................................................................... 5139 IMAGE ExChange ......................................................................................................................... 5240 DataScope ....................................................................................................................................... 5241 Design Insight – This N Trend Plot shows the effect of changes in voltage (VCC) and… ............... 5342 Test Insight – The Mean and Sigma Shift report compares two lots and shows which tests… ......... 5443 Wafer Insight – The Analog Parametric Map shows each die as a box whose size is… ..................... 5544 Production Insight – This Test Mean Trend Plot tracks the mean of four tests over several… ......... 5645 ATE Logger – The Activity Times Report is a timeline that displays the changing state of… ......... 5746 The A585 Vector Bus provides multiple memory types behind each digital pin .............................. 5947 Easy to use mnemonics define the data behind each digital pin ...................................................... 6048 Digital Signal I/O sends and receives the digital representation of analog signals within pattern ...... 6149 The Smem controller can control up to 512 different waveform segments that can be linked,… ..... 6250 The Digital Signal I/O is programmable to any device pin ............................................................... 63


Figures & Tables

FIGURE CONTENT/TITLE PAGE

51 Multiple Digital Signal I/Os are available to each digital pin using the Alternate Data Bus .............. 6452 Six edges/pin can generate data in each 20 ns vector cycle ............................................................... 6653 Time sets provide an indirect addressing capability to the edge set offering maximum… ................ 6854 With edge masking, a compare window can be opened over multiple vector cycles ......................... 6955 There are 29 drive and compare formats available on the A585 Advanced Mixed-Signal… ............. 7056 The Digital Channel Card provides access to all functions such as dc matrix, … ............................. 7157 The Superclock option provides a synchronized 400 MHz clock source for high-speed… ............... 7258 Super Speed Serial Pin Channel Card option ................................................................................... 7359 A full spectrum of high performance analog instruments ranging from precision dc to… ................. 7460 The architecture of the memory-based analog instruments is very similar to the VLSI… ................ 7561 Smem controller generating a video line. Looping on this series of subroutines generates a… ......... 7662 A variety of mixed-signal microcode commands control switching between waveforms… ............... 7763 The Precision Low Frequency Source (PLFS) analog channel card provides access… ................... 7864 The Precision Low Frequency Source instrument provides ultra-low distortion performance… ..... 7965 The Precision Low Frequency Digitizer includes sample memory, Vector Bus and conversion… ... 8066 The Low Frequency AC Source ..................................................................................................... 8167 The Low Frequency AC Digitizer .................................................................................................. 8268 The Very High Frequency Arbitrary Waveform Generator produces signals for disk drive… ........... 8369 The High Frequency Digitizer analyzes performance of devices such as video, disk drive,… ......... 8470 The VHFCW Source is an excellent input source for measuring linearity performance of… ........... 8571 The High Speed Sampler captures very high speed waveforms ...................................................... 8672 VHF Measure Module .................................................................................................................... 8773 The Time Jitter Digitizer measures elapsed time between two events for direct measurement… .. 8874 Pulse width measurement using Time Jitter Digitizer ..................................................................... 8975 Mixed-Signal Microwave Test Capability ........................................................................................ 9076 The A585 series dc matrix provides every device pin with APUs and standard dc instruments. … .. 9277 A full spectrum of V/I instruments address the most demanding applications .................................. 9378 The Advanced Analog Pin Unit ....................................................................................................... 9479 A single Op Amp Loop testing one component. Three wires are the only required connections. .... 9580 The Low Current Ammeter tests eight device pins in parallel. ........................................................ 9681 Multiple output channels are provided for the pulse driver. ............................................................. 9782 All power instruments can be two station multiplexed and interfaced to the Universal Bus… ......... 9883 The High Power Matrix extends the standard system matrix and provides the ability for… ............ 9984 Direct-docking test head layout with a typical channel card configuration. .................................... 10285 Exploded view of the A585 Series Advanced Mixed-Signal test head elements. ........................... 10386 The Configuration Board carries the required signals for all the instruments. ................................. 10487 The Teradyne patented Iso-Pins deliver full instrument performance in a shielded… .................. 10488 PATH II test head layout with typical channel card configuration .................................................. 10589 The PATH II cable interface easily connects to test floor equipment like the Tokyo Seimitsu … . 10690 PATH II Configuration Board installed in an A585/A575 Advanced Mixed-Signal Test Head… ... 10791 A585 Footprint .............................................................................................................................. 10892 A575 Footprint .............................................................................................................................. 10993 A565 Footprint .............................................................................................................................. 110

Tables:

1 Example of actual syntax for device pinmap .................................................................................... 352 Tester per-pin architecture ............................................................................................................... 583 Pattern microcodes available in the digital sequence control module ............................................... 654 Feature and Specification Comparison among the A585/A575/A565 Series Test Systems .............. 112

series of advanced mixed-signal test systemsa565 series of advanced mixed-signal test systems...

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