Serial Peripheral Interface

What is SPI?

o Serial Bus protocol

o Fast, Easy to use, Simple

o Everyone supports it

o A communication protocol using 4 wires

o Also known as a 4 wire bus

o Used to communicate across small distances

o Multiple Slaves, Single Master

o Synchronized o Full Duplex

Protocol

Wires:

Master Out Slave In (MOSI)‏

Master In Slave Out (MISO)‏

System Clock (SCLK)‏

Slave Select 1…N

Master Set Slave Select low

Master Generates Clock

Shift registers shift in and out data

Wires in Detail

MOSI – Carries data out of Master to Slave

MISO – Carries data from Slave to Master

(Both signals happen for every transmission)

SS_BAR – Unique line to select a slave

SCLK – Master produced clock to synchronize data transfer

Master shifts out data to Slave, and shift in data from Slave

Serial Peripheral Interface (SPI)

Data is shifted out of the master's MOSI pin and in its MISO pin Data transfer is initiated by simply writing data to the SPI data register. All data movement is coordinated by SCK. Slave select may or may not be used depending on interfacing device.

slave SPI device master SPI device

Master and multiple independent slaves

Master and multiple daisy-chained slaves

Data Transmission Mode

data order: if set, LSB is transmitted first

interrupt enable: if set, interrupt occurs when SPI interrupt flag and global interrupt enable are set

spi enable: if set, SPI interface is enabled

master/slave select: if set, SPI in master mode

clock polarity: '0' SCK low in idle '1' SCK high in idle

clock phase: '0' leading edge sample, trailing edge setup '1' leading edge setup, trailing edge sample

clock rate

SPI2X SPR1 SPR0 SCLK 0 0 0 fosc/4 0 0 1 fosc/16 0 1 0 fosc/64 0 1 1 fosc/128 1 0 0 fosc/2 1 0 1 fosc/8 1 1 0 fosc/32 1 1 1 fosc/64

(in SPSR)

SPI Control Register (SPCR)

interrupt flag: set when serial transfer is complete

write collision: set if SPDR is written during a receive transfer

2x clock rate: if set, doubles clock rate in master mode

reserved bits

SPI Status Register (SPSR)

SPI Data Register (SPDR)

SPDR is a read/write register used for data transfer. Writing SPDR sends data out MOSI. Reading SPDR gets the data that was clocked into MISO.

Configuration

SPI can be configured as MASTER or SLAVE

Here is described how to configure in MASTER/SLAVE

The following sequence describes how one should process a data transfer with the SPI block when it is set up to be the master.

The process assumes that any prior data transfer has already completed.

Configuration-MASTER operation

Configuration-MASTER operation

1. Set the SPI clock counter register to the desired clock rate.

2. Set the SPI control register to the desired setting.

3. Write the data to transmit to the SPI data register . This write starts the SPI data transfer.

Configuration-MASTER operation

4. Wait for the SPIF bit in the SPI status register to be set 1 . The SPIF bit will be set after the last cycle of SPI data transfer .

5. Read the SPI status register.

6. Read the received data from the SPI data register(optional).

7. Go to step 3 if more data is required transmit .

Configuration-MASTER operation

A read or write of the SPI data register is required in order to clear the SPIF status bit.

Therefore , if the optional read of the SPI data register does not take place ,a write to this register is required in order to clear the SPIF status bit

Configuration-MASTER operation Note:

The following sequence describes how one should process a data transfer with the SPI block when it is set up to be the SLAVE.

The process assumes that any prior data transfer has already completed.

Configuration-SLAVE operation

1. Set the SPI control register to the desired settings.

2. Write the data to transmit to the SPI data register .Note : This can only be done when a slave SPI data transfer is not in progress.

Configuration-SLAVE operation

3. Wait for the SPIF bit in the SPI status register to be set 1 . The SPIF bit will be set after the last sampling clock edge of SPI data transfer .

4. Read the SPI status register.

Configuration-SLAVE operation

Configuration-SLAVE operation

5. Read the received data from the SPI data register(optional).

6. Go to step 2 if more data is required transmit .

Configuration-SLAVE operation Note:

A read or write of the SPI data register is required in order to clear the SPIF status bit.

Therefore , at least one of the optional reads or writes of the SPI data register must take place ,in order to write to clear the SPIF status bit

Pros and Cons: Pros:

Fast and easy

Fast for point-to-point connections

Easily allows streaming/Constant data inflow

No addressing/Simple to implement

Everyone supports it

Cons:

SS makes multiple slaves very complicated

No acknowledgement ability

No inherent arbitration

No flow control