semiconductor memory test time reduction and automatic generation of flash memory built-in self-test...
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Semiconductor Memory Test Semiconductor Memory Test Time Reduction and Automatic Time Reduction and Automatic
Generation of Flash Memory Generation of Flash Memory Built-in Self-Test CircuitsBuilt-in Self-Test Circuits
Adviser: Prof. Cheng-Wen WuAdviser: Prof. Cheng-Wen Wu
Student: Shyr-Fen kuoStudent: Shyr-Fen kuo
May 13, 2004May 13, 2004
Adviser: Prof. Cheng-Wen WuAdviser: Prof. Cheng-Wen Wu
Student: Shyr-Fen kuoStudent: Shyr-Fen kuo
May 13, 2004May 13, 2004
Laboratory for Reliable Computing (LaRC)
Electrical Engineering Department
National Tsing Hua University
Laboratory for Reliable Computing (LaRC),2004
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OutlineOutlineOutlineOutline1. Introduction
2. Memory Test Time Reduction Method
3. Automatically Memory Test Time Reduction
4. Experimental Results
5. Proposed Flash Memory BIST Architecture
6. Flash Memory BIST Generator
7. Experimental Results
8. Conclusions and Future Work
Laboratory for Reliable Computing (LaRC),2004
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IntroductionIntroductionIntroductionIntroduction Memory plays an increasingly importance role for
System-on-Chip (SOC), not only RAM but flash memories are also including
The growing of density and capacity of memory More test time to finish full test flow More design-for-testability (DFT) circuits to speed
up the test time
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Memory Test Time Reduction (TTR)Memory Test Time Reduction (TTR)Memory Test Time Reduction (TTR)Memory Test Time Reduction (TTR) Complex test flow and a lot of test patterns
In industry, statistical techniques are usually applied to TTR
Wafer Sort 1
Bake
Wafer Sort 2
Wafer Sort 3 (HT)
Packing
Shipment
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Memory Built-in Self-Test (BIST)Memory Built-in Self-Test (BIST)Memory Built-in Self-Test (BIST)Memory Built-in Self-Test (BIST) Automatic generation of memory BIST circuit
RAM: BRAINS Flash: ??
Reusing RAM controller
Designing and testing easily
Flash memory
RAM
TPG
TPGSequenceController
Sequence
Laboratory for Reliable Computing (LaRC),2004
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OutlineOutlineOutlineOutline1. Introduction
2. Memory Test Time Reduction Method
3. Automatically Memory Test Time Reduction
4. Experimental Results
5. Proposed Flash Memory BIST Architecture
6. Flash Memory BIST Generator
7. Experimental Results
8. Conclusions and Future Work
Laboratory for Reliable Computing (LaRC),2004
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Specification(pins, timing,
functions)
Test item (test pattern, test
time)
Specialfunction
(description)
Device behavior
(description)
Automatic Test Time Reducing Kernel
Repeated test patterns/items
Partial test patterns alike
Correlative target failure
Using Engineering test mode or special function
Modified test patterns
Repeated test pattern or test item
Partial similar test
pattern
Correlative target failure
Suggested test pattern
Employed test mode/
function
Original test
item list
Suggested test item list
Proposed Memory TTR FlowProposed Memory TTR FlowProposed Memory TTR FlowProposed Memory TTR Flow
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Partial test pattern alike Finding the similar actions Understanding the behavior of test operations
Repeat test patterns/items Reducing test operations in test patterns Merging test patterns which have similar actions
Modified test patterns Simulating the fault coverage of test patterns Developing new test patterns
Memory TTR Method (Phase 1)Memory TTR Method (Phase 1)Memory TTR Method (Phase 1)Memory TTR Method (Phase 1)
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Repeated Test Patterns/ItemsRepeated Test Patterns/ItemsRepeated Test Patterns/ItemsRepeated Test Patterns/Items
rbwb
TestonPower
wbrawarbwbwarbwbrawa
TestFunctional
,0000
:
),(,,,),,(,,,0000
:
wbrawawbwbwarbwbrawa ,,,,,,,,,0000
Merged test patterns
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Modified Test PatternsModified Test PatternsModified Test PatternsModified Test Patterns
rbwbrawarbwbrawarbwbrawa
TestMarchN
wbrawarbwbwarbwbrawa
wbrawarbwbwarbwbrawa
wbrawarbwbwarbwbrawa
wbrawarbwbwarbwbrawa
wbrawarbwbwarbwbrawa
TestMarchN
wbholdrawaholdrbwbwaholdrbwbholdrawa
Testtention
,,,,,,,,,,,0000
:12
,,,,,,,,,8888
,,,,,,,,,4444
,,,,,,,,,2222
,,,,,,,,,1111
,,,,,,,,,0000
:10
,,,,,,,,,,,,,0000
:Re
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Developed New Test PatternsDeveloped New Test PatternsDeveloped New Test PatternsDeveloped New Test Patterns
rawarbrawa
rawarbrawa
rawarbrawaFF
rawarbrawaFF
rawaholdrbwbholdrawaholdrbwbholdrawa
,,,,5555
,,,,3333
,,,,00
,,,,00
,,,,,,,,,,,,,0000
Test Pattern SAF SOF TF AF CFst CFin CFid
10N March Test 1 X 1 X X 1 X
12N March Test 1 X 1 X X 1 X
LaRC Test 1 1 1 1 1 1 1
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Automatically Memory TTRAutomatically Memory TTRAutomatically Memory TTRAutomatically Memory TTRCompare the conditions
(Voltage, Timing, Bank, Burst, DBG)
Separated all patterns form conditions
Established thepattern correlation tables
Use TTR algorithm to fine the redundancy patterns
(find subset)
Established the pattern correlation table for suggest test items
(find intersection)
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Test Item FormulationTest Item FormulationTest Item FormulationTest Item Formulation
Voltage Timing Bank Burst DBG Alg.
Voltage: the applied voltage of test chip such as VDD, PP ...etc
Timing: the timing specification used in each test element
Bank: the number of memory bank used on testing
Burst: the number of burst used on testing
DBG: the data back ground
Alg.: the test patterns
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Pattern Correlation Table Pattern Correlation Table Pattern Correlation Table Pattern Correlation Table rawarbrbwbrawaPattern
raARwaPattern
rbrbwbrawaPattern
rawaPattern
NNN
NN
NNN
NN
,,,,,,:4
,,:3
,,,,:2
,:1
>N(wa)
>N(ra)
>N(ra,wb,rb)
>N(rb)
AR >N(rb,wa,ra)
Pattern1 v v
Pattern2 v v v
Pattern3 v v v
Pattern4 v v v
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TTR AlgorithmTTR AlgorithmTTR AlgorithmTTR Algorithm
Finding a pattern which has max subset in the correlative table
Taking away the element from the correlative table
Establishing the new correlative
table
Establishing the final correlative
tableIs there element in
the correlative table
Yes No
Finding the redundancy
patterns
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Input File of Test ItemsInput File of Test ItemsInput File of Test ItemsInput File of Test ItemsItem pattern1beginvoltage 2.3vtiming 12nbank 1burst 1DBG 0000function >N(wa),>N(ra)end
ZZ
NN
ZZ
NN
||
||
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Output Reference FileOutput Reference FileOutput Reference FileOutput Reference FileTable0
element >n(wa) >n(ra) >n(ra,wb,rb) >n(rb) (AR) >n(rb,wa,ra)
pattern2 ****** ********** *****
pattern3 ****** ****** ****
pattern4 ****** ********** **********
The redundancy pattern is:
pattern1
pattern5
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Experimental Result for Test Time ReductionExperimental Result for Test Time ReductionExperimental Result for Test Time ReductionExperimental Result for Test Time Reduction
Test Item Test Time
Functional Test 4.90
Power-on Test 3.00
Merged Test 5.00
Retention Test 27.8
10N March Test 3.00
12N March Test 31.00
LaRC New Pattern 28.9
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Total Reduced TimeTotal Reduced TimeTotal Reduced TimeTotal Reduced Time Chose 26 test items from 222 test items and red
uced to 22 test items Picked 2173 fail samples to prove our idea The test time is saved 7% at the condition of s
ame failure coverage
Original Tests Reduced Tests
Reduced Test Time Ratio
FT (HT) 582.2s (135) 530.9s (129) 8.48%
FT (LT) 834.8s (87) 785.6s (81) 5.89%
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OutlineOutlineOutlineOutline1. Introduction
2. Memory Test Time Reduction Method
3. Automatically Memory Test Time Reduction
4. Experimental Results
5. Proposed Flash Memory BIST Architecture
6. Flash Memory BIST Generator
7. Experimental Results
8. Conclusions and Future Work
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Contribution to Flash Memory TestingContribution to Flash Memory TestingContribution to Flash Memory TestingContribution to Flash Memory Testing
Flash Disturb Flash Modeling
Test Algorithm Development
Built-In Self-Test Design
Experimental Result
BIST/BISD BIST/BISD CompilerCompiler
BIST/BISD BIST/BISD CompilerCompiler
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Original Flash Memory BIST ArchitectureOriginal Flash Memory BIST ArchitectureOriginal Flash Memory BIST ArchitectureOriginal Flash Memory BIST Architecture
CTR TPG
MUX
(Test Collar)
BSI
BMS
BSO
BRS
BCE
CLKBNS
ENA
CONT
CMD
DONE
ERR
EOP
Address
Data
Control Signals
Flash test
control line
Address
Data
Control Signals
BSI: BIST serial input BSO: BIST serial output BMS: BIST mode selectBRS: BIST reset BNS: BIST/Normal select BCE: BIST commend endCLK: System clock
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The Original FSM of CTRThe Original FSM of CTRThe Original FSM of CTRThe Original FSM of CTR Get_CMD and
Scan_In will move to the state Scan_MB
Set_TPG and Run_TPG will move to the SEQ circuit
FinishFinish
IdealIdeal
Scan Scan InIn
Get Get CMDCMD
Set Set TPGTPG
Run Run TPGTPG Shift Shift
EOPEOP
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The Original FSM of TPGThe Original FSM of TPGThe Original FSM of TPGThe Original FSM of TPG The Dfetch and
Compare state will work in TPG
The Wait state will change to Shift_EOP in original Controller state
Idle Idle
FetchFetch
ExecExec
DfetchDfetch
comparecompare
WaitWait
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Proposed New Flash Memory BIST ArchitectProposed New Flash Memory BIST ArchitectProposed New Flash Memory BIST ArchitectProposed New Flash Memory BIST Architect
CTR SEQ TPGMBC
MSI
MSO
MBO
MRD
MCKMBRMBS
BG
SEQ_CS
MODE
CMD
SEQ_GO
SEQ_DONE
SEQ_DIAG TPG_FINISH
TPG_GO
TPG_DIAG
TPG_CS
SEQ_ADDR
SEQ_OP_CMD
SEQ_PARITY
Flash control line
Flash test
control line
MM
UU
XX
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MBC=1
Run_Test_Idle
Select_MB
Scan_MB
Run_MB
MBC=0
MBC=1
MBC=0
MBC=0
MBC=0MBC=1
MBC=1
The FSM of ControllerThe FSM of ControllerThe FSM of ControllerThe FSM of Controller The FSM is the same
as the RAM
Share with RAM controller completely
Generate by BRAINS
Only change algorithm to March-FT
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Idle
Ifetch
Exec
Shift_EOP
SEQ_CS = 0
SEQ_CS=1 FINISH=1
FINISH=0ERR=0
ERR=1
Counter = 0
Counter != 0
FINISH = 1
FINISH = 1
FINISH = 0
The FSM of SequencerThe FSM of SequencerThe FSM of SequencerThe FSM of Sequencer Decode command an
d decide address in Ifetch state
Send command to TPG in Exec state
Shift the error information in Shift_EOP stat
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The Test Pattern GeneratorThe Test Pattern GeneratorThe Test Pattern GeneratorThe Test Pattern Generator A counter to count the flash timing and send th
e message to flash in right time Decide when to compare and to compare data
and pattern Insert MUX Embedded flash memory core and stand-alone
flash memory chip are suitable for use
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Flash Memory BIST GeneratorFlash Memory BIST GeneratorFlash Memory BIST GeneratorFlash Memory BIST Generator
BID format(memory spec. and test requirement)
Description parser parse.py, read_lib.py,
create_march_f.py
Compiler enginebcf.py
top_module.py, controller_f.py, sequencer_f.py,
tpg_f.py
template (controller.template,
sequencer.template, tpg.template)
BIST model (verilog file, test bench)
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SupportsSupportsSupportsSupports work path program path library path clock cycle asynchronous reset test compilation test control
command count
default algorithm
supported element
diagnosis mode
data width and address width
mux support
port, command, task, timing, state
* Comparable with BRAINS
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Experimental Result of Embedded CoreExperimental Result of Embedded CoreExperimental Result of Embedded CoreExperimental Result of Embedded Core
BIST Flash MemoryTSMC SFC0512-08BB
MBC
MSI
MSO
MBO
MRD
MCK MBR MBS
Flash controller line
Flash test controller line
A typical 4Mbits (512K x 8) embedded Flash memory core with BIST circuitry
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BIST Waveform with Behavior Model BIST Waveform with Behavior Model BIST Waveform with Behavior Model BIST Waveform with Behavior Model
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Erase Command Detail WaveformErase Command Detail WaveformErase Command Detail WaveformErase Command Detail Waveform
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ConclusionsConclusionsConclusionsConclusions We proposed new method to reduce the lengthy
test time of industry test flow
The new test pattern was proposed and verified on the tester the reduction ratio is about 7% in our study case
We developed the flash memory BIST generator and this BIST architecture can combine with RAM BIST
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Future WorkFuture WorkFuture WorkFuture Work The memory TTR method can extend more
options and functions How to model test item of different type is
important
To extend Flash BIST generator Support test mode, handshaking, repair, etc…