semi international standards · • semi 3d4-0613 , guide for metrology for measuring thickness,...

SEMI® International Standards

Information on 3DS-IC ActivitiesJanuary 2014

SEMI 3DS-IC Standards Activities

3DS-IC Standards CommitteeCharter

• To explore, evaluate, discuss, and create consensus-based specifications, guidelines, and practices that, through voluntary compliance, will;– promote mutual understanding and improved communication between users and suppliers of 3DS-IC materials, carriers, automation systems and devices, and

– enhance the manufacturing efficiency and capability and shorten time-to-market so as to reduce manufacturing cost in the 3DS-IC industry.

• Committee formed in Fall 2010• Inaugural meeting held in January 12, 2011


Participating Companies*

SEMI 3DS-IC Standards Activities* partial list

AGC Electronics

Altera

Applied Materials

ASE

Brewer Science

Corning

eda 2 asic

Elpida Memory

Entegris

Fujifilm Electronic

GLOBALFOUNDRIES

Intel

ITRI

MicroSense

Neocera

NIST

Qualcomm

Quartet Mechanics

ROHM Semiconductor

Rudolph Technologies

SEMATECH

Semilab

Shin-Etsu Polymer

Sonoscan

SUMCO

Suss MicroTec

Tamar Technology

TAZMO

Tezzaron

Toray Engineering

TSMC

Xilinx


Organization Charts

NA 3DS-IC Committee

Chairs:

• Urmi Ray (Qualcomm)

• Sesh Ramaswami (Applied Materials)

• Rich Allen (NIST)

• Chris Moore (---)

Taiwan 3DS-IC Committee

Chairs:

• Tzu-Kun Ku (ITRI)

• Wendy Chen (King Yuan Electronics)

• Yi-Shao Lai (ASE)

Testing

Task Force

Leader:

• Sam Ko (KYEC)

• Roger Hwang (ASE)

• Tzong-Tsong Miau (ITRI)

Middle End Process

Task Force

Leader:

• Arthur Chen (NTUST)

• Erh Hao Chen (ITRI)

• Jerry Yang (SEMATECH)

Inspection & Metrology

Task Force

Leader:

• Yi-Shao Lai (ASE)

• David Read (NIST)

• Victor Vartanian (SEMATECH)

Thin Wafer Handling

Task Force

Leader:

• Urmi Ray (Qualcomm)

• Raghunandan Chaware (Xilinx)

• Richard Allen (NIST)

Wafer Bonded Stacks

Task Force

Leader:

• Rich Allen (NIST)

Japan Packaging Committee

Chairs:

• Kazunori Kato (AiT)

• Yutaka Koma (Koma Consulting)

• Masahiro Tsuriya (iNEMI)

3D-IC Study Group

Leader:

• Masahiro Tsuriya (iNEMI)

• Haruo Shimamoto (AIST)

Thin Chip (Die) Bending

Strength Measurement

Task Force

Leader:

• Haruo Shimamoto (ASET)

• Morihiro Kada (ASET)

• Shoji Yasunaga (Rohm)

Published Standards [1/7]

• SEMI 3D1-0912, Terminology for Through Silicon via Geometrical Metrology

– Clear and commonly accepted definitions are needed for efficient communication and to prevent misunderstanding between buyers and vendors of metrology equipment and manufacturing services.

– The purpose of this Document is to provide a consistent terminology for the understanding and discussion of metrology issues important to through silicon vias (TSV).



• SEMI 3D2-0113, Specification for Glass Carrier Wafers for 3DS-IC Applications– This Specification describes:

• dimensional, thermal, and wafer preparation characteristics for glass starting material that will be used as carrier wafers in a temporary bonded state;

• glass carrier wafers with nominal diameters of 200 and 300 mm, and a thickness of 700 um, although the wafer diameter and thickness required may vary due to process and functional variation. Such variations shall be clarified in the purchasing order or in the contract.

– Methods of measurements suitable for determining the characteristics in the specifications are indicated.



• SEMI 3D3-0613, Guide for Multi-Wafer Transport and Storage Containers for 300 mm, Thin Silicon Wafers on Tape Frames

– This Guide is intended to address the needs for choosing a method for shipping thin wafers on tape frames in such a way that they arrive undamaged at their final destination. It describes various methods of shipping thin wafers on tape frames.



• SEMI 3D4-0613, Guide for Metrology for Measuring Thickness, Total Thickness Variation (TTV), Bow, Warp/Sori, and Flatness of Bonded Wafer Stacks– Control of parameters, such as bonded wafer stack (BWS)

thickness, total thickness variation (TTV), bow, warp/sori, and flatness metrology, is essential to successful implementation of a wafer bonding process. These parameters provide meaningful information about the quality of the wafer thinning process (if used), the uniformity of the bonding process, and the amount of deformation induced to the wafer stack by the bonding process.

– This Guide provides a description of tools that can be used to determine these key parameters before, during, and after the process steps involved in wafer bonding.



• SEMI 3D5-0613, Guide for Metrology Techniques to be used in Measurement of Geometrical Parameters of Through-Silicon Vias (TSVs) in 3DS-IC Structures

– This Guide aims to assist in the selection and use of tools for performing measurements of geometrical parameters of an individual TSV (through-silicon via), or of an array of TSVs.



• SEMI 3D6-0913, New Standard: Guide for CMP and Micro-bump Processes for Frontside Through Silicon Via (TSV) Integration – This Guide provides:

• A generic middle-end process flow to define acceptable TSV and CMP quality criteria as well as to develop methodology and measuring procedures for micro-bump.

• A criteria and common baselines of the middle-end process for related upstream and downstream manufacturers in fabricating 3DS-IC products.


Originated by Taiwan 3DS-IC


• SEMI 3D7-0913, New Standard: Guide for Alignment Mark for 3DS-IC Process – Photo alignment mark configuration is the key to ensure consistent and precise alignment of layers, chips and wafers.

– This Guide provides:• the alignment mark strategy for chip to chip, chip to wafer, and wafer to wafer stacking.

• addresses the universal alignment mark where the outcome will be a feasible photo alignment standard.


Originated by Taiwan 3DS-IC

Recently Approved NA 3DS-IC BallotAdjudicated during the NA Standards Fall 2013 Meetings


* Cycle 6, 2013 *

Doc # Description TC Action

5617(5 LIs)

Line Item Revisions to SEMI 3D5-0613, Guide for Metrology Techniques to be used in Measurement of Geometrical Parameters of Through-Silicon Vias (TSVs) in 3DS-IC Structures

Line Item 1 – Rewrite sections 6.1 and 6.2 for clarity Passed as balloted. Superclean

Line Item 2 – Correct wording in Section 7.1 Passed as balloted. Superclean

Line Item 3 – Correct wording in Section 7.4 Passed as balloted. Superclean

Line Item 4 – Modify wording in Note 1 to clarify intent Passed as balloted. Superclean

Line Item 5 – Correct wording in Section 9.1.1.1 Passed as balloted. Superclean

Active SNARFs [1/3](Standards New Activity Report Form)


Bonded Wafer Stacks TF

Doc. 5173 New Standard: Guide for Describing Materials Properties and Test Methods for a 300 mm 3DS-IC Wafer Stack

Doc. 5174 New Standard: Specification for Identification and Marking for Bonded Wafer Stacks

NOTE: The NA 3DS-IC Bonded Wafer Stacks Task Force plans to split SNARF # 5173 into

smaller document development activities. Corresponding SNARFs will be submitted for approval.

North America

Active SNARFs [2/3]


Inspection & Metrology TF

Doc. 5270 New Standard: Guide for Measuring Voids in Bonded Wafer Stacks

Doc. 5447 Terminology for Measured Geometrical Parameters of Through-Glass Vias (TGVs) in 3DS-IC Structures

Doc. 5506(revised):

October 29, 2013)

New Standard: Guide for Measuring Warp, Bow and TTV on Silicon and Glass Wafers Mounted on Wire Grids by Automated Non-Contact Scanning using Laser Scanning Interferometry- Changed from Test Method to Guide

Doc. 5616 Revision to SEMI 3D4, Guide for Metrology for Measuring Thickness, Total Thickness Variation (TTV), Bow, Warp/Sori, and Flatness of Bonded Wafer Stacks

North America

Active SNARFs [3/3]


Taiwan

Middle-End Process TF

Doc. 5688New!

New Standard: Guide for Overlay Performance Assessment for 3DS-IC Process

Testing TF

Doc. 5485 New Standard: Guide for Incoming/Outgoing Quality Control and Testing Flow for 3DS-IC Products

Task Force – Major Updates [1/3]

• (NA) Bonded Wafer Stacks TF– SNARF # 5173 (Guide for Describing Materials Properties for a 300 mm 3DS-IC Wafer Stack) to be broken down into five (5) individual document development activities:1) Silicon Device Wafers2) Silicon Carrier Wafers3) Glass Carrier Wafers4) Intermediate Wafers5) Wafer Stacks

• (NA) Thin Wafer Handling TF– Discussions on possible new activities:

• Dicing tape characterization and performance• Unsupported thin wafer handling



• (TW) Middle-End Process TF– New SNARF # 5688: Guide for Overlay Performance Assessment for 3DS-IC Process• This guide will provide a generic optical measurement methodology and linear dimensional parameters such as translation, expansion, rotation, residue errors and vector plots for overlay performance assessment in 3D-IC middle end process quality control.

• It includes generic overlay target design methodology, instrument configuration, theoretical model and measurement algorithm consideration for face-to-face and face-to-back wafer in 3D-IC process.

• This guide will focus on infrared measurement methods available rather than provide an exhaustive list of the state of the art of overlay methodology of 3D-IC process.



• (JA) 3D-IC Study Group– Discussing possible new standards activity on Bonded Wafer Handling, Stacked Wafer Handling and Diced Stacked Dies Handling

• (JA) Thin Chip (Die) Bending Strength Measurement– Currently gathering the measurement data by newly proposed bending method with various wafer thickness down to 10 um. And the validity of measurement method is under discussion.

– Also discussing about the measurement data with/without TSVs which are significant for 3D-IC.


See next slide >>>


Stage

DieBending Tool

Height : L

Stage

Bending RegionInitial Position

Stage

Broken Point

Broken

Force

Bending Length

Grind Side

New Proposal : CANTILEVER BENDING METHOD

Broken Point

Bending Region

Initial Position

Applied

Force

bbbb Die WidthDie WidthDie WidthDie Width

hhhhDie Die Die Die ThicknessThicknessThicknessThickness

PPPPBBBB

AppliedAppliedAppliedApplied ForceForceForceForceatatatat Break(N)Break(N)Break(N)Break(N)

LLLL SpanSpanSpanSpan

CantileverCantileverCantileverCantilever BeamBeamBeamBeam

Calculation

σ(σ(σ(σ(MPaMPaMPaMPa) =) =) =) =

6P6P6P6PBBBBLLLL

bhbhbhbh2222

σσσσ: Flexural: Flexural: Flexural: Flexural StressStressStressStress

Die thickness＜＜＜＜50um

Upcoming Standards Meetings

• Japan Packaging– March 20, 2014 @ SEMI Japan (Tokyo)– In conjunction with the Japan Standards Spring 2014 Meetings

• Taiwan 3DS-IC– March 2014, exact date TBA

• North America 3DS-IC– April 1, 2014 @ SEMI HQ (San Jose, CA)– In conjunction with the NA Standards Spring 2014 Meetings


Upcoming 3D/Packaging Events

• [This week!] European 3D TSV Summit– January 20-22; Grenoble, France– Latest TSV product developments and achievements — including cost,

business models, supply chain, manufacturability and technology aspects —being addressed by executives and experts from global companies.

• SEMICON West 2014 (July 8-10)– Two SEMI Technology Symposium (STS) Sessions

• Partnering with the IEEE Components, Packaging, and Manufacturing Technology (CPMT) Society

• Organized by the SEMI Advanced Packaging Committee

– TechXpot session organized by MEPTEC (coordinating with the SEMI Advanced Packaging Committee)

– Other sessions with packaging-related component• Internet of Things• Silicon Photonics• Power Semiconductors


Standards Staff Contacts for 3DS-IC


JapanNaoko [email protected]

TaiwanCher [email protected]

North AmericaPaul [email protected]

Introduction to the SEMI International Standards Program

January 2014


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Back-up


SNARF # 5174

• New Standard: Specification for Identification and Marking for Bonded Wafer Stacks – Task Force: Bonded Wafer Stack TF (NA)– Rationale

• Current wafer identification standards and wafer marking standards do not adequately address the needs of bonded wafer stacks. Location (e.g. backside near notch for SEMI T7) will be removed during backside thinning operations or edge-trim operations, or buried under an opaque layer of silicon and rendered un-readable by optical readers when bonded. Multiple wafer stacks will combine wafers with multiple process history, including tracking of temporary carrier wafers, and a standard needs to be developed to combine and track bonded wafer stacks with multiple wafer histories.

– Scope• Develop an identification standard that will meet the needs of bonded wafer

stacks. The initial focus will be temporary bonding and permanent bonding as driven by contributions.


SNARF # 5270

• New Standard: Guide for Measuring Voids in Bonded Wafer Stacks– Task Force: Inspection & Metrology TF (NA)– Rationale

• This Guide will assist the user in selection and use of bond-void metrology tools based on their application and a protocol for performing bond-void measurements. New bonding processes and applications are sensitive to significantly smaller voids than bonding processes currently used for 3DS-IC package sealing. The Guide will compare detection, in bonded wafer pairs, of prefabricated voids in several oxide thicknesses, the void detection limits of a range of metrology tools and provide application recommendations. This activity will be executed in a planned 3DS-IC project at SEMATECH. The test results and analysis will create a fundamental study of oxide-bonded wafer pairs. Subsequently this study can assist producers and users of other wafer bonding processes to develop robust products and evaluations.

– Scope• A number of technologies have been released to measure voids between bonded wafers.

These technologies each have unique strengths and weaknesses. In this activity, we will compare the capabilities of these technologies and prepare a guide to the use and applicability of these tools for different bonding applications.


SNARF # 5447

• New Standard: Terminology for Measured Geometrical Parameters of Through-Glass Vias (TGVs) in 3DS-IC Structures– Task Force: Inspection & Metrology TF (NA)– Rationale

• Current standards or work in progress focuses on use of silicon as a substrate or wafer. This new document should address parameters and definitions for glass as a substrate or wafer for 2.5 and 3DS-IC applications. It will follow the new standard: Terminology for Through Silicon Via Geometrical Metrology definitions where applicable and will indicate when there are differences and why.

– Scope• Define terms currently used to describe TGV parameters which are not

defined in current SEMI Standards, and list those that are already defined in current SEMI Standards. For each parameter (or group of parameters), the various technologies that are used will be listed, along with any limitations and/or issues and needs particular to that technology and to making valid comparisons to the others. Include applicable ranges for valid measurements where possible.


SNARF # 5482

• New Standard: Specification for Glass Wafers for Use in Bonded Wafer Stacks– Task Force: Bonded Wafer Stacks TF (NA)– Rationale

• Glass wafers are moving from serving niche markets to high volume use, such as for carrier wafers for 3D stack applications. This standard will provide an order entry form for use by customers in purchasing glass wafers. In addition, this standard can serve as the basis for specifications for glass wafers for specific applications, starting with glass wafers for carrier applications.

• The material in this standard was previously balloted as section 9 of D5173A, most recently in Cycle 4, 2012. This section is being split out of D5173B as part of the Bonded Wafer Stack Task Force’s activities to address issues raised by the voters casting negative votes. It is also being modified to allow use for acquisition of wafers with diameters other than 300 mm (nominal). D5173B is expected to be balloted simultaneously with this document.

– Scope• Develop a glass wafer specification order format for order entry, such as Table 1 in SEMI

M1 and Table 1 in SEMI M62 for silicon wafers and silicon wafers with epitaxial layer, respectively. This standard will then be usable in SEMI documents for specifying glass wafers for purposes such as devices, carriers, etc.


SNARF # 5485

• New Standard: Guide for Incoming/Outgoing Quality Control and Testing Flow for 3DS-IC Products– Task Force: Testing TF (TW)– Rationale

• To ensure consistent yield control of 3DS-IC products, common criteria for incoming quality control (IQC) and outgoing quality control (OQC) of OSATs (outsourced sub-assembly and test providers) are needed. The generic testing flows for different 3DS-IC products to also be defined in this document will expedite the progress of 3DS-IC testing.

– Scope• This guide will define the criteria of incoming quality control (IQC) and

outgoing quality control (OQC) of OSATs, such as appearance, TSV void percentage by X-ray inspection, etc., to clarify the manufacturer’s responsibilities and to improve product yield.

• This guide will also define the generic testing flows for different 3DS-IC products, such as chip on chip (CoC), chip on substrate (CoS), stacked chip on substrate (CoS), wafer on wafer (WoW), etc., to help accelerate the progress of 3DS-IC testing.


SNARF # 5506

• New Standard: Guide for Measuring Warp, Bow and TTV on Silicon and Glass Wafers Mounted on Wire Grids by Automated Non-Contact Scanning using Laser Scanning Interferometry– Task Force: Inspection & Metrology TF (NA)– Rationale

• The current metrology strategies have evolved from methods used to characterize smaller, lower aspect ratio geometries. Conventionally, three point mounts have been used to measure flatness/warp of wafer along with gravity compensation.

• Nowadays, however, the trend goes to use larger in diameter and thinner wafers, for instance in 3DS-IC applications. Larger and thinner wafers are less stiff than conventional ones. Low stiffness leads to a high deflection and sag, which can even exceed the required warp tolerance. In addition, the new applications require a complete depiction of the wafer’s shape, thus interpolation calculation methods based on few data points fail to depict the real free state of the wafer and allow passing failures like local bow.

• The industry therefore would benefit from identifying a guide that better reflects the application usage of these wafers. One such approach used in the industry is a similar set up to Sori with a wire mount and a noncontact scanning method that allows depicting a complete picture of the wafer’s shape and dimensional parameters.

• This guide will recommend the wafer to be characterized in a position that allows for a free state profile measurement on a semi-continuous flat mounting surface.

– Scope• Establish a guide on how to measure wafers with a deflection of more than twice their warp

tolerance. This guide can be applied to all materials and geometrical shapes.


SNARF # 5616

• Revision to SEMI 3D4, Guide for Metrology for Measuring Thickness, Total Thickness Variation (TTV), Bow, Warp/Sori, and Flatness of Bonded Wafer Stacks – Task Force: Inspection & Metrology TF (NA)– Rationale

• Comments in balloting suggested some edits need to be made so we propose to ballot several line item changes.

– Scope• The following changes are proposed::

1) Section 2.4:Proposal to change text to: “The Guide focuses on general measurement techniques including IR laser profiling, white light confocal microscopy, visible and IR interferometry, capacitance, back-pressure and acoustic microscopy. Each technology has unique strengths and weaknesses—some rely on front-side illumination, others on back-side illumination. Some techniques can measure the thicknesses of individual layers in the bonded wafer stack, and some are additionally capable of measuring surface nanotopography.”2) Section 2.6:Proposal to change text to: “The measurements described in this Guide are on bonded wafer stacks with thickness in the range of 50 to 1550 ìm. The Taskforce will identify a thickness range appropriate for 3DS-ICs.”3) Section 5.2, proposal to fix typographical error:Proposal to remove the “2” after the word “depictions” in Figure 3 Figure Caption.4) Section 5, Terminology, proposal to add the following:5.1.5 CSI — coherence scanning interferometry5) Proposal to make Figure 44 less pixelated (need to obtain better copy of figure).Other line item changes as identified by the Taskforce.


SNARF # 5688

• New Standard: Guide for Overlay Performance Assessment for 3DS-IC Process– Task Force: Middle-End Process TF (TW)– Rationale:

• Various bonding processes have been developed and applied to specific products for 3D-IS process. Wafers can be bonded face to face (F2F) or face to back (F2B), where the choice of stacking direction is dictated by how the stacks are carried in the process and what the required functionality is. One of the challenges is to identify the perfectness of the overlay for the F2B and F2F. It will directly affect the device performance. A generic overlay performance assessment method will be described in order to provide criteria and common baselines of the middle-end process for related upstream and downstream manufacturers fabricating the 3DS-IC products. The guidelines will suggest generic overlay patterns, measurement methodologies, analysis methods for assessing the overlay performance.

– Scope: • 1. Address generic overlay target design methodology, instrument configuration, theoretical

model and measurement algorithm consideration for F2F F2B wafer in 3D-IS process.• 2. Develop criteria for describing overlay performance in terms of translation, expansion, rotation,

residue errors and vector plots, measurement uncertainty will also be described.• This guide will provide a generic optical measurement methodology and linear dimensional parameters

such as translation, expansion, rotation, residue errors and vector plots for overlay performance assessment in 3D-IC middle end process quality control. It includes generic overlay target design methodology, instrument configuration, theoretical model and measurement algorithm consideration for F2F and F2B wafer in 3D-IS process. This guide will focus on infrared measurement methods available rather than provide an exhaustive list of the state of the art of overlay methodology of 3D-IC process.


semi international standards · • semi 3d4-0613 , guide for metrology for measuring thickness,...

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