self-aligned techniques mems release techniques advance...
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![Page 1: Self-aligned Techniques MEMS Release Techniques Advance Techniquesmaecourses.ucsd.edu/~pbandaru/mae268-sp09/Class Readings... · 2004-04-15 · Self-aligned Techniques •LOCOS- self-aligned](https://reader033.vdocuments.mx/reader033/viewer/2022041909/5e66b39a789e022bc74083f4/html5/thumbnails/1.jpg)
Professor Nathan Cheung, U.C. Berkeley EECS143 Lecture # 19
Process Integration
• NMOS – Generic NMOS Process Flow .• CMOS - The MOSIS Process Flow
Self-aligned Techniques•LOCOS- self-aligned channel stop•Self-aligned Source/Drain•Lightly Doped Drain (LDD)•Self-aligned silicide (SALICIDE)•Self-aligned oxide gap
Advance Techniques•Twin Well CMOS •Retrograde Wells •SOI CMOS
MEMS Release Techniques•Sacrificial Layer Removal•Substrate Undercut
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Professor Nathan Cheung, U.C. Berkeley EECS143 Lecture # 19
Self-aligned channel stop with Local Oxidation (LOCOS)
Si3N4 CVDpad oxide
Si
LOCOS Process Flow
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Professor Nathan Cheung, U.C. Berkeley EECS143 Lecture # 19
B+ channelstop
implant
Si
thermal oxidation(high temperature)
FOX
Self-alignedchannel stop
pp
B
dose~1013/cm2
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4Professor Nathan Cheung, U.C. Berkeley EECS143 Lecture # 19
* If a poly or metal line lies on top of the FOX, they will forma parasitic MOS structure.If these lines carrying a high voltage, they may create an inversion layer of free electrons at the Si substrate and shorts out neighboring devices. The relatively highly doped Si underneath (the “channel stop”) raises the threshold voltage needed for the inversion
SiO2
p-Si
metal
Comment: Channel Inversion
Electron InversionLayer
Device 1 Device 2
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Professor Nathan Cheung, U.C. Berkeley EECS143 Lecture # 19
Comments : Non self-aligned alternative:
P.R.1
SiO2
P+ P+
SiP+ P+
SiO2
2B+
3
Disadvantages1) Two lithography steps2) Channel stop doping notaligned with field oxide
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Professor Nathan Cheung, U.C. Berkeley EECS143 Lecture # 19
Self-aligned Source and Drain
.n+n+
poly-Si gateAs+
.n+n+
As+
Off Alignment
Perfect Alignment
* The n+ S/D always follows gate
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Professor Nathan Cheung, U.C. Berkeley EECS143 Lecture # 19
Comment: Non self-aligned Alternative
.n+n+ 2
.n+n+
“Solution”Use gateoverlap to avoid offseterror.
.n+n+ 1
Channel not linked to S/D
Straycapacitance
Disadvantages: Two lithography steps, excess gate overlap capacitance
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8Professor Nathan Cheung, U.C. Berkeley EECS143 Lecture # 19
Lightly Doped Source/Drain MOSFET (LDD)
n+ n+n nSiO2
CVD oxidespacer
p-sub
•The n-pockets (LDD) doped to medium conc (~1E18) is to smear out the strong E-field bewteen the channel and heavily doped n+ S/D. Less hot-carrier generation.
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9Professor Nathan Cheung, U.C. Berkeley EECS143 Lecture # 19
n implantfor LDD
SiO2
CVD SiO2
Directional RIE of CVD Oxide
CVD conformaldeposition SiO2
LDD Process Flow
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10Professor Nathan Cheung, U.C. Berkeley EECS143 Lecture # 19
Spacer left when CVD SiO2is just cleared on flat region.
nn
0.05µm
0.25µm
n+ n+
n+ implant
n n
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11Professor Nathan Cheung, U.C. Berkeley EECS143 Lecture # 19
Self-Aligned Silicide Process (SALICIDE)
n+n+
TiSi2 (metal)poly-gate
* Metal silicides are metallic.Lower the sheet resistance of S/D and the poly-gate
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12Professor Nathan Cheung, U.C. Berkeley EECS143 Lecture # 19
n+n+SiO2
oxide spacer
SALICIDE Process Flow
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13Professor Nathan Cheung, U.C. Berkeley EECS143 Lecture # 19
n+n+SiO2
Ti
Ti deposition
Si
TiTiSi2
TiTi .
2)700(
2
2
SiOwithreactnotwillTiTiSiSiTi
Ctreatmentheat o
→+>
Selective etch to remove unreacted Ti only
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14Professor Nathan Cheung, U.C. Berkeley EECS143 Lecture # 19
Self-aligned Oxide Gap
n+
poly-Ipoly-II
small oxide spacing < 30nm
inversioncharge layerpoly-I
substrate
Gateoxide
poly-IIMOSFET
MOSCapacitor
DRAM structure ( MOSFET with a capacitor)
V (plate)
NOTEFor a small spacing betweenpoly-I and poly-II, inversioncharges between MOSFET and Capacitor are electrically linked. No need for a separaten+ island.
Thermal Oxide grown conformallay on poly-I
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15Professor Nathan Cheung, U.C. Berkeley EECS143 Lecture # 19
Process Flow of MEMS Rotating Mechanisms
MicroturbineEngine
In-Plane Movement
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16Professor Nathan Cheung, U.C. Berkeley EECS143 Lecture # 19
Process Flow for a Hinge StructureOut-of-plane Movement
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17Professor Nathan Cheung, U.C. Berkeley EECS143 Lecture # 19
Layout of Thermal Bimorph Actuator
(See 143 Lab Manual for details)
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18Professor Nathan Cheung, U.C. Berkeley EECS143 Lecture # 19
After Patterning Poly-Si ( Mask #2)
TopView
CrossSection
Poly SiAluminum Oxide Si substrate Al-Poly contact
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19Professor Nathan Cheung, U.C. Berkeley EECS143 Lecture # 19
After Patterning Intermediate Oxide ( Mask #3, Contact-Hole Cut)
TopView
CrossSection
Poly SiAluminum Oxide Si substrate Al-Poly contact
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20Professor Nathan Cheung, U.C. Berkeley EECS143 Lecture # 19
After Aluminum patterning (Mask #4)
To contact pad
TopView
CrossSection
Poly SiAluminum Oxide Si substrate Al-Poly contact
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21Professor Nathan Cheung, U.C. Berkeley EECS143 Lecture # 19
After XeF2 selective etching of Si Substrate (Final Structure)
To contact pad
Poly SiAluminum Oxide Si substrate Al-Poly contact
TopView
CrossSection
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22Professor Nathan Cheung, U.C. Berkeley EECS143 Lecture # 19
SubstrateBoron doped (100)SiResistivity= 20 Ω-cm
Thermal Oxidation~100Å pad oxide
CVD Si3N4~ 0.1 um
LithographyPattern Field OxideRegions
RIE removal of Nitride and pad oxide
Channel StopImplant: 3x1012 B/cm2
60keV
Thermal Oxidation to grow 0.45um oxide
Wet EtchNitrdie and pad oxide
Ion Implant forThresholdVoltage control8x1011 B/cm2 35keV
Thermal OxidationTo grow 250Ågate oxide
LPCVDPoly-Si~ 0.35um
Dope Poly-Si to n+with PhosphorusDiffusion source
A Generic NMOS Process Flow
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23Professor Nathan Cheung, U.C. Berkeley EECS143 Lecture # 19
LithographyPoly-Si Gate pattern
RIE Poly-Si gate
Source /Drain Implantation~ 1016 As/cm2 80keV
Thermal OxidationGrow ~0.1um oxide on poly-SiAnd source/drian
LPCVDSiO2~0.35um
LithographyContact Window pattern
RIE removal of CVD oxide and thermal oxide
Sputter DepositAl metal~0.7um
LithographyAl interconnect pattern
RIE etch of Al metallization
Sintering at ~400oC in H2 ambientto improve contact resistanceand to reduce oxide interface charge
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Professor Nathan Cheung, U.C. Berkeley EECS143 Lecture # 19
Generic NMOS Process Flow
activedevice
~5 µm
p-Si <100> 500µm
Boron-doped Si20 -cm<100>
Ω
NMOS Structure
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Professor Nathan Cheung, U.C. Berkeley EECS143 Lecture # 19
P.R.
SiO2
Si
nitride
SiO2
P.R.
Si
0.1µm
keVcmB
60/103: 212×
317 /103 cm×
nitride
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Professor Nathan Cheung, U.C. Berkeley EECS143 Lecture # 19
Fox
p+ p+
keVcmB 35/105 211×
Fox
p+p+
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Professor Nathan Cheung, U.C. Berkeley EECS143 Lecture # 19
Resist
n+n+
As+ 80keV, 1016/cm2
n+n+
Thermal oxide
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Professor Nathan Cheung, U.C. Berkeley EECS143 Lecture # 19
AlCVD oxide
intermediateoxide
n+n+
Si/SiO2
H2 anneal ~ 400oC
Al
InterfaceStates Passivation
n+ n+