second breakdown of vertical power mosfet's

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-29, NO. 8, AUGUST 1982 1287

Second Breakdown of Vertical Power MOSFET’s

Abstract-It is shown that a phenomenon of second breakdown similar to that in bipolar transistors can occur in vertical power MOSFET’s. A model for the phenomenon of second breakdown in- volving the avalanche multiplication of the channel current, the parasitic bipolar transistor, and base resistance is proposed. After presenting the theory, this model is compared with experiments on four-terminal V- groove test devices in which the substrate can be accessed independently. Good agreement is achieved between calculated and measured botindaries of the safe operating area, The model should be applicable to DMOS devices as well.

LIST OF SYMBOLS

Breakdown voltage in the expression of M (10). Open-base breakdown voltage of the parasitic bipolar transistor. Gate oxide capacitance per unit surface area. Geometry dependent parameter defined in (B-3). Internal base current. Internal base current at second breakdown. Leakage current between base and collector. Collector current. Collector current at second breakdown. MOSFET drain saturation current before significant avalanche multiplication occurs. MOSFET drain current. MOSFET drain current at second breakdown. Total drain current, Le., the sum of Id and IC. Total drain current at second breakdown. Emitter current. Hole current injected into the emitter current. Hole current injected into the emitter current at second breakdown. MOSFET source current. Hole current generated by impact ionization due to I,. Boltzmann constant. Ratio of Iep to Ip . Channel length. Avalanche multiplication gain. Avalanche multiplication gain at second breakdown. Fitting parameter in the expression of M (10). Doping level in p-base.. Electron charge. Internal base resistance. External base resistance.

Manuscript received September 15, 1981; revised March 4, 2982. This work was supported by the U.S. Naval Avionics Center under

The authors are with the Department of Electrical Engineering and Computer Sciences and the Electronics Research Laboratory, University of California, Berkeley, CA 94720.

Grant N00163-80-C-0450.

R,, On-state resistance of power MOSFET. T Temperature. Vb Internal base potential. VB Voltage at base terminal. Vd Drain voltage. V ~ , S B Drain voltage at second breakdown. V, Gate voltage. VT Threshold voltage. vTO Threshold voltage at’zero body bias. US Saturation drift velocity of electrons in inversion

W Channel width of MOSFET. LYT Base transport efficiency. P Common emitter-current gain. 7 Large-signal body-bias coefficient for MOSFET (see

layer.

Appendix I). 7~ Emitter efficiency of the bipolar transistor. fS Dielectric constant of silicon. P Mobility of electrons in the inversion layer.

B I. INTRODUCTION

POLAR TRANSISTORS in the on state are often sus- ceptible to a breakdown process known as the forward-

bias second breakdown. The important facts about second breakdown are that [1]-[3] : 1) it reduces the safe operating area in the high-voltage range; 2) it often leads to device destruction; and 3) thermal processes are probably involved and the safe operating area depends on the pulse width.

A similar limitation to the safe operating area of vertical power MOSFET’s may and probably does exist. The current, source-drain breakdown voltage, and power limitations of power MOSFET’s are well understood [4], [SI. An additional phenomenon can further limit the safe operating area of the MOSFET in the high-voltage, high-current range and can lead to device destruction. We refer to this phenomenon as the second breakdown in MOSFET’s. There is no universally ac- cepted name for this phenomenon, it is also informally known as “snapback” or “switch-back.” Unlike the forward-bias second breakdown in bipolar transistors, the onset of the second breakdown of MOSFET’s does not seem to involve thermal processes and the safe operating area boundary due to second breakdown is independent of the pulse width from dc down to at least 1 ps.

The explanation for the second breakdown phenomenon of MOSFET’s, as some have informally suggested, involves the parasitic bipolar transistor contained in all power MOSFET’s [4], [5]. The collector and emitter of the bipolar transistor are also the drain and source of the MOSFET as shown in Fig. 2 . When the MOSFET current and voltage are high, the

0018-9383/82/0800-1287$00.75 0 1982 IEEE

1288 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-29, NO. 8 , AUGUST 1982

Y . Droln voltage V, -t ”‘”’

Fig. 1. A typical I- V characteristic of n-channel power VMOS with the observed phenomenon of “second breakdown.”

N-epi

N’Substrate

Drain

P

Substrate SwrceGate Source Substrate

Drain

~1 I b “b

s -

d Drain

P .-- t 6 s -

the analysis. The vertical power MOSFET, however, is quasi- one-dimensional and much more amenable to analysis.

After presenting the theory, the model will be compared with experiments.

11. THEORY A typical structure of a power MOSFET has a short channel

between source and drain in order to minimize the “on-state” resistance. The source, drain, and the narrow p-base form a parasitic n-p-n transistor (for an n-MOSFET) as shown in Fig. 2(a), (b). The breakdown behavior of a power MOSFET will be descriljed by using an equivalent circuit which is Com- posed of a MOSFET in parallel with a bipolar transistor (Fig. 2(b)). One connection between the MOSFET and the parasitic transistor is through the common p-base with an internal base resistance (rb). Various capacitances are not shown in Fig. 2 since only dc breakdown behavior of the device will be discussed in this paper.

At high Id and Vd, impact ionization multiplication [7] generates hole current which flows to ground (source) through r,. This raises the internal base potential Vt,, . The phenomenon “snap-back” is believed to occur when the internal base potential vb is high enough to turn on the parasitic bipolar transistor. Immediately after the bipolar transistor is turned on, the collector (drain voltage) snaps back to or below SVCE and thus a negative-resistance region is traced out. A typical curve aepicting this behavior is sketched in Fig. 1.

A simple model is presented here to help predict or interpret the snap-back behavior of a power MOSFET. For simplicity, two assumptions are used at the onset of snap-back: 1) Vb * 0.6 V; and 2) vb = Ib * rb. At a given gate voltage V, , the source current is

Is = Id0 -k Yvb

=Id0 i- yrbIb (1)

where Ido is the saturation drain current at small-drain voltage and zero substrate bias and y is a large-signal body-bias coefficient which is defined as

An explicit expression of y is discussed in Appendix I. The electric field peaks at or near the metallurgical drain junction. At high, Vd, the large electric field at the drain causes avalanche multiplication of the electron channel current. The resultant holes are driven into the base. If the multiplication gain is M ,

Fig. 2. (a) Structure of U-groove VMOS (n-channel) with substrate the base current Ib is shorted to the source. (b) The circuit model of the structure in (a) includes a psirasitic n-p-n bipolar transistor and a base resistance. = ld - I, (c) Structure of VMOS (n-channel) with separate contacts to source and substrate. (d) Circuit model of the structure in (c). = MI, - Is

bipolar transistor can be turned on and the device voltage = ( M - 1)(IdO + yrblb). snaps back to or below the open-base breakdown voltage Therefore BYcE of the transistor-a relatively low voltage in a high gain bipolar transistor. Such a qualitative model has long been ( M - 1)IdO reported to explain the “snap-back” phenomenon similar to Ib = 1 - y ~ b ( M - 1) Fig. 1 and observed in surface IC-type MOSFET’s [4], [6]. Quantitative analysis, however, has been lacking because the I, = Ido ,

two-dimensional nature of the planar MOSFET’s complicates 1 - yrb(M- 1)

HU AND CHI: BREAKDOWN OF VERTICAL POWER MOSFET’s 1289

In Appendix 11, it is shown that the bipolar transistor snaps back to BVcEo when

I b r b E 0.6.

Equations (3) and (7) yield

Equations (3), (6), and (7) yield

1 0.6 I--=- , . (9)

MSB rb Id, SB

where subscript SB indicates values at snap-back. M is often expressed empirically as [7]

where n is a constant and BV is the breakdown voltage at drain and p-base. From (4), (6), and (10) one obtains

At snap-back, from (12) m d (13)

Id,SB - Id0 = (1 + y r b ) l b , S B

0.6 - + 0.67. -_ rb

= IC, SB

- IC, SB + Ib , SB vd, SB

where ID,sB includes both “drain current” and “collector current” at second breakdown. From Appendik I1

”/E is the emitter efficiency of the bipolar transistor and G is geometry dependent and probably less than unity as described in Appendix 11. I , SB may be neglected in (17). The smallness of and the k g h gain of the bipolar transistor indicate that at the time of second breakdown the recombination in

t 0.6

+ 0.5

s 9

- .. - I

0.4

- 0 ._ ... 5 0.3 0 a 0 LD

m 0.2

0. I

0 0 IO 20 30 40

Drain voltage V, (volt) +

Fig. 3: Internal’ base potential versus drain voltage with Id0 as a parameter. The base potential at the onset of snap-back, when Vd collapses, is close to 0.64 V. The inset shows the circuit used for measurements.

the base and hole injection into the emitter consume a negligible portion of the Ib generated at the MOSFET drain region and all Ib flows through Y b . Equation (1 5) shows that the second breakdown voltage decreases with increasing Id0 and/or increasing r b . Equation (17) actually gives the boundary of the second breakdown region. The shape of this boundary, shown in some later figures, also resembles that of the second breakdown of the bipolar transistor.

111. EXPERIMENTAL RESULTS To test the model presented above, measurements of the

second breakdown voltage v d , s B , y, r b , n, and,BV’.are made on a small four-terminal n-VMOS test device having 400 pm of total channel width. Except for the smaller channel. width, all dimensions are similar to typical commercial power MOSFET’s. The source junction is about 2 ,um deep and the p-base and n-epi-junction is about. 2 pm deep. From the geometry and the p-base resistivity, rb is estimated to be about 1 kQ. The special feature of the test device is that a fourth terminal accesses the p-base independently as shown in Fig. 2(c), (d). AU salient features of the model are checked against experiments. The boundary of the second breakdown region as well as its dependence on rb is calculated with the use of device parameters and compared with the measured values. Only dc tests are conducted. The ambient is kept at room temperature during the tests.

The potential of the internal base V, at the onset of the snap-back is measured with the circuit shown in the inset of Fig. 3. VG is first adjusted to achieve a particular I&. As v d is increased, VB (= v b ) atso increases due to increasing I, . The trace ends at snap-back whereupon v d suddenly collapses. The measurements are repeated for different Ido ranging from 0.25 to 30 PA per pm width of channel. The upper value is comparable to the highest current density in commercial power MOSFET’s.

Over the whole range o f I d 0 tested, snap-back occurs when VB is approximately 0.64 V. This provides strong evidence that turning-on of the parasitic bipolar transistor is associated with second breakdown, at least in this case of floating sub-

1290 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-29, NO. 8, AUGUST 1982

o.7$

Vd

Vr J

l b vs v, I d . = 0.5mA

0.1 -

0 I , , 0 10 2b 30 40 5 0 ' 6 0 70 80

. Drain voltoge V, (volt)'

Fig. 4. Base current versus drain voltage with external resistance (RB) as a parameter and at a constant I,,. The inset shows the circuit used for measurements.

i I d O = 0.5 mA

I

4 0 1 ; ; ; rb=O.B5Kn

External resistance R,(Ka)+

Fig. 5. A plot of l i lsB versus the external resistance (RBI at a constant I,,. The base re'sistance rb is determined from the intercept of the extrapolated line at the axis of Rg.

strate. The constancy of VB at snap-back also suggests that the junction temperature did not vary much over the range of I,, in this study.

rb can be determined in the following manner. At snap-back, Ib,SB . (RB -k Yb) = 0.64. Therefore

Ig,1SB = &2j ( R B r b ) (19)

where Rg is the external resistance connected to the p-base. The base current I b at snap-back is shown in Fig. 4 with different RB and a constant I, , . A plot of versus Rd is shown in Fig. 5 where rb is determined from the intercept of the extrapolated line at the RB axis. This plot follows (19) quite well indicating that vb is 0.63 V at the onset of snap- back regardless of RB. In other words, snap-back is associated with the turn-on of the bipolar transistor even when RB = 0. The value of 0.63 V agrees with Fig. 3 and rb is determined to be 0.85 kf2 for this device. This value of rb is consistent with the dimensions and the estimated resistivity of the p-layer in Fig. l(c). rb, however, is a variable parameter. is expected to originate from a small area at or near the drain junction. rb depends on the size of the area of origination which could affect the spreading resistance. As a result, rb may be a func-

0.7

0.6

+ - 0.5 E - D - 0.4 .. c L

0.3 m (n

m

0.2

0.1

0 40 ' 50 60 70 80 90

Drain voltage Vd (volt) -. (a)

?

0 2 4 6 8 1 0 1 2 Dram current at zero body blas I d 0 h A ) +

(b) Fig. 6. (a) Th-e base current versus drain voltage with Id0 as a parameter

and zero external resistance. The inset shows the circuit for measurement. @) Base resistance versus I,, calculated from data shown in Figs. 3 and 6(a).

tion of VG or Id , . Fig. 6(a) shows the I b at snap-back for different Ido and without R B . From Fig. 6(a) and Fig. 3, i-b

as a functibn of Ido is cdculated and shown in Fig. 6(b). The large-signal body-bias coefficient is determined in ac-

cordance with (2) at the onset of second breakdown, i.e.,

Currents are measured at low Vd but in the saturation region. y as a function of Id0 is shown in Fig. 7, where y is smdl at low I,, but reachek a constant value when Ido is large. This behavior is consistent with the constant transconductance at high Id, observed in power MOSFET's as discussed in Ap- pendix I.

Using (11) and data from Fig. 6(a), a log-log plot of (1 + Ti-b + I d o / I b ) versus V, yields information of n (from the slope) and BV (from the intercept with log [l + yrb +

parameter. It is seen that n varies between 3.5 and 4.5 while a range of 2 to 6 is most often cited for the multiplication of

Id0 / Ib] = 0). Fig. 8 shows Some Of such plots with Id0 as a


0 2 4 6 8 1 0 1 2 Drain current at zero body bios Ido (mA) +

Fig. 7. MeasuIed coefficient of body bias as a function of Ida.

Drain voltage V, (volt)+

Fig. 8. A log-log plot of (1 + yrb +Ido/Ib) versus,drain voltage with Id0 as a parameter.

t 3.04

0 2 4 6 8 1 0 1 2 Drain currentat zero body blas id, (mA)+

Fig. 9. The values of n and BV are found from Fig, 8 from the slopes and the intercepts with the line log (1 + yrb +Ido/Ib) = 0.

electrons [7]. Both IZ and BV are weak functions of Ido as shown in Fig. 9. The reason is believed to be the finite electron density in the drain depletion region that is necessary for the flow of and approximately proportional to the drain current [SI. The electrons partially compensate the space charge due to ionized donors and hence raise the junction breakdown voltage. Other relationships, e.g., (12) and (13), may also be used to find IZ and BV from drain-current measurement if the “collector” current is negligible or can be determined independently and substracted from f D in order to reveal 1,.

Equation (1 5) suggests that the second breakdown voltage is

.- c e n

4 Experlmentol data

, I I I I 1 I I I I I T 9 0 2 4 6 8 1 0 1 2

Drain current at zero body bias Id0 (rnA)+

Fig. 10. Calculated and measured drain voltage at snap-back as a function of Ido.

2 0

I J

0 50 Drain voltage Vd (Volt)+

Fig. 11. Measured and calculated boundaries of safe operating area. The measured boundary is where the I-V curves snap back. The dotted curve plots calculated vd,sB versus h , s ~ ignoring I,,sB, while the solid curve includes I,,sB.

a function of Ido. This relationship determined from the model is compared with the experimental data in Fig. 10. Interestingly the model actually predicts the boundary of a second breakdown or a safe operation region, i.e., the Id-Vd contour at which second breakdown occurs (16). Such a calculated SOA boundary is compared with experiments in Fig. 11. The dotted curve plots the Vd,sB versusId,SB ignoring I,, sB in (1 6); and the solid curve includes I c , s ~ . The “collector” current at snap-back is given in (18) and Ap- pendix 11. In our case, ~ E G M 0.25 is needed in order to fit the solid curve to the measured SOA boundary. Ic,sB, the difference between the dotted and the solid curves is about 1.5 mA. This value agrees with the I , measured at VB = 0.64 V and V, = 0 V. If this component of ID is ignored, the calculated SOA region would be somewhat more conservative, as shown in Fig. 11 by the dotted curve.

The multiplication gain at snap-back may be rather small. This and some other numbers of interest at Ido = 5.0 mA are

MSB = (1 - (&3)4.46-1) = 1.085

ID,SB - Ido = 5.6 mA

I,,sB = 1.4 mA

Ib,sB = 0.71 mA. (2 1)

IV. DISCUSSION Let us discuss the model from the viewpoint of device

optimization. n is a material constant. BY can be increased

1292 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-29, NO. 8 , AUGUST 1982

T

0 2 4 6 8 1 0 Total base reslstance rb + R, (KO) +

Fig. 12. Measured and calculated drain voltage at snap-back versus total base resistance (‘6 +RB).

4 5 0 1

g40- U

E 30- ” c

g 20-

‘. 0 I I I I b

Drain voltage (vdts) +

0 100 200 300 400 500

Fig. 13. Calculated boundaries of safe operating area for power MOSFET’s with BV = 500 V, n = 4.0, rb = 0.05, and ~ E G = 0.2 or 1.0.

‘7;G=0.21 .‘\VI 7E G=I.O

0 -.-__

0 100 200 300 400 500 Drain voltage (vdts) +

Fig. 13. Calculated boundaries of safe operating area for power MOSFET’s with BV = 500 V, n = 4.0, rb = 0.05, and ~ E G = 0.2 or 1.0.

hypothetical 0.1 or 0.5 a,

by increasing the thickness and resistivity of the n-epitaxial layers, but this is the usual voltage-Ron trade-off [9]. Some improvements may be gained by enhancing and exploiting the increase of BV with increasing Id0 (Fig. 9 and Section 111).

The behavior of y in Fig. 7 is consistent with the analytic expression (A-4). y increases with Id0 at small Ido and ap- proaches a constant value when Ido is large. The p-base dop, ing NA and channel length L in (A-4) are most likely determined by other more important considerations. The product yrb , which is the form y appears in all model equations, is not sensitive to the channel width W, since rb is inversely proportional to it. Besides, y does not enter the most important equation at all-the boundary of second breakdown (16) or (17).

I,,sB may be increased by reducing ~ E G such as when yE = 0, for example, ID,sB rises to infinity or when the snap- back phenomenon disappears (see (1 5) and (16)).

The one parameter that may have the most room for im- provement is rb , which depends on the geometry and the sheet resistance of the p-base.

Fig. 4 also shows how rb (or rb + RB) affects the second breakdown voltage. The relationship is plotted in Fig. 12 and is compared with (15).

Only dc measurements taken on small V-groove MOSFET’s are presented here, but similar behavior has been observed on three-terminal high current/voltage devices tested under pulse conditions. It is believed that the model presented here

applies to power MOSFET’s of all current and voltage ratings as well as different designs (VMOS and DMOS). Fig. 13 shows the calculated boundaries of the second breakdown of a hypothetical power MOSFET with BY= 500 V and n = 4.0. Here, the effects of rb are clearly demonstrated.

A standard power MOSFET has three terminals. There is no access to the substrate and it is impossible to measure Ib, I,, y, and r b , however, it is still possible to characterize them in light of the model presented here. One possible set of procedures i s outlined below. First, use (A-4) to estimate y (at high gate voltage, or Ida). Then, measure Id versus Vd at a given I&, where (14) yields rb. Equation (13) can be used to find n and BV after rb is determined. There is no way to measure I,, nevertheless, I , can be neglected if the device operates at high Ido or is estimated with (1 8).

The measurements in this study were performed at room temperature. Both BV and n are expected to increase with temperature. Both BV and rb are expected to increase with down voltage, however, larger rb tends to reduce the drain breakdown voltage. In any event, the second breakdown voltage and current are only weakly dependent on temperature from our high-temperature (25-120°C) measurements.

p-channel power MOSFET’s are not expected to exhibit significant snap-back behavior from the experience with surface MOSFET’s [4], [lo]. The reasons are: 1) lower rb due to higher electron mobility; and 2) lower hole impact-ionization coefficient [ 111.

Finally during the turn-off transient, large dVd/dt can induce a sufficient through the drain-base capacitance (omitted in Fig. 2(b)) to satisfy Ibrb > 0.6 v and cause breakdown [ 121. Since this phenomenon occurs only during the turn-off transient, it may be thought of as a counterpart to the bipolar transistors’ reverse second breakdown.

APPENDIX I ANALYTICAL EXPRESSION FOR y

For an n-channel MOSFET, the saturation drain current is usually expressed as

W 2L

Id = - p c i x [ V G - VT]’ (A- 1)

where

VT = VTI) i- 7 142 I 6 p I - VB - m1 (A-2) 2 f d N A

COX

and all parameters have their usual meanings. Standard power MOSFET’s are short-channel devices; and (A- 1) is only good in a small VG (or I d ) regime. At higher Vc (or I d ) , Id for a short- channel device is known to be linearly proportional to VG - ~r ~ 3 1

W I -- . cAx . ‘ (VGS - VT) d - L (A-3)

where us is the saturation drift velocity of charge carriers in the inversion layer.

Analytical expression of y defined by (2) or (20) may be derived from (A-l), (A-2), and (A-3)


(B-8) and (B-4) would yield

and (B-9) and (1 5) yield (small Id)

(m- .\/2l@p I - 0.6) -; ‘ u , -4- W

(large Id).

Once W and L are fmed, y becomes nearly fured, and dependent only on the substrate doping density.

APPENDIX I1 Vb AND I , AT THE BREAKDOWN OF THE

BIPOLAR TRANSISTOR If avalanche multiplication is considered, the relation be-

tween l e and I , is

IC = (TE aTIe + IBCo)M’ (B-1)

where 3% is the emitter efficiency, aT is the base transport efficiency, and

(B- 1 0)

If rb = 0, then K = 0 and (B-2) and (B-7) yield the open- emitter breakdown voltage BVCB, as expected. At large le (Vb > 0.6 V), K = 1, ( B - 9 , (B-2), and (B-7) yield the open- base breakdown voltage

BV,,, = B V ’ / g .

This is why Vd snaps back to BVCEO as soon as Vb reaches approximately 0.6 V. Once the bipolar transistor enters the high-current state, other mechanisms may set in and further reduce vd to about 20 V [ 2 ] .

ACKNOWLEDGMENT We would like to acknowledge R. Mullen and Dr. K. Lisiak

of Siliconix, Inc., for their assistance with this project. M’ = 1

1 - (V/BV‘)”

where BV‘ is the breakdown voltage of the planar portion of the base-collector junction [7] and may be higher than SV of the MOSFET. n may also be different than that in (10). At the same V , using (10) and (B-2)

REFERENCES

H. A. Schafft, “Second breakdown-A comprehensive review,” Proc. IEEE,vol. 55,no. 8, p. 1272, Aug. 1967. P. L. Hower and V.GX. Reddi, “Avalanche injection and second breakdown in transistors,” IEEE Pans. Electron Devices, vol. ED-17,no. 4,p. 320, Apr. 1970. B. A. Beatty, S. Krishna, and M. S. Adler, “Second breakdown in power transistors due to avalanche injection,” IEEE Pans. Elec- tron Devices, vol. ED-23, no. 8, p. 851, Aug. 1976. J. Yoshida, T. Okabe, M. Katsueda, S. Ochi, and M. Nagata, “Thermal stability and secondary breakdown in planar power MOSFET’s,” IEEE Trans. Electron Devices, vol. ED-27, no. 2, p. 395, Feb. 1980. R. W. Coen, D. W. Tsang, and K. P. Lisiak, “A high-performance planar power MOSFET,” IEEE Trans. Electron Devices, vol. ED-27, no. 2, p. 340, Feb. 1980. E. Sun, J. Moll, J. Berger, and B. Alders, “Breakdown mechanism in short-channel MOS transistors,” in IEDM Tech. Dig., pp. 478-482,1978. R. S. Muller and T. I. Kamins, Device Electronics for Integrated Circuits. New York: Wiley, 1977, pp. 128-133. A. W. Wieder, C. Werner, and J. Tihanyi, “2-D analysis of the negative resistance region of vertical power MOS-transistors,” in IEDM Tech. Dig., pp. 95-99,1980. C. Hu, “A parametric study of power MOSFETs,” in Rec. of IEEE Power Electronics Specialists Conf., pp. 385-395, June 1979. R. D. Josephy, ‘“OS transistors for power amplification in the HF band,” Philips Tech. Review, vol. 31, no. 71819, p. 251, 1970. T. Toyabe, K. Yamaguchi, S. Asai, and M. Mock, “A numerical model of avalanche breakdown in MOSFET’s,” IEEE Zkzns. Electron Devices, vol. ED-25, p. 825, 1978. R. Sevens, “The power MOSFET, a breakthrough in power device technology,” Intersil Inc., Application Bull. A033, 1980. R. H. Dennard, F. H. Gaensslen, E. J. Walker, and P. W. Cook, “1-pm MOSFET VLSI technology: Part 11-device designs and characteristics for high performance logic applications,” IEEE Trans. Electron Devices, vol. ED-26, no. 4, pp. 325-333, 1979.

M’- 1 -(%r (M- l)=G(M- 1)

l e p is the hole current injected into the emitter, and

Ip is the total hole current generated at the collector junction by impact ionization and is divided between the rb path and the emitter diode whose admittance is qIJkT. A combination of (B-1) and (B-4) yields

03-71

From (B-7), (8), and (B-3), K at snap-back is approximated to be

second breakdown of vertical power mosfet's

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