se-ir corporation 11/04 goleta, ca (805) 571-6800 camira tm se-ir corporation 87 santa felicia dr....

SE-IR Corporation 11/04Goleta, CA (805) 571-6800

CamIRaTM

SE-IR Corporation

87 Santa Felicia Dr.

Goleta, CA 93117

(805) 571-6800


CamIRaTM

General System Architecture

DSP

frame grabber

FPAor

CCD

CamIRa head

Pattern generator

PC


CamIRaTM

Camera Head architecture

BIAS cards

Voltage References

high speed A/D cards

Clock driver cards

Linearpower supplies

BA

CK

PL

AN

E

LV

DS

IN

CL

OC

KS

LV

DS

IN

CO

NT

RO

LS

LV

DS

OU

T

VID

EO

Analog pixel offsetor trigger card


Typical A/D channel Architecture

Bufferstage

optionalcurrent source

offsetstage

Prog.gainstage

A/D

Controllogic

Bufferstage

Bufferstage

input

programmableOffset voltage

GainSelect

(4 programmable)

VoltageReference

digi

tal o

utpu

tto

bac

kpla

ne

High, medium, low gain select 14 bit 10 and 20 MSPS16 bit 2 MSPS

1, 2 and 4 channels cards available


CamIRaTM Clock drivers Architecture

Clock inputto

clock channel output

selection matrix

clockchannel 1

clockchannel 4

slew rate control(each channel)

clock rails(each channel)


CamIRaTM Clock drivers

• Settable high/low clock rails for each ch.– Settable rail voltage range: +/-10V– Min. rail to rail voltage: .25V– Max rail to rail voltage: 20V

• Slew rate is adjustable for each channel– max. slew rate : 1 nsec/V– min. slew rate : 20 nsec/V


CamIRaTM Analog pixel offset

Bufferstages

Addresscounters

offsetsumming

stage

analogoutputbuffer

Trigger/Syncinputs

10 bit100MHz

DAC

512Kx16SRAM

global offset

8 bi

t dig

ital

outp

ut p

ort

High, medium, low range select

OffsetControl

logic

Controllogic

Reference voltage

Digitalcontrol

bus

Offset clocks


CamIRaTM Bias supplies Architecture

biassupply 1

biassupply 5

biassupply 4

biassupply 2

voltage referencebuffer

blockselectable

output

blockselectable

output


CamIRaTM Bias supplies

• Adjustable bias supply voltage: +/- 10V

• Max. current: 125mA per bias supply

• Selectable inline resistors for current measurement

• Common high precision voltage reference for all bias supplies

• Buffered outputs for channel to channel isolation


CamIRaTM

Voltage References Architecturehigh prescision10V reference

12 bitQUAD

OFFSETVOLTAGE

DACsfor

A/Ds

A/Dreferences

Biasreferences

CONTROLLOGIC

4 posgain select4 channels

Currentsource

references


CamIRaTM DSP architeciture

camera headcontrol

opt.Proc.

coef.list

NUCGi*(Xi+Bi) + Ci

coef.lists

dualmemorybuffers

pixelreorder

listdownload

andframe capture

memory

USB 2.0 interface

16 bit digital videoLVDS/TTL parallel

output

LV

DS

/CM

OS

/TT

L in

LV

DS

out


CamIRaTM DSP

• Single PCI slot card format, USB2.0 control

• up to 80 MHz pixel rate

• 16 bit inputs and outputs

• Scalable bit arithmetic

• 16 bit normalized result

• Coef. lists are 2M pixels long (4M opt.)

• Arbitary pixel re-ordering allows mirror,rotation and bad pixel replacement


CamIRaTM DSP cont’d

• 16 bit frame capture memory

• synchronous downloads of memory lists

• Optional processing or display module

• Data stream used dedicated pipeline( PC bus is not used for data stream)


CamIRaTM

Pattern Generator architecture

Integrationcontrol

4 ch

PatternMemory

512kx

32

Operandmemory

Instructiondecoder

Pat

tern

mem

ory

addr

ess

coun

ter

Jmp reg 1Jmp reg 2

Counter 1Counter 2Counter 3

USB 2.0 interface

LV

DS

dri

vers

A/Ddelays4 ch

4

44

10

18

ClockSynthesizer.02-80MHz

Instructionmemory

Instructionaddresscounter

Ext. status (4 ch)


CamIRaTM Pattern Generator

• Single AT slot card

• .01 to 80MHz clock synthesizer

• 26 clock lines– 18 general purpose clocks– 4 A/D conversion clocks (programmable delay)– 4 integration clocks (programmable duty cycle)

• 512K subpattern memory


CamIRaTM Pattern Generator cont’d

• Clock patterns defined as subpatterns

• Subpattern sequencing controlled by program instructions

• Memory usage:– Typical clock program for 640x480 FPA

• 160-200 pattern words

• 400-600 executable instructions


CamIRaTM Pattern generator cont’d

• Controllable polarity on all clocks

• Programmable integration clocks without reloading timing patterns

• A/D clock delays programmable– 2 nsec to 512 nsec in 2 nsec increments

• External status lines for synchronizationto external event

se-ir corporation 11/04 goleta, ca (805) 571-6800 camira tm se-ir corporation 87 santa felicia dr....

Documents