Scoreboarding & Tomasulo’s Approach

Bazat pe slide-urile lui Vincent H. Berk

Scoreboarding

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Figure A.51 The basic structure of a DLX processor with a scoreboard

Scoreboard

Integer unit

FP add

FP divide

FP mult

FP mult

Registers Data buses

Control/statusControl/status

Scoreboard

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Four Stages of Scoreboard Control: ISSUE

1. Issue: decode instructions & check for structural hazards (ID1)If a functional unit for the instruction is free and no other active instruction has the same destination register (WAW), the scoreboard issues the instruction to the functional unit and updates its internal data structure. If a structural or WAW hazard exists, then the instruction issue stalls, and no further instructions will issue until these hazards are cleared.

Algorithm: Assure In-Order issue Multiple issues per cycle are allowed Check if Destination Register is already reserved for writing

(WAW) Check if Read-Operand stage of Functional Unit is free (Structural)

5/43Four Stages of Scoreboard Control:READ-OPERANDS

2. Read operands: wait until no data hazards, then read operands (ID2) – First Functional Pipeline StageA source operand is available if no earlier issued active instruction is going to write it, or if the register containing the operand is being written by a currently active functional unit. When the source operands are available, the scoreboard tells the functional unit to proceed to read the operands from the registers and begin execution. The scoreboard resolves RAW hazards dynamically in this step, and instructions may be sent into execution out of order.

Algorithm: Wait for operands to become available, Register Result Status

(RAW) Operand Caching is allowed Forwarding from another WB stage is allowed

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Four Stages of Scoreboard Control – ex + write

3. Execution: operate on operands (EX) The functional unit begins execution upon receiving operands.

When the result is ready, it notifies the scoreboard that it has completed execution. This stage can be (sub-)pipelined.

4. Write result: finish execution (WB) Once the scoreboard is aware that the functional unit has

completed execution, the scoreboard checks for WAR hazards. If none, it writes results. If WAR, it stalls the instruction.

Algorithm: Delay write until all Rj and Rk fields for this register are marked as

either cached or read. If caching of operands is done: forward answer right away. If not, wait until all operands are read before writing.

Forward answers to units waiting for this write for their operand.

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Three Parts of the Scoreboard

1. Instruction status Indicates which of 4 steps the instruction is in.

2. Functional unit status Indicates the state of the functional unit (FU). 9 fields for each

functional unit Busy – Indicates whether the unit is busy or not Op – Operation to perform in the unit (e.g., + or -) Fi – Destination register Fj, Fk – Source-register numbers Qj, Qk – Functional units producing source registers Fj, Fk Rj, Rk – Flags indicating when Fj, Fk are available and not

yet read. (Alternatively: read and cached)

3. Register result status: Indicates which functional unit will write each register, if

one exists. Blank when no pending instructions will write that register.

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Scoreboard Example Cycle 1

Instruction status Read Execution Write

Instruction j k Issue operands complete Result

LD F6 34 R2 1LD F2 45 R3MULTD F0 F2 F4 Clock 1SUBD F8 F6 F2DIVD F10 F0 F6ADDD F6 F8 F2

Functional unit status dest S1 S2 FU for j FU for k Fj? Fk?

Name Busy Op Fi Fj Fk Qj Qk Rj RkInteger Yes Load F6 R2 YesMult1 NoMult2 NoAdd NoDivide No

Register result statusF0 F2 F4 F6 F8 F10 F12 ... F30

FU Int

R2 has not been read/cached until cycle 2!!!

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Scoreboard Example Cycle 2

Instruction status Read Execution Write

Instruction j k Issue operands complete Result

LD F6 34 R2 1 2LD F2 45 R3MULTD F0 F2 F4 Clock 2SUBD F8 F6 F2DIVD F10 F0 F6ADDD F6 F8 F2

Functional unit status dest S1 S2 FU for j FU for k Fj? Fk?

Name Busy Op Fi Fj Fk Qj Qk Rj RkInteger Yes Load F6 R2 YesMult1 NoMult2 NoAdd NoDivide No

Register result statusF0 F2 F4 F6 F8 F10 F12 ... F30

FU Int

Issue 2nd LD or MULT?

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Scoreboard Example Cycle 4

Instruction status Read Execution Write

Instruction j k Issue operands complete Result

LD F6 34 R2 1 2 3 4LD F2 45 R3MULTD F0 F2 F4 Clock 4SUBD F8 F6 F2DIVD F10 F0 F6ADDD F6 F8 F2

Functional unit status dest S1 S2 FU for j FU for k Fj? Fk?

Name Busy Op Fi Fj Fk Qj Qk Rj RkInteger Yes Load F6 R2 NoMult1 NoMult2 NoAdd NoDivide No

Register result statusF0 F2 F4 F6 F8 F10 F12 ... F30

FU Int

Yes

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Scoreboard Example Cycle 5

Instruction status Read Execution Write

Instruction j k Issue operands complete Result

LD F6 34 R2 1 2 3 4LD F2 45 R3 5MULTD F0 F2 F4 Clock 5SUBD F8 F6 F2DIVD F10 F0 F6ADDD F6 F8 F2

Functional unit status dest S1 S2 FU for j FU for k Fj? Fk?

Name Busy Op Fi Fj Fk Qj Qk Rj RkInteger Yes Load F2 R3 YesMult1 NoMult2 NoAdd NoDivide No

Register result statusF0 F2 F4 F6 F8 F10 F12 ... F30

FU Int

SUPERSCALAR: Issue MULTD?

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Scoreboard Example Cycle 6

Instruction status Read Execution Write

Instruction j k Issue operands complete Result

LD F6 34 R2 1 2 3 4LD F2 45 R3 5 6MULTD F0 F2 F4 6 Clock 6SUBD F8 F6 F2DIVD F10 F0 F6ADDD F6 F8 F2

Functional unit status dest S1 S2 FU for j FU for k Fj? Fk?

Name Busy Op Fi Fj Fk Qj Qk Rj RkInteger Yes Load F2 R3 YesMult1 Yes Mult F0 F2 F4 Int No YesMult2 NoAdd NoDivide No

Register result statusF0 F2 F4 F6 F8 F10 F12 ... F30

FU Mult1 Int

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Scoreboard Example Cycle 7

Instruction status Read Execution Write

Instruction j k Issue operands complete Result

LD F6 34 R2 1 2 3 4LD F2 45 R3 5 6 7MULTD F0 F2 F4 6 Clock 7SUBD F8 F6 F2 7DIVD F10 F0 F6ADDD F6 F8 F2

Functional unit status dest S1 S2 FU for j FU for k Fj? Fk?

Name Busy Op Fi Fj Fk Qj Qk Rj RkInteger Yes Load F2 R3 NoMult1 Yes Mult F0 F2 F4 Int No YesMult2 NoAdd Yes Sub F8 F6 F2 Int Yes NoDivide No

Register result statusF0 F2 F4 F6 F8 F10 F12 ... F30

FU Mult1 Int Add

Read multiply operands? DIVD could have been issued on this cycle.

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Scoreboard Example Cycle 8a

Instruction status Read Execution Write

Instruction j k Issue operands complete Result

LD F6 34 R2 1 2 3 4LD F2 45 R3 5 6 7MULTD F0 F2 F4 6 Clock 8SUBD F8 F6 F2 7DIVD F10 F0 F6 8ADDD F6 F8 F2

Functional unit status dest S1 S2 FU for j FU for k Fj? Fk?

Name Busy Op Fi Fj Fk Qj Qk Rj RkInteger Yes Load F2 R3 YesMult1 Yes Mult F0 F2 F4 Int No YesMult2 NoAdd Yes Sub F8 F6 F2 Int Yes NoDivide Yes Div F10 F0 F6 Mult1 No Yes

Register result statusF0 F2 F4 F6 F8 F10 F12 ... F30

FU Mult1 Int Add Div

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Scoreboard Example Cycle 8b

Instruction status Read Execution Write

Instruction j k Issue operands complete Result

LD F6 34 R2 1 2 3 4LD F2 45 R3 5 6 7 8MULTD F0 F2 F4 6 Clock 8SUBD F8 F6 F2 7DIVD F10 F0 F6 8ADDD F6 F8 F2

Functional unit status dest S1 S2 FU for j FU for k Fj? Fk?

Name Busy Op Fi Fj Fk Qj Qk Rj RkInteger NoMult1 Yes Mult F0 F2 F4 Yes YesMult2 NoAdd Yes Sub F8 F6 F2 Yes YesDivide Yes Div F10 F0 F6 Mult1 No Yes

Register result statusF0 F2 F4 F6 F8 F10 F12 ... F30

FU Mult1 Add Div

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Scoreboard Example Cycle 9

Instruction status Read Execution Write

Instruction j k Issue operands complete Result

LD F6 34 R2 1 2 3 4LD F2 45 R3 5 6 7 8MULTD F0 F2 F4 6 9 Clock 9SUBD F8 F6 F2 7 9DIVD F10 F0 F6 8ADDD F6 F8 F2

Functional unit status dest S1 S2 FU for j FU for k Fj? Fk?

Name Busy Op Fi Fj Fk Qj Qk Rj RkInteger NoMult1 Yes Mult F0 F2 F4 Yes YesMult2 NoAdd Yes Sub F8 F6 F2 Yes YesDivide Yes Div F10 F0 F6 Mult1 No Yes

Register result statusF0 F2 F4 F6 F8 F10 F12 ... F30

FU Mult1 Add Div

Issue ADDD?

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Scoreboard Example Cycle 11

Instruction status Read Execution Write

Instruction j k Issue operands complete Result

LD F6 34 R2 1 2 3 4LD F2 45 R3 5 6 7 8MULTD F0 F2 F4 6 9 Clock 11SUBD F8 F6 F2 7 9 11DIVD F10 F0 F6 8ADDD F6 F8 F2

Functional unit status dest S1 S2 FU for j FU for k Fj? Fk?

Name Busy Op Fi Fj Fk Qj Qk Rj RkInteger NoMult1 Yes Mult F0 F2 F4 Yes YesMult2 NoAdd Yes Sub F8 F6 F2 Yes YesDivide Yes Div F10 F0 F6 Mult1 No Yes

Register result statusF0 F2 F4 F6 F8 F10 F12 ... F30

FU Mult1 Add Div

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Scoreboard Example Cycle 12

Instruction status Read Execution Write

Instruction j k Issue operands complete Result

LD F6 34 R2 1 2 3 4LD F2 45 R3 5 6 7 8MULTD F0 F2 F4 6 9 Clock 12SUBD F8 F6 F2 7 9 11 12DIVD F10 F0 F6 8ADDD F6 F8 F2

Functional unit status dest S1 S2 FU for j FU for k Fj? Fk?

Name Busy Op Fi Fj Fk Qj Qk Rj RkInteger NoMult1 Yes Mult F0 F2 F4 Yes YesMult2 NoAdd NoDivide Yes Div F10 F0 F6 Mult1 No Yes

Register result statusF0 F2 F4 F6 F8 F10 F12 ... F30

FU Mult1 Div

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Scoreboard Example Cycle 13

Instruction status Read Execution Write

Instruction j k Issue operands complete Result

LD F6 34 R2 1 2 3 4LD F2 45 R3 5 6 7 8MULTD F0 F2 F4 6 9 Clock 13SUBD F8 F6 F2 7 9 11 12DIVD F10 F0 F6 8ADDD F6 F8 F2 13

Functional unit status dest S1 S2 FU for j FU for k Fj? Fk?

Name Busy Op Fi Fj Fk Qj Qk Rj RkInteger NoMult1 Yes Mult F0 F2 F4 Yes YesMult2 NoAdd Yes Add F6 F8 F2 Yes YesDivide Yes Div F10 F0 F6 Mult1 No Yes

Register result statusF0 F2 F4 F6 F8 F10 F12 ... F30

FU Mult1 Add Div

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Scoreboarding Summary

Limitations of CDC 6600 scoreboard No forwarding hardware Limited to instructions in basic block (small

window) Small number of functional units (structural

hazards), especially integer/load/store units Do not issue if structural or WAW hazards Wait for WAR hazards Imprecise exceptions

Key idea: Allow instructions behind stall to proceed Decode issue instructions and read operands Enables out-of-order execution out-of-order

completion

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Scoreboarding Summary Modern Day Improvements:

All operands are cached as soon as available Forwarding Pipelining Functional Units Microcoding, eg. IA32 (widens execution window) More precise exceptions In order retirement Works best with tons of actual registers

Tomasulo approach: Reservation stations vs. Forwarding and Caching Temporary Registers work as many virtual registers

Tomasulo’s Approach

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Hardware Schemes for ILP

Key idea: Allow instructions behind stall to proceed Decode => issue instructions and read operands Enables out-of-order execution => out-of-order

completion Why in hardware at run time?

Works when dependence is not known at run time Simplifies compiler Allows code for one machine to run well on another

Out-of-order execution divides ID stage: Issue — decode instructions, check for structural

hazards Read operands — wait until no data hazards, then

read operands

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Tomasulo’s Algorithm For IBM 360/91 about 3 years after CDC 6600 Goal: High performance without special compilers Differences between IBM 360 & CDC 6600 ISA

IBM has only 2 register specifiers/instruction vs. 3 in CDC 6600 IBM has 4 FP registers vs. 8 in CDC 6600

Differences between Tomasulo’s Algorithm & Scoreboard Control & buffers (called “reservation stations”) distributed with

functional units vs. centralized in scoreboard Registers in instructions replaced by pointers to reservation station

buffer HW renaming of registers to avoid WAR, WAW hazards Common data bus (CDB) broadcasts results to functional units Load and stores treated as functional units as well

Alpha 21264, HP 8000, MIPS 10000, Pentium III, PowerPC 604, ...

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Three Stages of Tomasulo Algorithm

1. Issue: Get instruction from FP operation queue

If reservation station free, issues instruction & sends operands (renames registers).

2. Execution: Operate on operands (EX)

When operands ready then execute; if not ready, watch common data bus for result.

3. Write result: Finish execution (WB)

Write on common data bus to all awaiting units; mark reservation station available.

Common data bus: data + source (“come from” bus)

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Tomasulo Organization

FP Adders

Common data bus (CDB)

From Memory

FP Registers

Load Buffers

From Instruction Unit

Operand Bus

Store Buffers

To Memory

FP Multipliers

FP Op Queue

Operation Bus

Reservation Stations

FP Mul Res. Station

FP Add Res. Station

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Reservation Station ComponentsOp – Operation to perform in the unit (e.g., + or – )

Qj, Qk – Reservation stations producing source registers

Vj, Vk – Value of source operands

Rj, Rk – Flags indicating when Vj, Vk are ready

Busy – Indicates reservation station and FU is busy

Register result status Indicates which functional unit will write each register, if one

exists. Blank when no pending instructions will write that register.

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Tomasulo Example Cycle 1

Instruction status Execution WriteInstruction j k Issue complete Result Busy AddressLD F6 34 R2 1 Load1 Yes 34+R2LD F2 45 R3 Load2 NoMULTD F0 F2 F4 Load3 NoSUBD F8 F6 F2DIVD F10 F0 F6ADDD F6 F8 F2Reservation Stations S1 S2 RS for j RS for k

Name Busy OpAdd1 No

Add2 No Clock 1Add3 NoMult1 NoMult2 No

Register result status

F0 F2 F4 F6 F8 F10 F12 ... F30FU Load1

Vj Vk Qj Qk

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ENGS 116 Lecture 8 29Tomasulo Example Cycle 2

Instruction status Execution WriteInstruction j k Issue complete Result Busy AddressLD F6 34 R2 1 Load1 Yes 34+R2LD F2 45 R3 2 Load2 Yes 45+R3MULTD F0 F2 F4 Load3 NoSUBD F8 F6 F2DIVD F10 F0 F6ADDD F6 F8 F2Reservation Stations S1 S2 RS for j RS for k

Name Busy OpAdd1 No

Add2 No Clock 2Add3 NoMult1 NoMult2 No

Register result status

F0 F2 F4 F6 F8 F10 F12 ... F30FU Load2 Load1

Vj Vk Qj Qk

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Tomasulo Example Cycle 3

Instruction status Execution WriteInstruction j k Issue complete Result Busy AddressLD F6 34 R2 1 3 Load1 Yes 34+R2LD F2 45 R3 2 Load2 Yes 45+R3MULTD F0 F2 F4 3 Load3 NoSUBD F8 F6 F2DIVD F10 F0 F6ADDD F6 F8 F2Reservation Stations S1 S2 RS for j RS for k

Name Busy OpAdd1 No

Add2 No Clock 3Add3 NoMult1 Yes MULTD R(F4) Load2Mult2 No

Register result status

F0 F2 F4 F6 F8 F10 F12 ... F30FU Mult1 Load2 Load1

Vj Vk Qj Qk

Register names are renamed in reservation stations

Load1 completing — who is waiting for Load1?

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Tomasulo Example Cycle 4

Instruction status Execution WriteInstruction j k Issue complete Result Busy AddressLD F6 34 R2 1 3 4 Load1 NoLD F2 45 R3 2 4 Load2 Yes 45+R3MULTD F0 F2 F4 3 Load3 NoSUBD F8 F6 F2 4DIVD F10 F0 F6ADDD F6 F8 F2Reservation Stations S1 S2 RS for j RS for k

Name Busy OpAdd1 Yes SUBD M(34+R2) Load2

Add2 No Clock 4Add3 NoMult1 Yes MULTD R(F4) Load2Mult2 No

Register result status

F0 F2 F4 F6 F8 F10 F12 ... F30FU Mult1 Load2 M(34+R2) Add1

Vj Vk Qj Qk

Load2 completing — who is waiting for it?

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Tomasulo Example Cycle 5

Instruction status Execution WriteInstruction j k Issue complete Result Busy AddressLD F6 34 R2 1 3 4 Load1 NoLD F2 45 R3 2 4 5 Load2 NoMULTD F0 F2 F4 3 Load3 NoSUBD F8 F6 F2 4DIVD F10 F0 F6 5ADDD F6 F8 F2Reservation Stations S1 S2 RS for j RS for k

Name Busy OpAdd1 Yes SUBD M(34+R2) M(45+R3)

Add2 No Clock 5Add3 NoMult1 Yes MULTD M(45+R3) R(F4)Mult2 Yes DIVD M(34+R2) Mult1

Register result status

F0 F2 F4 F6 F8 F10 F12 ... F30FU Mult1 M(45+R3) Add1 Mult2

Vj Vk Qj Qk

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Tomasulo Example Cycle 6

Instruction status Execution WriteInstruction j k Issue complete Result Busy AddressLD F6 34 R2 1 3 4 Load1 NoLD F2 45 R3 2 4 5 Load2 NoMULTD F0 F2 F4 3 Load3 NoSUBD F8 F6 F2 4DIVD F10 F0 F6 5ADDD F6 F8 F2 6Reservation Stations S1 S2 RS for j RS for k

Name Busy OpAdd1 Yes SUBD M(34+R2) M(45+R3)

Add2 Yes ADDD M(45+R3) Add1 Clock 6Add3 NoMult1 Yes MULTD M(45+R3) R(F4)Mult2 Yes DIVD M(34+R2) Mult1

Register result status

F0 F2 F4 F6 F8 F10 F12 ... F30FU Mult1 Add2 Add1 Mult2

Vj Vk Qj Qk

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Tomasulo Summary

Reservation stations: renaming to larger set of registers + buffering source operands Prevents registers as bottleneck Avoids WAR, WAW hazards of scoreboard Allows loop unrolling in HW

Not limited to basic blocks (integer units get ahead, beyond branches)

Lasting Contributions Dynamic scheduling Register renaming Load/store disambiguation

360/91 descendants are Pentium III; PowerPC 604; MIPS R10000; HP-PA 8000; Alpha 21264

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Tomasulo with Speculation

1. Issue – Empty reservation station and an empty ROB slot. Send operands to reservation station from register file or from ROB. This stage is often referred to as: dispatch

2. Execute – Monitor CDB for operands, check RAW hazards. When both operands are available, then execute.

3. Write Result – When available, write result to CDB through to ROB and any waiting reservation stations. Stores write to value field in ROB.

4. Commit – Three cases:• Normal Commit: write registers, in order commit• Store: update memory• Incorrect branch: flush ROB, reservation stations and

restart execution at correct PC

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Now, for the grand finale

Let’s compare!!!

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Figure A.51 The basic structure of a DLX processor with a scoreboard

Scoreboard

Integer unit

FP add

FP divide

FP mult

FP mult

Registers Data buses

Control/statusControl/status

Scoreboard

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Tomasulo Organization

FP Adders

Common data bus (CDB)

From Memory

FP Registers

Load Buffers

From Instruction Unit

Operand Bus

Store Buffers

To Memory

FP Multipliers

FP Op Queue

Operation Bus

Reservation Stations

FP Mul Res. Station

FP Add Res. Station

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Scoreboard Example Cycle 6

Instruction status Read Execution Write

Instruction j k Issue operands complete Result

LD F6 34 R2 1 2 3 4LD F2 45 R3 5 6MULTD F0 F2 F4 6 Clock 6SUBD F8 F6 F2DIVD F10 F0 F6ADDD F6 F8 F2

Functional unit status dest S1 S2 FU for j FU for k Fj? Fk?

Name Busy Op Fi Fj Fk Qj Qk Rj RkInteger Yes Load F2 R3 YesMult1 Yes Mult F0 F2 F4 Int No YesMult2 NoAdd NoDivide No

Register result statusF0 F2 F4 F6 F8 F10 F12 ... F30

FU Mult1 Int

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Tomasulo Example – cycle 6

Instruction status Execution WriteInstruction j k Issue complete Result Busy AddressLD F6 34 R2 1 3 4 Load1 NoLD F2 45 R3 2 4 5 Load2 NoMULTD F0 F2 F4 3 Load3 NoSUBD F8 F6 F2 4DIVD F10 F0 F6 5ADDD F6 F8 F2 6Reservation Stations S1 S2 RS for j RS for k

Name Busy OpAdd1 Yes SUBD M(34+R2) M(45+R3)

Add2 Yes ADDD M(45+R3) Add1 Clock 6Add3 NoMult1 Yes MULTD M(45+R3) R(F4)Mult2 Yes DIVD M(34+R2) Mult1

Register result status

F0 F2 F4 F6 F8 F10 F12 ... F30FU Mult1 Add2 Add1 Mult2

Vj Vk Qj Qk

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Differences between Tomasulo’s Algorithm & Scoreboard

Control & buffers (“reservation stations”) distributed with functional units

Registers in instructions replaced by pointers to reservation station buffer

HW renaming of registers to avoid WAR, WAW hazards

Common data bus (CDB) broadcasts results to functional units

Load and stores treated as functional units as well

Stages: Issue, Execution, Write result

Control & buffers centralized

Use actual registers

Do not issue if structural or WAW hazards

Wait for WAR hazards

Forwarding?

Stages: Issue, Read operands, Execution, Write result

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