www.elsevier.com/locate/sse

Solid-State Electronics 49 (2005) 695–701

Scaling CMOS: Finding the gate stack with the lowest leakage current

Thomas Kauerauf a,b,*, Bogdan Govoreanu a,b, Robin Degraeve a,Guido Groeseneken a,b, Herman Maes a,b

a IMEC, Kapeldreef 75, B-3001 Leuven, Belgiumb KU Leuven, Kasteelpark Arenberg 10, B-3001 Leuven, Belgium

Received 29 June 2004

The review of this paper was arranged by Prof. S. Cristoloveanu

Abstract

In order to reduce the gate leakage current, high-k gate dielectrics are expected to replace SiO2 in future CMOS generations.

Many of these novel dielectrics are stacks of a thin SiO2 and a high-k layer. We present a theoretical study that aims at identifying

the combination of the stack architecture and high-k material with the lowest leakage current. In the first part of this work the leak-

age current through high-k double stacks with various thicknesses, materials and gate electrodes is calculated assuming tunneling

only. We discuss the difference between gate and substrate injection and show quantitatively the impact of interfacial layer thickness,

barrier height, k-value and the work function of the gate material on the tunneling current. In the second part the material properties

are no longer considered to be independent and with the universal relation between k-value and barrier height introduced, we are

able to identify what material suits best all requirements. The leakage current is calculated for different EOTs and we demonstrate

that if all dielectrics follow this universal relation, for a fixed thickness there exists one material, which gives a minimum gate leakage

current. It is concluded that even for sub 1 nm EOT devices the k-value has not to exceed �25 and ZrO2 or HfO2 come closest to the

ideal high-k if only leakage current issues are considered.

� 2005 Elsevier Ltd. All rights reserved.

Keywords: High-k; Gate dielectric; Leakage current; k-Value; Barrier height

1. Introduction

To increase the transistor performance and to fulfillthe CMOS scaling laws, every new technology node re-

quires a reduction of the gate oxide thickness. In the

past this was achieved by simply depositing a thinner

SiO2 dielectric and more recently SiON has been intro-

duced as gate dielectric. In the latest most advanced

high-performance devices, oxides with a thickness down

to 1.4 nm are used in production. In the following years

this scaling will continue and in Fig. 1 an overview of

0038-1101/$ - see front matter � 2005 Elsevier Ltd. All rights reserved.

doi:10.1016/j.sse.2005.01.018

* Corresponding author. Address: IMEC, Kapeldreef 75, B-3001

Leuven, Belgium.

E-mail address: kauerauf@imec.be (T. Kauerauf).

some important parameters according to the ITRS

(The International Technology Roadmap for Semicon-

ductors) roadmap [1] is given.A major penalty of reduced oxide thickness is the in-

crease in gate leakage currents. At operating voltage the

stack is in the direct tunneling regime and the current

increases exponentially with decreasing oxide thickness.

For sub-1.5 nm Equivalent Oxide Thickness (EOT) this

leads to enormous current densities and high power dis-

sipation. Especially for mobile application this is

unacceptable.Presently, high-k gate dielectrics are aggressively

developed to replace SiO2/SiON in order to reduce gate

leakage currents with a physically thicker layer while

still scaling the EOT in future CMOS generations.

Fig. 1. Excerpt taken from the ITRS showing the trends in gate length,

operating voltage and oxide thickness. Especially for high performance

applications (MPU), the scaling is very aggressive.

696 T. Kauerauf et al. / Solid-State Electronics 49 (2005) 695–701

Several materials like Al2O3 and ZrO2 were investigated,

but recently HfO2 [5] and particularly HfSiON [2–4]

showed the most promising results. There the extracted

k-values generally range between 12 and 18, depending

on the Si and Hf content, respectively. These materials

were chosen for processing compatibility reasons and

especially HfSiON for the integration with poly-Si elec-

trodes with a high thermal budget during the activationanneal. With the introduction of metal gates, several

other candidate materials may become viable options.

Considering new gate dielectric materials, there exists

a common misconception that higher k-values will auto-

matically lead to lower leakage current, but leakage cur-

rent is not only determined by the k-value. In this work,

a systematic analysis of the impact of the interfacial

layer thickness, capping layers, k-value, barrier heightand gate work function is done in order to determine

the optimal choice of gate dielectric from a leakage cur-

rent point of view. It is shown that a strong asymmetry

exists between gate and substrate injection, and that

small changes of the dielectric properties may have a

large impact on the leakage current.

Fig. 2. The energy band diagram in flatband condition with Ec the Si

conduction band, Ev the Si valence band, Ef the semiconductor Fermi

level, Ei the intrinsic Fermi level, Eg the band gap, us the semicon-

ductor work function, um the metal work function, ub,1 the potential

barrier for the interface and ub,2 for the high-k, ums the work function

difference and v the semiconductor electron affinity. The EOT of the

stack is 1.6 nm with p-Si substrate, 1 nm interfacial SiO2, 3 nm high-k

dielectric (k = 20, ub,2 = 1.5 eV) and a mid gap metal gate electrode.

2. Simulation model and the dual-layer stack

In this study, we restricted ourselves to only consider-

ing the leakage due to electron quantum-mechanical

tunneling through defect-free high-k stacks. The calcula-

tions are therefore best-case and can only be reached

with mature processes and in cases where chemical

and atomic properties allow the fabrication of low-de-fect density material.

The tunneling current was calculated using the inde-

pendent electron approximation [6,7], according to

which the tunneling current is the energy integral of

the tunneling probability multiplied by a factor account-

ing for the occupation probability and the density of

states in the electrodes:

J ¼ qm�

2p2�h3

Z 1

0

dEZ E

0

dEkT ðEÞ½f1ðEÞ � f2ðEÞ�

where q is the elementary charge, �h is the reduced Planckconstant, m* the conduction band effective mass, T the

tunneling probability, and f1, f2 are the Fermi–Dirac dis-

tribution functions in the source and destination elec-

trodes, respectively. It is assumed that tunneling is an

energy conserving process. If the parallel momentum

conservation is neglected, the equation may be reduced

to a single integral.

The tunneling probability was calculated using theWentzel–Kramers–Brillouin (WKB) approximation by

either numerical integration or using a Taylor expansion

around the Fermi level in the injecting electrode. Varia-

tions of the dielectric constant, barrier height and effec-

tive mass across several dielectric stacks have been taken

into account. This method gives qualitatively similar re-

sults as compared to the Airy implementation [7] for the

bias and thickness range of interest in this work, and istherefore a useful approach for predicting the trends.

The applied bias Vg relates to the voltage drop across

the stack Vstack through the potential balance equation:

V g ¼ ws þ V stack þ ums � Qox=Cox

V g ¼ ws þ V stack þ V FB

where ws is the surface potential, ums is the metal–semi-

conductor work function and Qox/Cox is the shift in-duced by the interface-equivalent oxide charge density,

in this work set to 0. The band diagram of a MOS struc-

ture at flatband with a high-k dual layer stack is shown

in Fig. 2, At applied bias, the potential distribution

across the stack is calculated using basic electrostatics.

Most of the current high-k gate stacks consist of a

thin interfacial SiO2 or SiON layer, a thicker high-k

layer and either a poly-Si or metal gate. Any applied

-8

-6

-4

-2

0

2

4En

ergy

(eV)

6420Physical thickness (nm)

high-k

SiO2

Fig. 3. The band-diagram of a dual-layer stack with 2 nm EOT, 1 nm

interfacial SiO2 and a 5 nm high-k material with k = 20. This stack is

the starting point for all calculation in this work.

0

2

4

(ev)

e- Vg = 3V

T. Kauerauf et al. / Solid-State Electronics 49 (2005) 695–701 697

gate voltage (Vg) will partly drop over the interfacial

layer and the high-k, whereas the distribution depends

on the physical layer thicknesses and the k-values. Con-

sidering for example a 2 nm EOT stack with 1 nm inter-

facial SiO2 and 5 nm high-k with k = 20, the applied Vg

will equally divide over the two layers. If not mentionedotherwise, in the following calculation this specific stack

with a barrier height ub,2 of the high-k of 1.5 eV and an

n+ poly-Si electrode will be used as a reference stack

(Fig. 3). Moreover, for all the considered dielectric

materials the effective mass has been fixed at 0.5m0.

-8

-6

-4

-2

Ener

gy

6420Physical thickness (nm)

high-kSiO2

Fig. 5. Substrate injection: With a positive bias applied electrons

tunnel from the Si substrate towards the electrode. Already at relative

low voltages electrons start to enter the high-k conduction band and

tunnel only through the interfacial layer.

3. Simulation and discussion: Part I

Assuming applied gate voltages in the range of nor-

mal operating and measurement conditions (jVgj be-

tween 0 and 4 V), in case of gate injection (Vg < 0 V)

the leakage current is determined by electron tunneling

through the high-k and the interfacial layer (Fig. 4).

For the reference stack down to Vg = �3 V the current

is limited by direct tunneling of the electrons through

-6

-4

-2

0

2

4

6

Ener

gy (e

V)

6420Physical thickness (nm)

high-k

SiO2

e-

Vg = -3V

Fig. 4. Gate injection: If a negative bias at the gate is applied electrons

tunnel from the gate electrode through the high-k and then the

interfacial layer.

each entire layer. Only if gate voltages below �3 V are

applied and no energy relaxation is assumed, the current

is determined by Fowler–Nordheim tunneling through

both the high-k and the interfacial layer.

For substrate injection (Vg > 0) the situation is differ-

ent: the electrons tunnel through the interfacial layerand just partly (or even not) through the high-k before

entering the high-k conduction band (Fig. 5). Only if

the gate voltage is below 1.5 V the current is limited

by direct tunneling through the entire stack. In the range

1.5 V < Vg < 3 V the electron flow is determined by di-

rect tunneling through the interfacial layer and Fowler–

Nordheim tunneling through the high-k. Already from

voltages >3 V the electrons do not tunnel through thehigh-k and enter its conduction band directly.

The difference in tunnel barrier results in a very large

asymmetry in leakage for substrate and gate injection.

We calculated the current through stacks with fixed

2 nm EOT for both injection polarities by varying the

interfacial SiO2 layer thickness from 0 nm (no interfacial

SiO2) to 2 nm (no high-k, pure SiO2) and a difference up

to several orders of magnitude was found (Fig. 6).

100

102

104

106

108

1010

1012

J sub

inj /

Jga

te in

j

2.01.51.00.50.0

Interfacial SiO2 in nm (for 2nm EOT)

Vg = 1V Vg = 2V

Fig. 6. In dual-layer stacks for substrate injection the leakage is several

orders of magnitude higher than for gate injection.

Fig. 7. Selected work functions of Si based and metal gate electrodes

divided into p-type, n-type and midgap.1

10-25

10-22

10-19

10-16

10-13

10-10

10-7

J (A

/cm

2 )

3.02.01.00.0

Vstack (V)

ϕm : 4.05 to 5.45 eV

Fig. 8. For gate injection variations of the gate material work function

lead to significant changes in leakage current. Already an increase of

0.2 eV can reduce the leakage by two orders of magnitude.

10-21

10-17

10-13

10-9

10-5

10-1

J (A

/cm

2 )

Vg = 1V

Vg = 2V

698 T. Kauerauf et al. / Solid-State Electronics 49 (2005) 695–701

For different gate materials (poly-Si, fully silicided or

pure metal gates) this effect can be even more pro-

nounced. Depending on the work function for gate

injection the barrier for the electrons can be significantly

larger (see also Fig. 2) and in Fig. 7 an overview of workfunctions for current and possible gate materials is

given.

For a given gate voltage Vg, variations in the gate

work function result in a parallel shift of the IV curve.

But focusing on fixed voltage over the dielectric stack

Vstack, the difference in barrier has a significant impact.

For substrate injection the effect from a variation of

the gate work function on the leakage is minor, butfor gate injection large differences can be observed.

Assuming the stack on Fig. 3 with a metal gate, in

Fig. 8 the leakage currents for gate injection with a var-

iation of the work function from 4.05 eV to 5.45 eV were

calculated. The current density is plotted versus the

stack voltage (Vstack = Vg � ws � VFB). For example at

2 V variation of 0.2 eV lead to differences in current of

up to two orders of magnitude.Those differences have to been taken into account

when potentially replacing poly Si by metal gates, par-

ticularly when mid gap metals are considered. However,

it is clearly shown that the injection polarity and espe-

cially for gate injection, the gate material work function

has a strong impact on the leakage. When comparing

the leakage for different dielectrics, possible differences

are not necessarily due to an improvement or worseningof the stack. Therefore, the entire stack properties and

measurement conditions should be mentioned, espe-

cially for benchmarking.

In the following paragraphs the effect of the stack

architecture and the dielectric itself will be discussed.

There, the thickness of the interfacial layer has large im-

pact on the leakage. Thicker interfacial layers usually

lead to higher mobility and therefore better perfor-

1 The values were taken from literature and internal sources.

Depending on the experiment and the calculation model the values

can strongly vary and the numbers given here are mainly intended to

illustrate the applicable range of work functions.

mance, while processing of ultra thin interfaces

(�0.3 nm) requires more caution, but if for a given

EOT the interface is increased, the high-k layer has to

become thinner. Fig. 9 shows the result of simulations

where the thickness of the SiO2 interface was varied be-

tween 0 and 2 nm, and the current density for each curve

was read off at a gate voltage of 1 V. For this stack with

a fixed EOT of 2 nm, a 0.1 nm reduction of the interfa-cial SiO2 can lead to more than 1 order of magnitude

lower leakage current. However, for higher voltages this

trend must not be necessarily true. Simulation showed

that if the applied gate voltage is larger than the barrier

height of the high-k (e.g. Vhigh-k > 1.5 V and

ub,2 = 1.5 eV) and the current is no longer limited by di-

rect tunneling through the entire stack, the leakage can

be higher with thicker high-k layers (Fig. 9). This is sim-ilar to the effect in the VARIOT tunneling barrier [8],

which was proposed to replace the conventional tunnel

oxide in nonvolatile memory.

One method to improve the stability of the high-k

gate stack especially when using poly-Si gates is the

introduction of SiO2 or SiON capping layers. To inves-

2.01.51.00.50.0

Interfacial SiO2 in nm (for 2 nm EOT)

Fig. 9. For this stack for substrate injection at operating conditions

(Vg = 1 V) every 0.1 nm reduction of the interfacial layer thickness

gives about one order of magnitude in leakage current reduction.

10-10

10-9

10-8

10-7

10-6J

(A/c

m2 )

Capping layer thickness (nm)

substrate injectionEOT: 2 nm

0.50.40.30.20.0 0.1

Fig. 10. For a given EOT additional capping layers on the upper high-

k interface lead to a reduction of the high-k thickness. For 2 nm EOT

this implies a strong current increase, whereas for EOTs around 1 nm

it will be totally impractical.

10-21

10-17

10-13

10-9

10-5

10-1

J (A

/cm

2 )

3.02.52.01.51.00.5

Conduction Band offset (eV)

2 nm EOT1 nm interfacek = 20thigh-k = 5.13 nmVg = 1 V

Fig. 12. For a given k-value and EOT, a 0.1 eV larger barrier can

imply a current reduction up to two orders of magnitude.

T. Kauerauf et al. / Solid-State Electronics 49 (2005) 695–701 699

tigate the effect of this additional layer on the leakage

current, the 2 nm EOT stack was calculated with a

SiO2 capping layer thickness from 0 to 0.5 nm (Fig.10). Similar to a thicker interfacial layer in this case

the thickness of the high-k is sacrificed too, leading to

an obvious current increase. Summarizing, it can be

clearly stated that when designing any high-k gate stack,

from a leakage point of view the interfacial layer thick-

ness has to be kept as thin as possible and capping layers

should be avoided.

Besides stack engineering, the selection of the high-kmaterial affects the gate leakage the most. The first

materials previously considered were mainly coming

from memory applications (Ta2O5, SrTiO3, Al2O3 [8])

or other metal oxides (HfO2, La2O3, TiO2, Y2O3,

ZrO2). The quoted k-values for some candidates went

up to more than 100, but at the moment materials like

HfO2 with k � 20 seem to be the only real choice.

10-16

10-14

10-12

10-10

10-8

10-6

10-4

J (A

/cm

2 )

3025201510k-value

2 nm EOT1 nm interfaceVg = 1 V

Fig. 11. Increasing the k-value of the dielectric on a stack with fixed

EOT allows physically thicker layers. Assuming a constant barrier

height, this leads to significant leakage current reduction.

Even with those moderate k-values significant leak-

age current reductions can be observed, and small in-creases of k lead to further reduction. For the

calculations of the tunneling current through the 2 nm

stack shown in Fig. 11 k ranged from 10 to 30. We

found that by increasing the k-value from 18 to 21

and a fixed barrier height of 1.5 eV the leakage decreases

by as much as two orders of magnitude. This can be ex-

plained by the physically thicker layer and confirms

again the sensitivity to the material and stack properties.Since even slight variations in processing have impact on

the material properties the processing conditions and

there especially the thermal budget have to be selected

very carefully.

Similar observations can be made by a variation of

the barrier height of the high-k. Again assuming our

2 nm EOT stack with a constant k-value of k = 20, at

Vg = 1 V an increase by only 0.1 eV of the barrier im-plies a leakage current reduction of up to two orders

of magnitude (Fig. 12). But one has to be careful: as

mentioned earlier, if the barrier height gets as low as

the operating voltage the leakage increases drastically

and the beneficial effect of the high-k will disappear.

4. Simulation and discussion: Part II

In the first part of the discussion we demonstrated the

effect of the high-k stack architecture and the high-k

material properties, including the k-value and the bar-

rier height on the leakage current independently from

each other.

However, the enormous amount of materials con-

stants found in literature suggests that k-value and con-duction band offset are related. Based on literature data

[9,10] and our own physical and electrical characteriza-

tion results, we collected the parameters of some high-

k materials that recently received most consideration.

The result is shown in Fig. 13, knowing that there might

be small but important variations due to different pro-

10-10

10-8

10-6

10-4

10-2

100

102

104

106

J (A

/cm

2 )

3.02.52.01.51.00.5EOT (nm)

MPU LOP LSTP 0.5 + HfO2 own SiO2 own SiOxNy

Roadmap: VddSimulations: Vstack = 1Vown data: Vg - Vth = 1V

Fig. 15. While SiO2 will not meet the leakage specs of the ITRS, SiON

and in all probability Hf-silicates are suitable for MPU, whereas high-k

dielectrics can be used in low power applications.

4

3

2

1

0

Con

duct

ion-

band

offs

et (e

V)

403020100k-value

SiO2

Si3N4

Al2O3

Y2O3

HfO2 ZrO2

BaZrO3

Ta2O5

Fig. 13. The relation between barrier height and k-value. For most of

the high-k materials with increasing k-value the barrier height

decreases.

700 T. Kauerauf et al. / Solid-State Electronics 49 (2005) 695–701

cessing conditions. Since the values for Hf-silicates

strongly depend on the Hf and Si content, the data are

not included in the graph. Measurements however sug-gest, that there is a linear transition from k-value of

SiO2 to that of HfSiON and similar results are expected

for the barrier height.

From Fig. 13 it becomes clear that there is a universal

relation and an increase in k-value comes along with a

decrease in barrier height and the two parameters can-

not longer be considered independent. To find now the

dielectric material with the lowest leakage (neglectingall possible integration challenges) the current through

our reference stack of 2 nm EOT and 1 nm interfacial

SiO2 using a high-k material with different combination

of k-value and barrier height by walking along the line

in Fig. 13 was calculated (Fig. 14). High leakage

throughout the whole voltage range was clearly

obtained for a pure SiO2 dielectric. With an increasing

k-value the leakage reduces, but when the barrier heightdrops below certain values this remains only true for

10-9

10-7

10-5

10-3

10-1

101

103

105

J (A

/cm

2 )

2.52.01.51.00.5Gate voltage (V)

k-value upBH down

minimum leakageat 1.2V for k = 14and BH = 1.6eV

k = 40φb = 0.6eV

k = 3.9φb = 3.1eV

Fig. 14. The leakage current calculated for different combination of k-

value and barrier height for a stack with 2 nm EOT and an interfacial

thickness of 1 nm. Clearly at a fixed gate voltage an increase of the k-

value does not automatically imply a decrease in leakage current.

very low voltages. Therefore the leakage has to be readof at specific voltages (ideally operating conditions) and

a minimum leakage at Vg = 1.2 V was found for a mate-

rial with k � 14 and a barrier height of 1.6 eV.

To study this trend for thinner stacks, similar calcula-

tions were made for a 1.5 nm EOT layer with an interfa-

cial thickness of 0.5 nm at an operating voltage of

Vg = 1 V. For this stack, the minimum leakage current

was found for a high-k material with k = 18 and a cor-responding barrier height of 1.25 eV. These results let

us conclude, that even for EOTs around and below

1 nm, the k-value of the optimal high-k stack in terms

of leakage current reduction has not to exceed �25, be-

cause the gain in physical thickness would be obliterated

by a too low barrier height. This means that the lowest

leakage current can be reached with an HfO2 or ZrO2

like material. If all dielectric materials are followingthe trend of Fig. 13, there is no further need to search

for ultra high-k materials.

To verify this and to compare our results with the

ITRS (The International TechnologyRoadmap for Semi-

conductors) roadmap [1], in Fig. 15 the simulated leakage

for a stack with 0.5 nm interfacial oxide and HfO2 high-k

is plotted togetherwith our ownmeasured SiO2 and SiON

data and the specifications of the roadmap. While SiONand Hf-silicates with low Hf content might meet the

MPU (micro processor unit) leakage current and perfor-

mance specs, high-k materials are needed to accomplish

the roadmap requirements for LOP (low operation

power) and LSTP (low standby power) applications.

5. Conclusion

A strong asymmetry exists in leakage current between

gate and substrate injection. For a fixed EOT, large ben-

efits in current reduction can already be obtained from a

thinner interfacial layer, a small increase in k-value and

a slight increase in barrier height. From the universal

barrier height vs. k-value relation a minimum leakage

T. Kauerauf et al. / Solid-State Electronics 49 (2005) 695–701 701

current is predicted for an HfO2 or ZrO2 like material.

While SiON and Hf-silicates with low Hf content will

meet the leakage specs for high performance devices,

low power applications are the main driving force for

high-k integration.

Acknowledgement

The authors would like to acknowledge Eduard Car-

tier, Andreas Kerber, Edward Young for helpful discus-

sions and Anabela Veloso for the SiON data.

References

[1] The International Technology Roadmap for Semiconductors.

Available from: http://public.itrs.net.

[2] Lee JC et al. IEDM Tech Dig 2003:95–8.

[3] Koike M et al. IEDM Tech Dig 2003:107–10.

[4] Shanware A et al. IEDM Tech Dig 2003:939–42.

[5] Tsai W et al. IEDM Tech Dig 2003:311–4.

[6] Harrison WA. Phys Rev 1961;123(1):85–9.

[7] Govoreanu B et al. Solid-State Electron 2003;47(6):1045–53.

[8] Govoreanu B et al. IEEE Electron Dev Lett 2003;24(2):99–101.

[9] Wilk GD et al. J Appl Phys 2001;89(10):5243–75.

[10] Peacock PW et al. J Appl Phys 2002;92(8):4712–21.