scalable bipolar transistor modelling with hicum l0
DESCRIPTION
Scalable bipolar transistor modelling with HICUM L0. S. Frégonèse, D. Berger * , T. Zimmer, C. Maneux, P. Y. Sulima, D. Céli * Laboratoire de Microélectronique IXL, FRANCE * ST Microelectronics, FRANCE. Outlines. Introduction Geometry Scaling Modelling strategy Why HICUM L0 ? - PowerPoint PPT PresentationTRANSCRIPT
19 juin 2004
HICUM WORKSHOP 2004
1/25
S. FREGONESE
Scalable bipolar transistor modelling with HICUM L0
S. Frégonèse, D. Berger*, T. Zimmer, C. Maneux, P. Y. Sulima, D. Céli*
Laboratoire de Microélectronique IXL, FRANCE* ST Microelectronics, FRANCE
19 juin 2004
HICUM WORKSHOP 2004
2/25
S. FREGONESE
Outlines• Introduction
– Geometry Scaling– Modelling strategy– Why HICUM L0 ?
• HICUM L0 & L2– Similarity between L2 and L0– L0 equations
• Applications– Extraction – Impact of emitter via resistances– Impact of corner rounding– DC & AC measurement and model comparison
• Conclusion
• Perspectives
19 juin 2004
HICUM WORKSHOP 2004
3/25
S. FREGONESE
Introduction :Geometry scaling
• Transistor modelling with a function of emitter length and width as parameters– Circuit performances optimisation– Model many transistors with one parameter set
• Important parameter for scalable modelling of the internal transistor– Real length and width ( WE0 and LE0 )
• Spacer have to be taken into account– Effective diffusion length under emitter window
C
– Corner rounding• Low size transistor
– SIC window• Internal & external base collector capacitances
modelling• Base Collector current
EB
C
Mask
r0
WE0
C
LE0
19 juin 2004
HICUM WORKSHOP 2004
4/25
S. FREGONESE
Introduction : Modelling Strategy
Scaling level 1 Scaling level 2 Scaling level 3
Scaling rules implanted in a program outside
the model (Tradica [ *] )
simulator preprocessor
language
inside the model
Model card One for each transistor
One for all transistors One for all transistors
Optimisation of circuit performances with W & L
Depends on its implementation in
the design kit
Easy Easy
Modification of scaling rules
Easy with Master Toolkit XMOD*
Easy Easy for research with Verilog A
Link between ICCAP and Model
Easy with Master Toolkit XMOD*
Difficult Very Easy
19 juin 2004
HICUM WORKSHOP 2004
5/25
S. FREGONESE
Introduction : Why HICUM L0 ?
• A new model combining– Simplicity of Gummel Poon:
• Less computational effort (internal nodes number, L0 : 3,L2 : 5)
• Extraction is easier
– Major features of HICUM• Accurate charge description• Self heating is taken into account
• Useful for:– Quick evaluation of the basic circuit functionality– For non critical transistor
19 juin 2004
HICUM WORKSHOP 2004
6/25
S. FREGONESE
HICUM L0 & L2 : Similarity between L0 and L2
• Simplifications– Charge:
• Simplification of charge modelling in transfer current source
• DC and AC are uncorrelated.– Internal base node is suppressed
• External base resistance and internal base resistance are merged together
• External base-emitter capacitance and internal base-emitter capacitance are grouped together
– Current source are merged:• Peripheral and internal base-collector• Peripheral and internal base-emitter
– Others effects:• Substrate network• Parasistic transistor• NQS effects• Base-Emitter tunnelling current source
19 juin 2004
HICUM WORKSHOP 2004
7/25
S. FREGONESE
HICUM L0 & L2 :Similarity between L0 and L2
• AC Charge formulation unchanged– Capacitance formulation– Transit time formulation
• At low & high current• Critical current
• Internal base resistance:
• Temperature dependence & self heating
)(0
biasfrbiri
Geometry dependent zero bias value is unchanged
Bias variation function is simplified
19 juin 2004
HICUM WORKSHOP 2004
8/25
S. FREGONESE
HICUM L0 & L2 : L0 Equations
-Transfer current source in HICUM L2
- Transfert current source in HICUM L0
)exp( ''
,
10
T
EB
TPFT
VV
QCI
rtftjcijcijeijeiPTP QQQhQhQQ 0,
)exp(
***1
* ''
000
Tcf
EB
P
rT
P
fT
P
jcijci
SFT
VmV
QQh
II
)exp(1
* ''
Tcf
EB
QR
TRL
QF
TFL
Ef
jci
SFLT
VmV
II
II
Vq
II
- Low to medium current :
-Low current:
)exp(* ''
Tcf
EBSFLT
VmVII
- Low current:
)exp( ''
0
10
T
EB
jeijeiPFT
VV
QhQCI
2 scalable
parameters
1 scalable parameter 1 constant parameter
19 juin 2004
HICUM WORKSHOP 2004
9/25
S. FREGONESE
HICUM L0 & L2 : L0 Equations
- Charge increase for AC regime:
Same equation as L2
- Charge increase for DC regime:
AC et DC are uncorrelated
²wIQ TFHCSFHAC QFH
TFL
CK
TFLFHlowDCFH
II
IIwq )²(
csEQFHuQFH fAII ),( TFCK IIfw
csECKuCK fAII ),( TFLCKlow IIfw
fe
TFEF
EF
gIQ
1
00
fcs function parameter is extracted from RCI0
extraction
( from AC characteristics)
19 juin 2004
HICUM WORKSHOP 2004
10/25
S. FREGONESE
Applications : Extraction flow
CBE, CBCi, CBCx, CCS
C and Collector current source (Jcu, mcf)
base-emitter & base-collector current source
RE is extracted / RCX, RBX, RBI are calculated from
layer resistivity
Transit time @ low current 0I, 0P, TBVL, DT0H
Critical current parameters
RCI0U, C, VCES, VPT, VLIM
Transit time @ high current EF0, GTE, HCS,
ALHC
DC charge @ high current
IQFHu, FH
19 juin 2004
HICUM WORKSHOP 2004
11/25
S. FREGONESE
Applications : Extraction of Capacitance
• CBE=CBEpuPE0+CBEsuAE0
0
2
4
6
8
0.0 0.2 0.4 0.6 0.8
Area / Perimeter ( µm )
CB
E /
perim
eter
(nF
/m) VBE
CBEpu
CBEsu
0
40
80
120
160
-1.0 -0.5 0.0 0.5
VBE (V)
CB
E (
fF)
0.25*12.65 µm² 0.65*12.65 µm²
1.45*12.65 µm² 0.25*1.45 µm²
0.25*3.05 µm² 0.25*6.25 µm²
19 juin 2004
HICUM WORKSHOP 2004
12/25
S. FREGONESE
Applications : Extraction of C
• IC=JC(WE0+2C)(LE0+2C)
• IC=0 if WE0=-2C
0.0
0.5
1.0
1.5
2.0
-0.5 0.0 0.5 1.0 1.5 2.0
w E0 (µm)
I C (µ
A)
-2C
VBE5
VBE4
VBE3
VBE2
VBE1
Collector current versus emitter width for different VBE and VBC=0 V
(measurement)
EB
C
Mask
r0
WE0
C
LE0
19 juin 2004
HICUM WORKSHOP 2004
13/25
S. FREGONESE
Applications: Extraction of Transit time
• Split into one internal part and into one peripheral part:– Ic=Ii+Ip= JiAE0+JpPE
– Qtotal= Q0i+ Q0P
– Internal charge: Q0i=0iIi
– Peripheral charge: Q0P=0PIP
• Equivalent transit time=Qtotal/Ic
• Scalable model [1] :
1.4
1.6
1.8
2.0
0 5 10 15 20
Emitter area (µm²)
0 (
ps)
extracted value
model
1
23
4 5
67
•Extracted 0 values versus emitter area for different
emitter sizes. (1: 0.25*1.45 µm², 2: 0.25*3.05 µm², 3: 0.25*6.25 µm², 4: 0.25*12.65 µm², 5: 0.25*25.45 µm², 6: 0.65*12.65 µm², 7: 1.45*12.65 µm²)
0
00
00
.1
.1
E
EC
E
EPC
I
AP
AP
[1] Michael Schröeter et al. IEEE solid states circuits,
vol .31, n°10, oct 1996
19 juin 2004
HICUM WORKSHOP 2004
14/25
S. FREGONESE
Applications : Extraction of Critical current parameter
• Critical current– Models the transit frequency
fall- off – Link to Kirk effect
• Collector doping• Internal collector resistance:
• Current spreading in the collector with a C angle
• Scalable model [1] 0
50
100
150
200
250
300
0 5 10 15 20
emitter area (µm²)R
ci0
() extracted Rci0
model
1
6
5
43
2
7
).1.1
ln(
).(.00
cL
cW
CLWEuCICI
WWW
ARR
Extracted RCI0 values versus emitter area for different emitter
sizes. (1: 0.25*1.45 µm², 2: 0.25*3.05 µm², 3: 0.25*6.25 µm², 4: 0.25*12.65 µm², 5: 0.25*25.45 µm², 6: 0.65*12.65 µm², 7: 1.45*12.65 µm²)
0
1CI
CKR
I
0
)tan(.2E
wW
c 0
)tan(.2E
lL
c with
fcs
[1] Michael Schröeter et al. IEEE solid states circuits,
vol .31, n°10, oct 1996
19 juin 2004
HICUM WORKSHOP 2004
15/25
S. FREGONESE
Applications : Impact of vias on the emitter resistance
• Number of vias and emitter width is not proportional:– Simple model doesn’t work( )– Number of vias has to be
calculated versus the width with layout rules:
• WE0 = 0.25 µm Nb_via = 1
• WE0 = 0.65 µm Nb_via = 1
• WE0 = 1.45 µm Nb_via = 21.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
0.70 0.80 0.90 1.00
VBE (V), VBC=0 V
I C, I B
(A
)
Ic mesureIb mesureModel 1Model 2
0E
EUE
ARR
Gummel plot@ VBC =0 V for 3emitter sizes (0.25, 0.65, 1.45*12.65 µm²)
(model 1: taking into account via; model 2: without via) viaNb
RARR via
E
EUE
_0
19 juin 2004
HICUM WORKSHOP 2004
16/25
S. FREGONESE
Applications :Impact of Corner rounding
2422 00 CCECEE rLWA
r
WE0
LE0
C
r C
2))(4
1( CCorner rA
[2]
[2] Michael Schröeter et al. IEEE solid states circuits,
vol .34, n°8, oct 1999
1E-17
1E-16
1E-15
1E-14
0.4 0.5 0.6 0.7 0.8 0.9 1.0
VBE (V)
Ic/e
xp(V
BE
/UT)
(A)
measurement
Schroter r0=we/2
without model
1
2
3
4
5
6
With r0 (maximum value) =WE0/2
Emitter sizes 1: 0.25*0.65 µm², 2: 0.25*1.45 µm², 3: 0.25*3.05 µm², 4: 0.25*6.25 µm², 5: 0.25*12.65 µm², 6: 0.25*25.45 µm²
19 juin 2004
HICUM WORKSHOP 2004
17/25
S. FREGONESE
• Model is not physical• But usefull for low size
4²
2arctan²24
2²22
EE
E
EEEEEEE
WrW
WrrWrWWrrrWWLA
1E-17
1E-16
1E-15
1E-14
0.4 0.5 0.6 0.7 0.8 0.9 1.0
VBE (V)
Ic/e
xp(V
BE
/UT)
(A)
measurement
without model
Schroter r0=we/2
new model r0=150nm
1
2
3
4
5
6
Applications :Impact of Corner rounding
r
Wr E
dxS xr2/
2 2
12
)²2(²arctan42
E
EEE
WrWrr
rLP
S1
r
r
r-wE/20
y
LE
WE
S
Emitter sizes 1: 0.25*0.65 µm², 2: 0.25*1.45 µm², 3: 0.25*3.05 µm², 4: 0.25*6.25 µm², 5: 0.25*12.65 µm², 6: 0.25*25.45 µm²
19 juin 2004
HICUM WORKSHOP 2004
18/25
S. FREGONESE
Applications : DC measurement and model comparisonBiCMOS 0.25 µm from STMicroelectronics
0
50
100
150
200
0.5 0.6 0.7 0.8 0.9 1.0
VBE (V)
b
0.25*12.65µm2
0.65*12.65µm²
1.45*12.65µm²
0.E+00
1.E-02
2.E-02
3.E-02
4.E-02
5.E-02
0.0 0.5 1.0 1.5 2.0 2.5
VCE(V)
I C (
A)
Measurement
Simulation
0.25*25.45 µm²
0.E+00
1.E-02
2.E-02
3.E-02
4.E-02
5.E-02
0.0 0.5 1.0 1.5 2.0 2.5
VCE(V)
I C (
A)
Measurement
Simulation
0.65*12.65 µm²
0.E+00
1.E-03
2.E-03
0.0 0.5 1.0 1.5 2.0 2.5
VCE(V)I C
(A
)
Measurement
Simulation
0.25*0.65 µm²
19 juin 2004
HICUM WORKSHOP 2004
19/25
S. FREGONESE
Applications : AC measurement and model comparison BiCMOS 0.25 µm from STMicroelectronics
0
20
40
60
80
0.01 0.10 1.00 10.00 100.00
IC (A)
f T (
GH
z)
0.25*12.65µm²0.65*12.65µm²1.45*12.65µm²
0.25*1.45µm²0.25*25.45µm²
0
10
20
30
40
50
60
0.01 0.10 1.00 10.00 100.00 1000.00
Ic (mA)
f MA
X (
GH
z)
0.25*1.45 µm²
0.25*6.25 µm²
0.25*12.65 µm²
0.65*12.65 µm²
1.45*12.65 µm²
19 juin 2004
HICUM WORKSHOP 2004
20/25
S. FREGONESE
Applications : AC measurement and model comparisonY parameters :Y=f(frequency,VCE=1.5 V) for 4 VBE (0.7 V, 0.8V, 0.9V, 1V)emitter size (0.25 * 12.65 µm²)
BiCMOS 0.25 µm from STMicroelectronics
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
0.10 1.00 10.00 100.00
frequency (GHz)
real
(Y
11)
S
mesure
simulation
1.0E-07
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
0.10 1.00 10.00 100.00
frequency (GHz)
real
(y1
2) (
S)
mesure
simulation
1.0E-05
1.0E-04
1.0E-03
1.0E-02
0.10 1.00 10.00 100.00
frequency (GHz)im
ag (
y12)
(S
)
mesure
simulation
1.0E-04
1.0E-03
1.0E-02
1.0E-01
0.10 1.00 10.00 100.00
frequency (GHz)
imag
(y1
1) (
S)
mesure
simulation
19 juin 2004
HICUM WORKSHOP 2004
21/25
S. FREGONESE
Applications : AC measurement and model comparisonY parameters :Y=f(frequency,VCE=1.5 V) for 4 VBE (0.7 V, 0.8V, 0.9V, 1V)emitter size (0.25 * 12.65 µm²)
BiCMOS 0.25 µm from STMicroelectronics
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
1.0E+00
0.10 1.00 10.00 100.00
frequency (GHz)
imag
(y2
1) (
S)
mesure
simulation
1.0E-04
1.0E-03
1.0E-02
1.0E-01
0.10 1.00 10.00 100.00
frequency (GHz)im
ag (
y22
(S)
mesure
simulation
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
1.0E+00
0.10 1.00 10.00 100.00
frequency (GHz)
real
(y2
2) (
S)
mesure
simulation
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
1.0E+00
0.10 1.00 10.00 100.00
frequency (GHz)
real
(y2
1) (
S)
mesure
simulation
19 juin 2004
HICUM WORKSHOP 2004
22/25
S. FREGONESE
Applications : AC measurement and model comparisonY parameters :Y=f(IC,VBC=0) for 3 widths (0.25 * 12.65 µm²,0.65 * 12.65 µm²,1.45 * 12.65 µm²) and @ 7 GHz
BiCMOS 0.25 µm from STMicroelectronics
1.00E-03
1.00E-02
1.00E-01
0.01 0.10 1.00 10.00 100.00
Ic (mA)
imag
(Y11
) (S
)
0.25 µm
0.65 µm
1.45 µm
1.0E-04
1.0E-03
1.0E-02
1.0E-01
0.01 0.10 1.00 10.00 100.00
Ic (mA)
real
(Y
11)
(S)
0.25 µm
0.65 µm
1.45 µm
0.001
0.010
0.01 0.10 1.00 10.00 100.00
Ic (mA)im
ag (
y12)
(S
)
0.25 µm
0.65 µm
1.45 µm
1.0E-05
1.0E-04
1.0E-03
1.0E-02
0.01 0.10 1.00 10.00 100.00
Ic (mA)
real
(Y
12)
(S
)
0.25 µm
0.65 µm
1.45 µm
19 juin 2004
HICUM WORKSHOP 2004
23/25
S. FREGONESE
Applications : AC measurement and model comparisonY parameters :Y=f(IC,VBC=0) for 3 widths (0.25 * 12.65 µm²,0.65 * 12.65 µm²,1.45 * 12.65 µm²) and @ 7 GHz
BiCMOS 0.25 µm from STMicroelectronics
1.0E-04
1.0E-03
1.0E-02
1.0E-01
1.0E+00
0.01 0.10 1.00 10.00 100.00
Ic (mA)
real
(Y
21)
(S)
0.25 µm
0.65 µm
1.45 µm
0.001
0.010
0.100
1.000
0.01 0.10 1.00 10.00 100.00
Ic (mA)
imag
(Y
12)
(S)
0.25 µm
0.65 µm
1.45 µm
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
1.0E+00
0.01 0.10 1.00 10.00 100.00
Ic (mA)
real
(Y
22)
(S)
0.25 µm
0.65 µm
1.45 µm
0.001
0.010
0.01 0.10 1.00 10.00 100.00
Ic (mA)im
ag (
Y22
) (S
)
0.25 µm
0.65 µm
1.45 µm
19 juin 2004
HICUM WORKSHOP 2004
24/25
S. FREGONESE
Conclusion
• L0 can be enhanced (substrate network & Parasistic transistor)
• L0 has the Simplicity of Gummel Poon:• Less computational effort • Extraction is easier• Electrical description is very good
– Charge description
• But L2 is more precise for electrical description• But L2 has convergence problems for :
– Transient simulation with pulse for high slew rate
• Geometry Scaling with L0 can be realized• This scalable model was used on a BiCMOS 0.25 µm
STMicroelectronics technology.– DC and AC shows good agreements
• For different emitter size:– Width 0.25 µm -> 1.45 µm– Length 1.45 µm -> 25.45 µm
19 juin 2004
HICUM WORKSHOP 2004
25/25
S. FREGONESE
Perspectives
• Comparison of L0 model with measurement from– Very low size transistor– Faster transistor
• Enhancing model accuracy for specific physical effects (ex: High injection Barrier effects)
• SOI modelling