sar+ adc with open-loop integrator using dynamic … sar+adc with open-loop integrator using dynamic...
TRANSCRIPT
2017.10.26
SAR+ADC with Open-Loop Integrator using Dynamic Amplifier
Akira Matsuzawa and Masaya Miyahara
Tokyo Institute of Technology
1Contents
Background and Motivation Design concepts
• ADC architecture• Open-loop integrator• Dynamic amplifier• Binary-mode DEM
Measurement resultsSAR+DS ADC for CMOS image sensorConclusion
2017.10.26 A. Matsuzawa, Tokyo Tech.
2Background SAR ADCs Lowest power consumption with clock scalability SNR is limited by noises (Comp., Ref., mismatch)
∆Σ ADCs Highest SNR Power consuming of an Opamp in an integrator
Noise-shaping SAR ADCs [1, 2] High SNR and high efficiency Opamps are still used
[1] P. Harpe, et al., ISSCC 2014, [2] Y-S Shu, et al., ISSCC 2016
2017.10.26 A. Matsuzawa, Tokyo Tech.
3
biasperiod conversion ADCtime OperatingtimeRecovery current average Opamp I
Previous works 1
[3] K. Obata, et al., VLSIC 2016
Switched Opamp [3] Overhead of the recovery time
2017.10.26 A. Matsuzawa, Tokyo Tech.
4Previous works 2Fully passive integrator [4] Low gain, incomplete integration => Only for low OSR
[4] Z. Chen, et al., A-SSCC 2016
S
NS1
NS2
s
1 2
NS1
NS2
3
top
2
2 1
1
3 1
1 1,
1
0.5 1 1 0.6 ( )1 0.2 0.5
res plusz z V zY X
z
2017.10.26 A. Matsuzawa, Tokyo Tech.
5Previous works 3Passive integrator with dynamic pre-amp [5] Higher gain, but incomplete integration
[5] C-C. Liu, et al., ISSCC 2017
2017.10.26 A. Matsuzawa, Tokyo Tech.
6Effect of incomplete integration
An incomplete integrator cannot suppress Qn at low freq.
-80
-60
-40
-20
0
20
0.001 0.01 0.1
Qn
PSD
(dB
)
Normalized frequency
Ref. [5]Ref. [6]Idel 2nd order
Ex.) @ Fin = 1/20Ref. [5] = -15.0 dBRef. [6] = -21.3 dBIdeal = -32.2 dB
2017.10.26 A. Matsuzawa, Tokyo Tech.
[4][5]
[4][5]
7Our Design Concepts
Open-loop Integrator • A complete integrator can be realized by
using a low gain open loop amplifier and switched capacitors
• Dynamic amplifiers achieve low power consumption and clock scalability
Binary-mode DEM• Simple structure• Low power and small area
2017.10.26 A. Matsuzawa, Tokyo Tech.
8Target SQNR
Target SQNR > 95dBSAR ADC part : 6bit, SQNR = 38dBDSM part : Qn suppression > 57dB @OSR=20
0
20
40
60
80
100
120
1 10 100
SQNR
(dB
)
OSR
2nd order3rd order
2017.10.26 A. Matsuzawa, Tokyo Tech.
9ADC Architecture
Reset Sampling SAR Conversion Integration
2017.10.26 A. Matsuzawa, Tokyo Tech.
10ADC Architecture
Reset Sampling SAR Conversion Integration
2017.10.26 A. Matsuzawa, Tokyo Tech.
11Proposed Open-loop Integrator
Phase: 1Vout = Vout_n-1
Phase: 1Vout = Vout_n-1V1 = A1VinV2 = A2Vout_n-1
2017.10.26 A. Matsuzawa, Tokyo Tech.
12Proposed Open-loop Integrator
Phase: 1Vout = Vout_n-1
Phase: 2Vout = Vout_n-1+Vin
Phase: 1Vout = Vout_n-1V1 = A1VinV2 = A2Vout_n-1
Phase: 2Vout = (Vout_n-1+V1+V2)/3A1=3, A2=2,
Vout = Vout_n-1+Vin
2017.10.26 A. Matsuzawa, Tokyo Tech.
Proposed method can realize a complete integration
13Dynamic Amplifier Design• No DC current• Gain controllable 1.5x~4.5x, 5bit resolution
2017.10.26 A. Matsuzawa, Tokyo Tech.
14Open loop vs. Closed loop
An open loop integrator achieves 50~90% power reduction
0200400600800
100012001400160018002000
0 1 2 3 4 5 6 7 8 9 10
Aver
age
curr
ent (μA
)@10
MS/
s
Opamp recovery time (ns)
90%
50%Proposed
TelescopicOpamp
Folded cascodeOpamp
Proposed OpampDC Gain(V/V) 3 100# of unit 2 1IntegratorType Open Closed
IntegratorOutput noise 100μV RMS
Settling error - 1%Settling time 1.8nsClock Freq. 150MHzRecoverytime None 1 CLK
(6.7ns)
2017.10.26 A. Matsuzawa, Tokyo Tech.
15Gain error influence
80
85
90
95
100
105
110
-100 -50 0 50 100
SNDR
(dB)
Gain error (%)
Simulated SNDR vs. gain error of amplifier used in 1st integrator
Gain error of ±20% can be accepted (|∆SNDR| < 3dB)
3dB down
%20
2017.10.26 A. Matsuzawa, Tokyo Tech.
16ADC Architecture
Reset Sampling SAR Conversion Integration
2017.10.26 A. Matsuzawa, Tokyo Tech.
17Proposed Binary-mode DEM (B-DEM)
Randomly select left(0) or right(1) unit capacitors in each conversion.
DEM Control Code(DCC)
1XX
11X
10X
111
110
101
100
0XX
00X
01X
000
001
010
011
MSB conversion
MSB-1 conversion
LSB conversion
3bit example
2017.10.26 A. Matsuzawa, Tokyo Tech.
18Effect of proposed B-DEM
-140
-120
-100
-80
-60
-40
-20
0
1 10 100 1000 10000
Nor
mal
ized
Pow
er [d
B]
Frequency [kHz]
-140
-120
-100
-80
-60
-40
-20
0
1 10 100 1000 10000
Nor
mal
ized
Pow
er [d
B]
Frequency [kHz]
B-DEM disable
B-DEM enable
OSR=16, Mismatch 0.1%20 times Monte Carlo Simulation
SFDR (dB) SNDR (dB)Disable 88.2 83.0Enable 103.2 88.5
Improvement +15.0 +5.5
2017.10.26 A. Matsuzawa, Tokyo Tech.
19Chip photo• 65nm 9M1P CMOS technology • Chip area of 0.08mm2
2017.10.26 A. Matsuzawa, Tokyo Tech.
20FFT Spectrum
-140
-120
-100
-80
-60
-40
-20
0
1 10 100 1000 10000
No
rm
ali
zed
Po
wer [
dB
]
Frequency [kHz]
Without DEM
With DEM
Fs=10MS/s, Bandwidth = 250kHz, OSR=20, 10kHz input
BW=250kHz
SNR=84.2dBSFDR= 96.5dBSNDR=83.4dB
SNR=84.2 dBSFDR=96.5 dBSNDR=83.4dB
BW=250kHz
Without DEM
Without DEM
Fs=10MS/s, BW=250kHz, OSR=20, 10kHz input
Frequency [kHz]
1 10 100 1000 10000
0
-20
-40
-60
-80
-100
-110-120
-140
Nor
mal
ized
Pow
er [d
B]
2017.10.26 A. Matsuzawa, Tokyo Tech.
21Dynamic range
Dynamic range = 84.2 dB
-20
0
20
40
60
80
100
-100 -80 -60 -40 -20 0 20
SNR
,SN
DR
[dB
]
Input power [dBFS](Fs=10MS/s, OSR=20)
SNRSNDR
Dynamic range = 84.2dB
808182838485
-3 -2 -1 0 1
2017.10.26 A. Matsuzawa, Tokyo Tech.
22Clock scalability
FoMs > 170 dB for different sampling rates of 2.5 - 25 MS/s.
Pc @ 10MS/sAnalog : 60.0W (23.3%)Ref : 35.1W (13.6%)Digital : 162.7W (63.1%)
70
90
110
130
150
170
190
0
200
400
600
800
1000
1200
0 5 10 15 20 25 30
FoM
, SFD
R, S
ND
R [d
B]
Pow
er c
onsu
mpt
ion
[mW
]
Sampling rate [MS/s](OSR=20)
FoM
SNDR
Power
SFDR
2017.10.26 A. Matsuzawa, Tokyo Tech.
23Performance Summary
This Work VLSI 2016 [3]
ISSCC 2016 [1]
ISSCC2014 [2]
Architecture NS SAR NS SAR NS SAR NS SARProcess [nm] 65 28 55 65
Active Area [mm2] 0.08 0.116 0.072 0.18Supply [V] 1.0 1.55/0.75 1.8/1.1 1.2 0.8
Sampling rate [MS/s] 2.5 10 25 0.1 1.0 1.0 0.128BW [kHz] 62.5 250 625 2 20 4 16
SFDR [dB] 88.3 96.5 89.9 111.8 108.0 105.1 86.9SNR [dB] 84.3 84.2 82.2 98.57 94.44 96.8 -
SNDR [dB] 82.3 83.4 80.4 97.99 93.95 96.1 76.1Power [W] 66.3 257.8 630.2 37.1 493.1 15.7 1.37
FoM [dB] 172.0 173.3 170.4 175.3 170.0 180.0 176.8
Recent noise shaping SAR ADC
2017.10.26 A. Matsuzawa, Tokyo Tech.
24Performance comparison
10
100
1000
10 100 1000 10000
Wal
den
FoM
[fJ
/con
v.]
Bandwidth [kHz]
This work
140.0
150.0
160.0
170.0
180.0
190.0
10 100 1000 10000
Schr
eier
FoM
[dB
]
Bandwidth [kHz]
This work
Compared with the state-of-the-art ADCs over 80 dB SNDR
2017.10.26 A. Matsuzawa, Tokyo Tech.
25SAR+ ADC for CMOS image sensor
We have applied our proposed ADC technique to CMOS image sensor for reducing the read noise and power reduction.
2017.10.26 A. Matsuzawa, Tokyo Tech.
A. Matsuzawa and M. Miyahara, IISW, May. 2017.
26
∫ ∫
Proposed ADC for CIS
A. Matsuzawa, Tokyo Tech.
CDAC
6b+shift
CDAC
Int. Int.
RST
DynamicComp.
Vin
Vref
Trig
LogicsControl
Oscillator
Dout
2
for SAR and S/H
Low power SAR ADC + low noise ADC
1b+overlap
2017.10.26
2nd order incremental SAR+ADC
27 ADC with multiple sampling
A. Matsuzawa, Tokyo Tech.
Vin Vrefa1 a2
b
b
a1
a2
C C1
C1
C
Repeat
Vres
Signal sampling Residue generation
S/H 1 2 6 1 2 M
SAR ADC; 6 times ADC; m=32, 64, 128
Multi-samplingTrigger RST
After the SAR conversion, ADC is performed.The signal is sampled and the residue voltage is generated in CDAC using the converted data.
8-10 ns
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28CDS and ADC
A. Matsuzawa, Tokyo Tech.
1
01
0
Vr(6) Vq_DS
VRST
Vin
Vs
LSB
Shift
△ΣADCOverlap
Correlated Double Sampling (CDS)
SAR ADC
Vq_DS=30mV
△ΣADC is performed in small Vq of 30 mV with overlapping.The effect of capacitor mismatch is avoided in CDS operationby fixing the CDAC condition for the small signal.
fix the CDAC condition
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29Layout of the ADC20μm
770μm
CDAC COMP LOGIC VCO 1st Integrator 2nd Integrator
A. Matsuzawa, Tokyo Tech.
The ADC is designed in 65 nm CMOS technology
CDAC COMP LOGIC VCO
1st Integrator 2nd Integrator
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30Measured noise voltage
A. Matsuzawa, Tokyo Tech.
MeasuredADC for CIS
SimulatedMeasuredGeneral purpose ADC [2]
[2] M. Miyahara, et al, CICC, April, 2017
Measured noise is quite larger than that of the simulated. Our previous SAR+ADC realized much lower noise.
66 V
24 V
Oversampling ratio, m
Noi
se v
olta
ge (μ
Vrm
s)
m=16
m=32m=64
m=128
1000
100
1010 100 1000
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31What is the difference ?
A. Matsuzawa, Tokyo Tech.
General purpose [2]
This work for CIS
General purpose [2] This work for CISSignal: Samplig Full differential Single endedSignal: Integrator Full differential Full differentialCapacitance (pF): Sampling 10 1Capacitance (pF): Integrator 5 0.5Signal swing 2 Vpp 1 VQuantization voltage (mV) 16 32Order of integrator 3 2 (Incremental)
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32Conclusion
• Open-loop integrator A low gain open-loop amplifier can be used. No static current, clock scalable by using dynamic amplifiers. 50~90% power reduction compared with conventional
closed-loop integrator.
• Binary-mode DEM Simple shuffler +15dB of SFDR @ OSR=16
• An 84 dB dynamic range, 62.5-625 kHz bandwidth, FoMs > 170 dB noise shaping SAR ADC is realized.
• SAR+ADC is developed for low noise, low power, and high speed ADC for CMOS image sensor.
2017.10.26 A. Matsuzawa, Tokyo Tech.