samsung onenand™ system requirement

SEC-ONENAND-AN-001

Samsung OneNAND™ System Requirement

Samsung Electronics

Copyright ⓒ 2004 Samsung Electronics Co.,LTD.

2 Samsung Electronics Co., Ltd.

Revision History

Version Date Comment Author Approval 0.1 NOV-25-2004 Initial version Seungeun Lee

Document Overview - Status: On writing - Num of Pages: 20 - Appendix: No

Contact Information Flash Planning Group Memory Division, Device Solution Network Samsung Electronics Co., Ltd Address : San #16, Banwol-Ri, Taean-Eup, Hwasung-City, Gyeonggi-Do, Korea, 445-701 E-mail : [email protected] Copyright © 2004 Samsung Electronics Co, Ltd. All Rights Reserved. Though every care has been taken to ensure the accuracy of this document, Samsung Electronics Co, Ltd. cannot accept responsibility for any errors or omissions or for any loss occurred to any person, whether legal or natural, from acting, or refraining from action, as a result of the information contained herein. Information in this document is subject to change at any time without obligation to notify any person of such changes. Samsung Electronics Co, Ltd. may have patents or patent pending applications, trademarks copyrights or other intellectual property rights covering subject matter in this document. The furnishing of this document does not give the recipient or reader any license to these patents, trademarks copyrights or other intellectual property rights. No part of this document may be communicated, distributed, reproduced or transmitted in any form or by any means, electronic or mechanical or otherwise, for any purpose, without the prior written permission of Samsung Electronics Co, Ltd. The document is subject to revision without further notice. All brand names and product names mentioned in this document are trademarks or registered trademarks of their respective owners.

Samsung Electronics Co., Ltd. 3

Purpose This is an application note of OneNAND™ developed by Samsung Electronics. This application note is designed for the project manager, project leader, application programmers and engineers when they adopt OneNAND™ to mobile devices and implement OneNAND™ to their hardware system. This application note provides why system requirements of OneNAND must be mainly considered for adopting.

Scope

Chapter Description

1 Introduction

Explains the system requirements of mobile phone for flash memory. This also introduces Samsung’s new memory design, a unified storage architecture OneNAND™, and explains its performance comparison with NOR and NAND.

2 Flash Memory Read Performance

Explains the system the read performance of OneNAND by illustrating an example, which compares NAND and OneNAND.

3 Flash Memory Write Performance

Explains Multi-Shot Sequence to Flash memory in mobile phone. Then, this chapter describes RAM overhead and Shot-to-Shot delay in write performance of Multi-Shot. It covers OneNAND’s features and the methods for performance improvement.

4 Associated Memory Architecture Proposal

Explains Samsung’s proposal for memory architecture by flash density; low-end, middle-end and high-and mobile phone.

5 Conclusion Summarizes this application note and finalizes it.

6 Additional Information Lists Samsung’s website URLs related to OneNAND™ products and documents. You can get useful information about OneNAND™.

Definitions and Acronyms

Definitions and Acronyms Description

Bottleneck The delay typically occurs when a system's bandwidth cannot support the amount of information relayed at the speed it is being processed.


Demand paging In virtual memory systems, demand paging is a type of transferring in which pages of data are not copied from disk to RAM until they are needed.

DSP Digital Signal Processor

GSM Global System for Mobile Communication

W-CDMA Wideband Code Division Multiple Access

Code Read Only area for instructions that CPU executes

Data Read / Write area for data that are required for executing instructions

Storage Read / Write area for configuration data and user data that are required for system set-up

References

SEC Semiconductor division, NAND Flash Memory and SmartMedia Data Book, Samsung Electronics Co., Ltd 2003


Contents 1 Introduction ..............................................................................................8

1.1 Write Bandwidth Requirements for Recording .................................................8 1.2 Unified Storage Architecture for Read Performance..........................................9 1.3 Samsung OneNAND Flash Memory and Its Performance..................................... 10

2 Flash Memory Read Performance ................................................................... 12 2.1 NAND and OneNAND Read Performance Comparison........................................ 12

3 Flash Memory Write Performance................................................................... 16 3.1 Background of DSC Write Performance........................................................ 16 3.2 Multi-Shot Sequence in Flash Memory and Shot-to-Shot Delay by Flash Memory....... 17 3.3 Case 1 : RAM Overhead in Multi-Shot .......................................................... 18 3.4 Case 2 : Shot-to-Shot Delay in Multi-Shot..................................................... 21

4 Associated Memory Architecture Proposal ........................................................ 26 4.1 Memory Architecture by Flash Density ........................................................ 26

5 Conclusion .............................................................................................. 29 6 Additional Information................................................................................ 30

6.1 Information Website.............................................................................. 30


Figures Figure 1-1. Write Bandwidth Requirements for Recording.............................................. 8 Figure 2-1. Boot-up Time Comparison between OneNAND and NAND ............................... 13 Figure 2-2. Definition of Execution stall caused by Page Faults in Execution flow ............... 14 Figure 3-1. Performance Improvement of DSC.......................................................... 16 Figure 3-2. Shot Write Sequence into Flash Memory................................................... 17 Figure 3-3. RAM-buffered Multi-Shot Memory Map ..................................................... 19 Figure 3-4. Direct Multi-Shot Memory Map .............................................................. 20 Figure 3-5. Different Procedures for NOR and OneNAND in Multi-Shot ............................. 22 Figure 3-6. DSC Timing Calculation in Low-end DSC ................................................... 23 Figure 3-7. DSC Timing Calculation in High-end DSC................................................... 24 Figure 3-8. OneNAND Write Performance Roadmap.................................................... 25


Tables Table 1-1. OneNAND Performance Comparison with NOR and NAND................................ 10 Table 2-1. Read Performance Comparison between OneNAND and NAND.......................... 12 Table 2-2. System Requirements of NAND and OneNAND for Full and Partial demand Paging.. 14 Table 3-1. Comparison on RAM overheads of Single Shot and 3 Multi-Shot in terms of Write

Mode ..................................................................................................... 20 Table 4-1. Memory Architecture at Low-end ~ Middle-end Flash Density .......................... 26 Table 4-2. Memory Architecture at High-end Flash Density .......................................... 27 Table 6-1. Information Website ........................................................................... 30


1 Introduction This chapter begins by portraying the bandwidth requirements for flash write in recent mobile device market, and explains why unified storage architecture has so much meaning when applying OneNAND to high-end handheld devices. This chapter ends with performance comparison among OneNAND, NAND, and NOR giving some clues that OneNAND’s write performance is superior to the other two while its read performance is truly improved.

1.1 Write Bandwidth Requirements for Recording Today mobile phones such as smart phones and video phones in market require a high density of memory storage to support advanced functionalities, download contents, and execute multimedia applications in real time. There are two popular types of flash memory in mobile phone market used: NOR and NAND. They are named after their unique cell array structures each one uses to read and write data. Flash Memory’s high write data rate is a decisive factor of real-time stream recording in mobile phones. Moreover, encoding overhead of mobile phone makes more than 30% of write data rate of flash memory necessary for the mobile phone system. Figure 1-1 shows how much mobile phone will need the write bandwidth for recording in next 5 years.

Figure 1-1. Write Bandwidth Requirements for Recording

QCIF phone whose frame speed is 15f/sec requires 50KB/sec of write bandwidth. NOR flash memory has write performance coverage enough for QCIF phone. However, even 300K pixel CIF phone is beyond NOR flash memory’s write performance coverage. The gap between NOR flash memory’s write performance and mobile phone system’s demand for its memory component’s


write performance becomes much bigger at further advanced phones such as VGA phone or Mega-Pixel phone. NOR flash memory cannot fully satisfy demands from newly emerging multimedia applications which require much higher write bandwidth. NOR flash memory is adaptable for low-end voice-centric color phone but is not proper for 3G mobile phones or more advanced phones. In order to cope with faster and more powerful mobile phones, NAND-based architecture flash memory is designed and will be commercially launched from 2005. Furthermore, mobile phones strongly needs NAND-based architecture flash memory’s renovation so that flash memory handles increasing code and data size for executing seamless video, CD-quality audio and others. Consequently, some system engineering efforts have been made to cope with system requirement for memory’s write performance in mobile memory market. Samsung Electronics have developed the unified flash memory, OneNAND™, for wide-ranging applications in high-end mobile phones.

1.2 Unified Storage Architecture for Read Performance The above chapter describes why mobile market requests high density flash memory more and more, and how much mobile market requests flash memory for the write performance of the mobile device. On the other hand, in order to reduce the device cost and improve the system performance, the market is being changed for the unified storage. OneNAND is one of the unified flash memories newly invented by Samsung Electronics. OneNAND is a flash storage device for storing code and data together. In RTOS, OS code in kernel part and code in application part are not separated from each other. When the system power is on, all kernel codes must be loaded into DRAM together to make the whole system work properly. To minimize boot time of the whole system, the read performance becomes more important for the unified storage system. To run application program, the system first copies the application program from OneNAND to DRAM by demand loading, and then executes the copied application program on DRAM. To minimize wait time of the whole system during demand loading, the read performance becomes more significant. Current mobile device usually adopts the unified storage architecture based on NAND flash memory. However, NAND flash memory cannot satisfy the system requirements for read performance of flash memory. OneNAND that provides the advanced functionalities, dual buffering and cache read operation shows the speed of read operation as much as NOR. The high-end mobile device equips CD-quality sound, crystal-clear screen and real-time execution, so the size of code is extremely increased. Accordingly, to boot the system or to execute application program in mobile devices, the system must copy that increased code into DRAM by demand loading. Samsung OneNAND is the most perfect for the unified storage architecture of high resolution mobile device because of its speedy read performance.


1.3 Samsung OneNAND Flash Memory and Its Performance OneNAND is a high-capacity fusion memory manufactured by Samsung Electronics. It is a single silicon chip comprising a NOR flash interface, NAND flash controller logic, and NAND flash memory. OneNAND includes a built-in boot loader that is not in NAND flash memory, which enables OneNAND to boot faster than NAND flash memory. In addition, OneNAND performs read operation as fast as NOR flash memory; however NAND flash memory shows relatively low speed in read operation. OneNAND as a NAND-based architecture flash memory is designed for embedded applications, especially mobile phones. It is able to provide higher read/write performance and reduced power consumption with a minimal increase of costs. Thus, OneNAND could be the second to none for applications requiring faster internal data flows and large storage requirements such as high resolution digital image and memory-hungry applications. Table 1-1 shows OneNAND’s performance compared with NAND’s and NOR’s performance based on Data Specification.

Table 1-1. OneNAND Performance Comparison with NOR and NAND

OneNAND NOR (MLC)

NAND (x8, Large

Block) 0.12µm 90nm Code Data

Read 16.5MB/s 27MB/s 68MB/s 108MB/s 23.9MB/s

Program 6.5MB/s 6.1MB/s 9.3MB/s 0.14MB/s 0.14MB/s

Erase (Single) 64MB/s 64MB/s 64MB/s 0.11MB/s 0.11MB/s

Erase (Multi) Not Available 2.1GB/s 2.1GB/s 0.11MB/s 0.11MB/s

(Unit: MB per a second)

NOR flash memory offers eXecute In Place (XIP) capabilities and high read performance, so it is typically used for code storage and execution. On the other hand, NAND flash memory offers high cell densities and fast program/erase performance. Accordingly, NAND is mostly used for data storage. Table 1-1 provides the performance results of two OneNAND products (0.12µm and 90 nm). In read operation, 0.12µm OneNAND product shows 27MB/s. By increasing the internal bus width and the host frequency, 90nm OneNAND product reaches 68MB/s in read operation. In program operation, 0.12µm OneNAND product shows 6.1Mb/s. However, 90nm OneNAND product shows 9.3MB/s but NAND flash memory (x8, Large Block) shows 6.5MB/s. Besides, OneNAND dramatically improves erase performance by providing multi-block erase operation. Reference


The performance results in Table 1-1 are based on Data Book Specification of NOR, NAND, and OneNAND, and are dependent on the used platform, software, and development environment. However, if a user’s platform is fast enough and accommodates Burst mode, a user is able to achieve better performance results.


2 Flash Memory Read Performance This chapter illustrates an example comparing the read performance of OneNAND with that of NAND to prove why the unified storage architecture of OneNAND is critically important for the read performance. Then, it describes the real effects of adopting OneNAND’s fast read performance.

2.1 OneNAND and NAND Read Performance Comparison Chapter 1.2 explains that read performance is one of strong points of OneNAND. This section describes how much OneNAND accomplishes read performance in contrast to NAND. To prove OneNAND’s superior performance, we use three cases; 50ns (read cycle time) NAND, 100ns (read cycle time) NAND, and 70ns (asynchronous access time) OneNAND. Reference When adopting NAND to the real system, the total system is composed of many hardware devices. That is, the real system consumes more read cycle time because of the physical performance of other hardware devices. In other words, 100ns is the real read cycle time of NAND and 50ns is the most optimized read cycle time of NAND. Thus, we use two separate examples for NAND read performance. Because OneNAND is a unified storage device, the read performance in real systems is rarely different from the evaluated read performance. Thus, we use only one example 70ns OneNAND for read performance. Table 2-1 shows the comparison results of the read performance between NAND and OneNAND.

Table 2-1. Read Performance Comparison between OneNAND and NAND

Features Bandwidth [@64K Words]

Case 1 NAND(x8) tRE=50ns 16.5MB/s

Case 2 NAND(x8) tRE=100ns 9MB/s

Case 3 OneNAND(x16) tAA=76ns(Async. Read) 27MB/s

50ns in Case 1 is NAND cycle time under the most optimized system environment which shows 16.5MB/s of bandwidth. Case 2 describes the real cycle time tested under the real system environment. It shows 100ns of cycle time and 9MB/s of bandwidth. Finally, Case 3 is when OneNAND asynchronous access time is 76ns. The calculated asynchronous access time is hardly different from the real one because even though OneNAND shares bus with other devices – the devices sharing bus with OneNAND do not have big capacitance due to interface issue (OneNAND has NOR-like interface) – it will not have a huge effect on load capacitance increase. In this case, the bandwidth is 27MB/s.


Reference There are two independent 2KB bi-directional data buffers, DataRAM0 and DataRAM1. Dual buffers enable the host to execute simultaneous Read-While load, and Write-While-Program operations after booting up. Each of the DataRAM is concurrently used for fast data transmission from NAND array to host. It is called a dual buffering. Now, We know the fact that OneNAND is superior to NAND in read performance. From now to this chapter, two examples showing that the above fact is true will be explained. Booting time: When the system boots up, the system first copies codes into DRAM from flash memory, which is called code shadowing. In other words, a host reads code from flash memory and moves it into DRAM. Because the whole system’s booting time is affected by this code-copying time in large portion, the read speed of flash memory could be so important a factor for applications requiring short boot up time such as DTV. Figure 2-1 shows the comparison of boot-up time between OneNAND and NAND.

Figure 2-1. Boot-up Time Comparison between OneNAND and NAND

In the above figure, OneNAND has the best read performance and the fastest boot-up speed. The boot-up time is inversely proportional to the read speed of Flash memory. Note that OneNAND used in synchronous read mode, which is described with parentheses, has much faster booting speed. Execution stall (Page fault): When a page fault occurs in a system using demand paging, CPU must take some steps to get the right data from memory to cache which causes execution stall defined as the timing delay between two executions when a page fault occurs. Figure 2-2 illustrates what steps CPU must take when a page fault occurs and defines execution stall.


Figure 2-2. Definition of Execution stall caused by Page Faults in Execution flow

In this specific example of execution stall caused by a page fault, once a page fault occurs, CPU should take three steps. Among these three steps, the second step – Find physical page and load the page from OneNAND to RAM – occupies the biggest portion of the total execution stall. The total delay caused by execution stall has been measured and proved to be less than 250us in worst case. This implies that OneNAND is good enough to replace NOR because the execution stall less than 250us satisfies the system requirements for not just full demand paging but also partial demand paging. In other words, using OneNAND with demand paging scheme does not cause any system requirement violation despite the fact that OneNAND has such weak point as execution stall caused by page faults. Table 2-2 explains the system requirements of NAND and OneNAND for Full Demand Paging and Partial Demand Paging. Table 2-2 indicates that as Flash Market moves from RU (NOR+UtRAM) to ND (NAND+DRAM) for the purpose of cost down, ND combination has not taken a huge advantage of cost down because of the size increase of DRAM. In order to overcome this RAM overhead, demand paging scheme has become much more significant for ND combination. However, the innate drawback of low read speed of NAND limits the range of usage for demand paging. From this read speed’s point of view, OneNAND has no such usage limitation when being used as OD (OneNAND+DDR) combination with either full or partial demand paging scheme. This OD plus demand paging scheme satisfies the current market request for both cost down and high read speed.

Table 2-2. System Requirements of NAND and OneNAND for Full and Partial demand Paging

Method Allowable Duration NAND OneNAND

Full Demand Paging 300us (watchdog) X 0

Partial Demand Paging 2ms 0 0

When applying demand paging scheme to time critical codes which need run-time execution, the execution stall can be a serious problem. Thus, if these time critical codes remain in RAM all the time, CPU does not have to read codes from flash but access directly RAM and fetch those codes from it even though a page fault occurs. This can reduce the execution stall in a great deal, which makes demand paging possible for even time critical codes with OneNAND. In 3G and later generation mobile device, satisfying the requirement of the read performance will become quite a serious issue. OneNAND is the most suitable flash memory for the high-end


mobile device due to its outstanding read performance. OneNAND will show much more improved results if it is used in synchronous read mode.


3 Flash Memory Write Performance This chapter stresses the importance of the write performance of OneNAND when DSC takes multi-shots. This chapter also indicates 2 problems that usually occur in DSC applications and provides solution for each problem.

3.1 Background of DSC Write Performance In order to make continuous multi-shot-taking possible for Digital Still Camera (DSC), the write speed of flash memory has been a mainly discussed issue. This section describes how DSC multi-shots are taken and how taking multi-shots affects the total DSC system. One snapshot process in a digital still camera is composed of the following steps: 1. Image Sensing and Processing 2. Compression 3. Flash Write That is, the write performance of DSC depends on the above three processes, and this total processing time must be decreased to satisfy multi-shot per second requirement. In order to reduce the total processing time, fast flash write speed is becoming a more significant factor since processing times for other 2 processes have been reduced much enough already. 2 different architectures could be chosen for High-end DSC according to flash write speed in Figure 3-1. These 2 architectures will be explained in detail in section 3.3.

Figure 3-1. Performance Improvement of DSC


Reducing the time taken for the camera to capture the image and then transfer it to memory is an important issue required by market. However, Figure 3-1 shows that DSCs with slow write speed flash memory cannot perform multi-shot action. This slow write performance of flash memory is an obstacle against taking multi-shots. Thus, Burst Write mode (or Burst Infinite mode) – an advanced architecture of DSC – is becoming new popular trend of DSC architecture. DSC with Burst Write mode shows the decreased time for imaging sensing & processing and compressing. In addition, we suggest the newest advanced architecture prior to others: Continuous Write mode (a unified architecture). This up-to-date architecture requires the flash memory that performs highly speedy write; hence this architecture makes it possible to take multi-shots by improving write performance of DSC. This result notifies that the unified architecture is the most adoptable for high-end DSC and also satisfies market demand for shot-handling speed.

3.2 Multi-Shot Sequence in Flash Memory and Shot-to-Shot Delay by Flash Memory

When you take a snapshot using camera-attached mobile phone, data of the photograph is saved in flash memory through write operation. Figure 3-2 shows the sequence writing a snapshot data to flash memory when you take a photograph using the chipset of mobile phone.

Figure 3-2. Shot Write Sequence into Flash Memory

The real processes of storing snapshot data in flash memory are as follows: (1) A Snapshot data is saved into DRAM through chipset. (2) The Snapshot data from DRAM is compressed into CODEC of DSP. (3) The compressed data from CODEC is saved into DRAM. (4) The compressed data from DRAM is written into flash controller of DSP. (5) The data from flash controller is written into flash memory.


If you take multi-snapshots using mobile phone, the speed of repeated flash write (step 5) is crucial for system operating. For example, if the speed of flash write operation (step 5) is slower than that of JPEG encoding, data of each shot cannot be written into flash memory one by one, which causes a serious bottleneck in the way of this whole sequence. Hence, data of multi-shots are accumulated at RAM first. After handling the other processes of multi-shot data such as (step 1) ~ (step 4), the data accumulated at RAM are written into flash memory all together. In this case of shot-to-shot delay caused by flash memory’s incomparably lower write speed over JPEG encoding speed, the size of RAM buffer act as the limiting factor for how many multi-shots DSC can take. Thus, increasing the number of multi-shots causes the size of RAM to increase, accordingly hardware cost goes up. In addition, that shot-to-shot delay makes write performance of flash memory change in an irregular way. The fluctuation about the bandwidth of write performance must be minimized and stabilized not to overflow RAM buffer. In conclusion, continuous multi-shots in mobile phone can be done with OneNAND or High-speed MMC. OneNAND shows powerful write performance which eliminates the limiting factor for how many multi-shots DSC of mobile phones can take. The powerful write performance lets the ability of whole system in mobile phone be stable and strong. Now, the following two sections show typical problems that occur when DSC takes multi-shots. The first one is about the influence of RAM size on multi-shot performance, and the second one is about the influence of shot-to-shot delay on the flow of system. We suggest direct write architecture to solve the RAM overhead problem, and adopt fast write flash memory to solve the shot-to-shot delay problem without RAM overhead.

3.3 Case 1 : RAM Overhead in Multi-Shot This section shows the influence of RAM size on multi-shot performance. Here is an example that you take three multi-shots per second using mobile phone. The raw data of 3 multi-shots is saved in DRAM through CCD module. Next, the raw data is encoded as JPEG in turn, and then the encoded data is written into flash memory. If flash write is slower than JPEG encoding, a bottleneck occurs between JPEG encoding and flash write. Figure 3-3 shows the case of 3 multi-shots per second and their accumulation at RAM.


Figure 3-3. RAM-buffered Multi-Shot Memory Map

Figure 3-3 is called RAM-buffered Multi-Shot Memory Map used for NOR. Snapshot raw data from CCD module are accumulated at RAM. Next, Raw images are processed, compressed, and then stored at RAM again. After RAM is filled with RAW images and encoded images (in this example of Figure 3-3, 3 raw data and 3 encoded JPEGs), the next process – the flash write process - is performed. In this example, the chipset starts to write 3 encoded JPEGs into flash memory one by one. Until completing that flash write process, the next multi-shots are delayed. This is called shot-to shot delay. RAM-buffered Multi-Shot Memory Map imposes a heavy burden of RAM on the overall system to manage raw data and encoded JPEG images. That RAM overhead not just prevents large raw image from being treated at a time but also prohibits it to be processed and compressed to JPEG. What is more, RAM overhead limits the number of multi-shot that can be done at a time, and makes slow the whole process storing snapshot image at flash memory. However, if flash write is faster than JPEG encoding, there is no bottleneck in RAM unlike the above case. Figure 3-4 shows the case of 3 multi-shots per second and their image processing and compression through RAM without delay.


Figure 3-4. Direct Multi-Shot Memory Map

Figure 3-4 is called Direct Multi-Shot Memory Map used for OneNAND. The processes in direct multi-shot memory map are as follows: (1) The first raw image is saved into DRAM, it is encoded as the first JPEG image by the encoder of DSP, and the JPEG image is saved into DRAM.

(2) The second raw image is saved into DRAM while the first JPEG image is written into flash memory. (3) The third raw image is saved into DRAM while the second JPEG image is written into flash memory.

(4) Finally, the third JPEG image is written into flash memory. In Direct Multi-Shot Memory Map, RAM buffer is slimmed down as much as one processing unit. This method eliminates the burden of RAM on the system, so the hardware cost is diminished. A matter of course, direct multi-shot method secures well-balanced data flow and reliable memory system. Continuous multi-shots can be done with OneNAND which has superior flash write ability until its available flash storage space is emptied. Table 3-1 shows the comparison on RAM overheads of single shot and 3 multi-shot for different pixel size of mobile phones.

Table 3-1. Comparison on RAM overheads of Single Shot and 3 Multi-Shot in terms of Write Mode


0.3M (640x480)

1M (1280x960)

2M (1600x1200)

3M (2048x1536)

5M (2592x1942)

Single Shot 0.7MB 2.9MB 4.6MB 7.5MB 12.0MB Buffered

Write Scheme 3 Multi

Shot 2.2MB 8.8MB 13.7MB 22.5MB 36.0MB

Single Shot Direct

Write Scheme 3 Multi

Shot

0.6MB 2.3MB 3.7MB 6.0MB 9.6MB

In 300K pixel mobile phone, single shot in Buffered Write Scheme requires 0.7MB and 3 multi-shot in Buffered Write Scheme requires 2.2MB, whereas both single shot and 3 multi-shot in Direct Write Scheme require 0.6MB. In 5M pixel mobile phone, the gap between the 2 Write Scheme’s requests for RAM buffer becomes much bigger. Single shot in Buffered Write Scheme requires 12.0MB and 3 multi-shot in Buffered Write Scheme requires 36.0MB, whereas both single shot and 3 multi-shot in Direct Write Scheme require 9.6MB. This result indicates that RAM-Buffered Write Scheme imposes a heavy burden of RAM on the system as the pixel of mobile phone becomes high and the number of multi-shot increases. On the other hand, Direct Write Scheme reduces RAM overhead despite of the high pixel of mobile phone or the increased multi-shots. OneNAND, adopting Direct Write Scheme with fast flash write performance, cuts down RAM overhead in multi-shots and requires the just small size of RAM. As a result of the reduced system requirements, the size of hardware is diminished and the cost of the whole system goes down.

3.4 Case 2 : Shot-to-Shot Delay in Multi-Shot This section shows the influence of shot-to-shot delay on the flow of system. We have an example in which you take three multi-shots per second using mobile phone in chapter 3.3. In this example, shot-to-shot delay occurs due to the slow flash write performance. It is needed to increase the size of buffer to eliminate the shot-to-shot delay, but this leads to RAM overhead. Thus, In order to avoid shot-to-shot delay without RAM overhead, the fast flash write performance must be required for taking multi-shots. If the mobile phone adopts NOR flash memory that performs slow flash write to take multi-shots, RAM buffer overhead increases and accordingly shot-to-shot delay occurs. On account of adopting NOR, larger RAM is needed even 300K pixel mobile phone for multi-shot in Figure 1-1. Shot-to-shot delay caused by NOR’s slower write speed than JPEG encoding speed and RAM buffer overhead limit the number of multi-shot as explained in Figure 3-3. Figure 3-5 shows the different procedures for NOR and OneNAND in multi-shot.


Figure 3-5. Different Procedures for NOR and OneNAND in Multi-Shot

In this example, a user can take up to 3 multi-shots, so up to 3 snapshot data can be stored in DRAM before being written into NOR flash memory. Thus, NOR makes it difficult to save the large size of image or continuous images. The write speed of OneNAND is faster than JPEG encoding speed, so there is no bottleneck in multi-shot memory map like Figure 3-4. You can take continuous multi-shots as long as flash memory is available. The fast read speed of OneNAND offers fast-scan of a pile of snapshot files. Therefore, OneNAND can support mega-pixel multi-shots for high-end mobile phone. Now, we provide examples about the improvement of DSC write performance using OneNAND. It explains how write performance of DSC is improved in order of generation. In chapter 3.1, we have explained one snapshot processing time in DSC. Figure 3-6 illustrates DSC timing calculation in low-end DSC and Figure 3-6 illustrates DSC timing calculation in high-end DSC. These two charts explain what the key issue of write performance in mega-pixel DSC is and how write performance of DSC has been improved.


Figure 3-6. DSC Timing Calculation in Low-end DSC


Figure 3-7. DSC Timing Calculation in High-end DSC

In Figure 3-6, low-end DSC had poor internal processor in CCD Sensing, Image Processing and JPEG Compression. That poor internal processor was the main factor of bottleneck in DSC performance. However, powerful internal processor in high-end DSC remarkably shortens time for CCD Sensing, Image Processing and JPEG Compression in Figure 3-7. Thus, the internal processor cannot be the source of trouble in DSC write performance any more. Instead, slow flash write speed becomes the major cause of bottleneck in DSC write performance. In both Figure 3-6 and Figure 3-7, every mega pixel case provides two DSC Timings for MMC and SD. The flash write speed of MMC causes bottleneck of the overall write performance in DSC. But the flash write speed of SD apparently demonstrates the performance improvement. This result implies that the improving flash write speed is a main theme in order to improve the write performance of DSC. These results about DSC timing calculation distinctly notify the importance of the flash write speed. OneNAND is one of those memories that perform fast flash write and we keep trying to improve the write performance of OneNAND. Figure 3-8 shows the Roadmap of OneNAND write performance.


Figure 3-8. OneNAND Write Performance Roadmap

Figure 3-8 describes how speedy the flash write performance of OneNAND is and how much it is improved. By reducing internal transfer time from NAND Flash core to SRAM Buffer, we have got 9.3MB/s flash write speed for 90nm 1Gb OneNAND over 5.8MB/s for 0.12um 512Mb OneNAND. Samsung Electronics continue developing new flash write schemes such as 2X Program and Synch Burst Write and consequently expect the overall write bandwidth will reach up to 17MB/s for the next generation of 60nm 2Gb OneNAND. This improvement in write performance will make possible a various usage of OneNAND in high-end handheld devices.


4 Associated Memory Architecture Proposal This chapter describes Samsung’s recommendation about flash memory architecture corresponding to flash density. In particular, it stresses the necessity of adopting the unified memory architecture at high-end mobile phone.

4.1 Memory Architecture by Flash Density Here is Samsung’s proposal for memory architecture by flash density. We classify memory architecture according to flash density: low-end, middle-end, and high-end. We again divide high-end memory architecture into two classes; full demand loading (or demand paging) and partial demand loading. Table 4-1 shows two memory architectures and their software adoptions from Low-end to Middle-end flash density.

Table 4-1. Memory Architecture at Low-end ~ Middle-end Flash Density

Flash Density Memory Architecture

1 ≤ 256 Mb

Low-end ~ Middle-end

2 ≥ 256 Mb

Middle-end ~ High-end

Low-end mobile phone is voice-centric color phone. Because Low-end mobile phone rarely needs not only high write performance but also high capacity flash memory, that phone does not use NAND-based architecture flash memory. Thus, we suggest (NOR +SRAM (or UtRAM)) memory architecture for low-end mobile phone requiring lower than 256Mb. In low-end mobile phone, NOR is used for storage and code including data, and SRAM (or UtRAM) is used as a working RAM. In this case, data and application code are built together with OS.


Middle-end mobile phone is mid-tier data-centric color phone. This phone adopts SRAM (or UtRAM) which does not consume electric power as much as DRAM because the low electric power consumption is a key figure at this level of mobile phones. What is more, middle-end flash density is needed because middle-end mobile phone partially provides camera or video-recording or mp3 player features. Thus, we suggest (NOR + NAND + SRAM (or UtRAM)) memory architecture for middle-end flash density requiring more than 256Mb. In middle-end mobile phone, NOR is used for code, NAND for data and storage, and SRAM (or UtRAM) as a working RAM. In this case, built-in data (such as font, bitmap, timer, etc) can be isolated from code, and moved and stored to NAND for lower cost. Table 4-2 shows two memory architectures and their software adoptions for high-end flash density.

Table 4-2. Memory Architecture at High-end Flash Density

Flash Density Memory Architecture

3 Partial Demand Loading

4 Full Demand

Loading / Demand Paging

High-end mobile phones fully support the following features: recording video, taking multi-shots, or executing real-time applications. Accordingly, write performance and capacity are critical factors for choosing memory for mobile phone. High-end mobile phone basically adopts OneNAND and DRAM, and is divided into two classes: partial demand loading and full demand loading (or demand paging).


In RTOS, real-time code1(kernel code)and application code are not separated from each other. Because of that, application code and kernel code must be loaded into DRAM together when the system power is on. In other words, all code must reside in DRAM while the system is working. Because loading codes together causes RAM overhead, high-end mobile phone cannot make a merit of using OneNAND. In the above case, NOR is adopted for code whereas OneNAND is used only for storage and DRAM is used as a working RAM like the memory architecture of middle-end mobile phone. This method is called partial demand loading. However, if real-time code is separated from other application code or default data, OneNAND can reduce RAM overhead and shadowing time. In this case, OneNAND can be used for code and storage and DRAM is used as a working RAM while not using NOR. This method is called full demand loading or demand paging. RAM overhead can be decreased by adopting full-demand loading method to minimize the size of code that would be loaded in DRAM. OneNAND’s code execution by full demand loading shows faster speed than NOR’s code execution because OneNAND code is directly executed on DRAM. Most of all, because both RAM overhead and shadowing time are minimized, full demand loading surpasses partial demand loading in read performance, which is the most significant factor in determining which type of memory to use in high-end mobile phone. Samsung Electronics highly recommends full demand loading for memory architecture of high-end mobile phone, and partial demand loading for memory architecture of middle-end mobile phone. This proposal is expected to take off in years to come. Most of high-end mobile phones currently adopt partial demand loading. In order to use OneNAND™ as a single unified memory using full demand paging memory architecture, Samsung and major OS manufacturers are participating in new memory architecture project for high-end mobile phone. Furthermore, this project is driving down OneNAND prices while driving up OneNAND performance. The unified memory architecture will be commercially launched soon.

1 Real-time code means the code that requests fast random access. It is also called kernel code.


5 Conclusion According to mobile phone evolution in a range of functions, flash memory is requested in density. As the high-resolution phone offers hours of video recording, an MP3 player, and text-to-speech conversion, flash memory must maximize performance and robustness but minimize cost and executing time. Samsung OneNAND, which combines NAND flash memory and RAM and system logic in one chip, is mostly appropriate for memory-intensive applications of new-generation mobile phone. It speeds up the process and manages high-capacity data at a time. Samsung OneNAND allows phone makers to build multimedia phones that can access media services from wireless carriers with cheaper, faster and mightier system.


6 Additional Information

6.1 Information Website This section provides information website about Samsung OneNAND, including application notes, can be found at.

Table 6-1. Information Website

Samsung Branch WebSite

Samsung Semiconductor www.samsungsemi.com

Samsung USA Semiconductor www.usa.samsungsemi.com

Samsung Flash Memory Home Page

http://www.samsung.com/Products/Semiconductor/Flash/index.htm

Samsung Membership Technical Document

https://c-dance.samsungsemi.com/ It is a Samsung’s Flash Software release website. Samsung Semiconductor provides authorized person with our customer specific documents. Only permitted user can access the customer-level documents on it

samsung onenand™ system requirement

Documents

performance onenand

samsung onenand flash

read performance of

performance of multishot

memory architecture

system requirements

performance comparison

performance improvement