sama5d27c automotive datasheet -...
TRANSCRIPT
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Ultra-low power ARM Cortex-A5 core-based MPU, 500 MHz, Graphics Interface, Ethernet 10/100, CAN, USB, Security,
Automotive
SAMA5D27C AUTO
Introduction
The SAMA5D27C-CNVAO is a high-performance, ultra-low-power ARM Cortex-A5 processor-based MPU runningup to 500 MHz. It offers support for multiple memories such as DDR2, DDR3, DDR3L, LPDDR1, LPDDR2, LPDDR3,and QSPI Flash and integrates powerful peripherals for connectivity and user interface applications. In addition, it offersadvanced security functions (ARM TrustZone, tamper detection, secure data storage, etc.), as well as high-perfor-mance crypto-processors AES, SHA and TRNG.
Compliant with the international standard ISO-TS-16949, the device is suitable for automotive applications.
The SAMA5D27C-CNVAO is delivered with a free Linux distribution and bare metal C examples.
Features
ARM Cortex-A5 core- ARMv7-A architecture- ARM TrustZone- NEON Media Processing Engine- Up to 500 MHz- ETM/ETB 8 Kbytes
Memory Architecture- Memory Management Unit- 32-Kbyte L1 data cache, 32-Kbyte L1 instruction cache- 128-Kbyte L2 cache configurable to be used as an internal SRAM- One 128-Kbyte scrambled internal SRAM- One 160-Kbyte internal ROM
64-Kbyte scrambled and maskable ROM embedding boot loader/ Secure boot loader 96-Kbyte unscrambled, unmaskable ROM for NAND Flash BCH ECC table
- High-bandwidth scramblable 16-bit or 32-bit Double Data Rate (DDR) multiport dynamic RAM controller sup-porting up to 512 Mbyte 8-bank DDR2/DDR3 (DLL off only) / DDR3L (DLL off only) / LPDDR1/LPDDR2/LPDDR3, including on-the-fly encryption/decryption path
- 8-bit SLC/MLC NAND controller, with up to 32-bit Error Correcting Code (PMECC) System running up to 166 MHz in typical conditions
- Reset controller, shutdown controller, periodic interval timer, independent watchdog timer and secure Real-Time Clock (RTC) with clock calibration
- One 600 to 1200 MHz PLL for the system and one 480 MHz PLL optimized for USB high speed- Digital fractional PLL for audio (11.2896 MHz and 12.288 MHz)- Internal low-power 12 MHz RC and 32 KHz typical RC- Selectable 32.768-Hz low-power oscillator and 8 to 24 MHz oscillator- 51 DMA Channels including two 16-channel 64-bit Central DMA Controllers- 64-bit Advanced Interrupt Controller (AIC)- 64-bit Secure Advanced Interrupt Controller (SAIC)- Three programmable external clock signals
Low-Power Modes- Ultra Low-power mode with fast wakeup capability- Low-power Backup mode with 5-Kbyte SRAM and SleepWalking features
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Wakeup from up to nine wakeup pins, UART reception, analog comparison Fast wakeup capability Extended Backup mode with DDR in Self-Refresh mode
Peripherals- LCD TFT controller up to 1024x768, with four overlays, rotation, post-processing and alpha blending, 24-bit parallel RGB- ITU-R BT. 601/656/1120 Image Sensor Controller (ISC) supporting up to 5 M-pixel sensors with a parallel 12-bit interface for Raw
Bayer, YCbCr, Monochrome and JPEG-compressed sensor interface- Two Synchronous Serial Controllers (SSC), two Inter-IC Sound Controllers (I2SC), and one Stereo Class D amplifier- One Peripheral Touch Controller (PTC) with up to 8 X-lines and 8 Y-lines (64-channel capacitive touch)- One Pulse Density Modulation Interface Controller (PDMIC)- One USB high-speed device port (UDPHS) and one USB high-speed host port or two USB high-speed host ports (UHPHS)- One USB high-speed host port with a High-Speed Inter-Chip (HSIC) interface - One 10/100 Ethernet MAC (GMAC)
Energy efficiency support (IEEE 802.3az standard) Ethernet AVB support with IEEE802.1AS time stamping IEEE802.1Qav credit-based traffic-shaping hardware support IEEE1588 Precision Time Protocol (PTP)
- Two high-speed memory card hosts: SDMMC0: SD 3.0, eMMC 4.51, 8 bits SDMMC1: SD 2.0, eMMC 4.41, 4 bits only
- Two master/slave Serial Peripheral Interfaces (SPI)- Two Quad Serial Peripheral Interfaces (QSPI)- Five FLEXCOMs (USART, SPI and TWI)- Five UARTs- Two master CAN-FD (MCAN) controllers with SRAM-based mailboxes, and time- and event-triggered transmission- One Rx only UART in backup area (RXLP)- One analog comparator (ACC) in backup area- Two 2-wire interfaces (TWIHS) up to 400 Kbits/s supporting the I2C protocol and SMBUS (TWIHS)- Two 3-channel 32-bit Timer/Counters (TC), supporting basic PWM modes- One full-featured 4-channel 16-bit Pulse Width Modulation (PWM) controller- One 12-channel, 12-bit, Analog-to-Digital Converter (ADC) with Resistive TouchScreen capability
Safety- Zero-power Power-On Reset (POR) cells- Main crystal clock failure detector- Write-protected registers- Integrity Check Monitor (ICM) based on SHA256- Memory Management Unit- Independent watchdog
Security- 5 Kbytes of internal scrambled SRAM:
1 Kbyte non-erasable on tamper detection 4 Kbytes erasable on tamper detection
- 256 bits of scrambled and erasable registers- Up to eight tamper pins for static or dynamic intrusion detections- Secure Boot Loader(1)
- On-the-fly AES encryption/decryption on DDR and QSPI memories (AESB)- RTC including time-stamping on security intrusions- Programmable fuse box with 544 fuse bits (including JTAG protection and BMS)Note 1: For secure boot strategies, refer to the document SAMA5D2 Series Secure Boot Strategy (document no. 44040), available
under Non-Disclosure Agreement (NDA). Contact a Microchip Sales Representative for details. Hardware cryptography
- SHA (SHA1, SHA224, SHA256, SHA384, SHA512): compliant with FIPS PUB 180-2- AES: 256-, 192-, 128-bit key algorithm, compliant with FIPS PUB 197- TDES: two-key or three-key algorithms, compliant with FIPS PUB 46-3
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- True Random Number Generator (TRNG) compliant with NIST Special Publication 800-22 Test Suite and FIPS PUBs 140-2 and 140-3
Up to 128 I/Os- Fully programmable through set/clear registers- Multiplexing of up to eight peripheral functions per I/O line- Each I/O line can be assigned to a peripheral or used as a general purpose I/O- The PIO controller features a synchronous output providing up to 32 bits of data output in one write operation
Automotive- Qualification AEC-Q100 grade 2 ([-40C : +105C] ambient temperature)
Packages- 289-ball LFBGA, 14 x 14 mm body, 0.8 mm pitch
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1. DescriptionThe SAMA5D27C-CNVAO is a high-performance, power-efficient embedded MPU based on the ARM Cortex-A5 processor. It integratesthe ARM NEON SIMD engine for accelerated multimedia and signal processing, a configurable 128-Kbyte L2 cache, a floating point unitfor high-precision computing and reliable performance, as well as high data bandwidth architecture. The device features an advanced userinterface and connectivity peripherals. Advanced security is provided by powerful cryptographic accelerators, by the ARM TrustZone tech-nology securing access to memories and sensitive peripherals, and by several hardware features that safeguard memory content, authen-ticate software reliability, detect physical attacks and prevent information leakage during code execution.
The SAMA5D27C-CNVAO features an internal multilayer bus architecture associated with 2 x 16 DMA channels and dedicated DMAs forthe communication and interface peripherals required to ensure uninterrupted data transfers with minimal processor overhead. The devicesupports DDR2, DDR3, DDR3L, LPDDR1, LPDDR2, LPDDR3, and SLC/MLC NAND Flash memory up to 32-bit ECC.
The comprehensive peripheral set includes an LCD TFT controller with overlays for hardware-accelerated image composition, an imagesensor controller, audio support through I2S, SSC, a stereo Class D amplifier and a digital microphone. Connectivity peripherals includea 10/100 EMAC, USBs, CAN-FDs, FLEXCOMs, UARTs, SPIs and two QSPIs, SDIO/SD/e.MMCs, and TWIs/I2C.
Protection of code and data is provided by automatic scrambling of memories and an Integrity Check Monitor (ICM) to detect any modifi-cation of the memory contents. The SAMA5D27C-CNVAO also supports execution of encrypted code (QSPI or one portion of the DDR)with an on-the-fly encryption-decryption process.
With its secure design architecture, cryptographic acceleration engines, and secure boot loader, the SAMA5D27C-CNVAO is the idealsolution for point-of-sale (POS), IoT and industrial applications requiring anti-cloning, data protection and secure communication transfer.
The SAMA5D27C-CNVAO features three software-selectable low-power modes: Idle, Ultra-low-power and Backup.
In Idle mode, the processor is stopped while all other functions can be kept running.
In Ultra-low-power-mode 0, the processor is stopped while all other functions are clocked at 512 Hz and interrupts or peripherals can beconfigured to wake up the system based on events, including partial asynchronous wakeup (SleepWalking).
In Ultra-low-power mode 1, all clocks and functions are stopped but some peripherals can be configured to wake up the system based onevents, including partial asynchronous wakeup (SleepWalking).
In Backup mode, RTC and wakeup logic are active. The Backup mode can be extended to feature DDR in Self-refresh mode.
The SAMA5D27C-CNVAO also includes an Event System that allows peripherals to receive, react to and send events in Active and Idlemodes without processor intervention.
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2. Configuration Summary
For information on device pin compatibility, see Section 7.2 Pinouts.
Table 2-1: Configuration SummaryFeature SAMA5D27C-CNVAO
Package LFBGA289
PIOs 128
DDR Bus 16/32-bit
SMC Up to 16-bit
SRAM 128 Kbytes
QSPI 2
LCD 24-bit RGB
Camera Interface(ISC) 1
EMAC 1
PTC 8 X-lines x 8 Y-lines
CAN 2
USB
3(2 Hosts/1 HSIC
or1 Host/1 Device/1 HSIC)
UART/SPI/I2C 10 / 7 / 7
SDIO/SD/MMC 2
I2S/SSC/Class D/PDM 2 / 2 / 1 / 1
ADC Inputs 12
Timers 6
PWM 4 (PWM) + 6 (TC)
Tamper Pins 8
AESB Yes
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3. Block Diagram
Figure 3-1: Block Diagram
Note: Refer to Section 39. DMA Controller (XDMAC) for peripheral connections to DMA.
SPI0
DM
A
PIO
JTAG / SWD
In-Circuit Emulator
I/D
DM
A DM
A
PIO
DM
A
EBI
DDR2DDR3DDR3L
LPDDR1LPDDR2LPDDR3Controller
Cortex-A5 Processor
MMU
L2 Cache
L1 32-KBDCache
TrustZone
NEONFPU
L1 32-KBICache
DM
A
PIO
PIO
ReducedStatic
MemoryController
NANDFlashController
PMECC(9 KB SRAM)
DM
A
ETMCoreSight
ETB
128 KBL2 or SRAM
PIO
PIO
SSC0
I2SC0
4-ch PWM
TWI0
PDMIC
StereoCLASS
D
12-ch12-bit ADC(+ Resistive
Touchscreen)
160 KB ROM
SHA1/256ICM
TRNG
TDES
ISC
2 xSDMMC
2 x QSPI
4-layerLCDC
CAN0
EMAC10/100
HS EHCIUSB HOSTHS HSIC
HS USBDevice
HS Trans
HS Trans
PC
PB
PA
HS Trans
16-ch DMA1
16-ch DMA0
M
M
M
M
M
S
S S
M
M
S
H64MX Peripheral Bridge
M
S
S
Scr
ambl
ing
M
S
Scr
ambl
ing
Scra
mbl
ing S
3 xUART
2 x FLEXCOM(USART, SPI,
TWI)
128 KBSRAM
DM
A
KeyDigitalAnalogMemories, bridges
PIOBackup AreaSecurity Module
Cryptoprocessor
M MasterS Slave
6 x 32-bitTimers + PWM
(TC)
H32MX Peripheral Bridge 0
PTC
Trus
tZon
e S
ecur
ed M
ultil
ayer
Mat
rix
Scr
ambl
ing
DM
A
CAN1DMA
SPI1
TWI1
I2SC1
SSC1
2 xUART
3 x FLEXCOM(USART, SPI,
TWI)
S
SHA1/256/512
AES128/192/256 AESB
(Bridge to memory)
H32MX Peripheral Bridge 1
PIO POR
PLL UTMI
System Controller
PLLA
12 MHz RC Osc.
Environmental Sensors
Security Module
ACCPOR
Audio PLL Crystal Oscillator(or external Clockin Bypass mode)
Clock Control (PMC)
Fuse Box (SFC)
WDT
Reset Control (RSTC)
256-bitBackup Register
Secure RAM
Shutdown and Wakeup Control
(SHDWC)
RTC
64 kHz RC Osc.
32K Crystal Osc.(or external clockin Bypass mode)
Backup Area
RX UART Wakeup (RXLP)
S
S
M
M
M
S
M
S
8 PIOBU
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4. Signal DescriptionTable 4-1 gives details on signal names classified by peripheral.
Table 4-1: Signal Description List
Signal Name Function Type CommentsActive Level
Clocks, Oscillators and PLLs
XIN Main Oscillator Input Input
XOUT Main Oscillator Output Output
XIN32 Slow Clock Oscillator Input Input
XOUT32 Slow Clock Oscillator Output Output
CLK_AUDIO Audio Clock Output
VBG Bias Voltage Reference for USB Analog
PCK 02 Programmable Clock Output Output
Reset State:
- PIO Input
- Internal Pull-up enabled
- Schmitt Trigger enabled
Shutdown, Wakeup Logic
SHDN Shutdown Control Output
PIOBU 07 Tamper or Wakeup Inputs Input
WKUP Wakeup Input Input
ICE and JTAG
TCK/SWCLK Test Clock/Serial Wire Clock Input
TDI Test Data In Input
TDO Test Data Out Output
TMS/SWDIO Test Mode Select/Serial Wire Input/Output I/O
JTAGSEL JTAG Selection Input
Reset/Test
NRST Microprocessor Reset Input Low
TST Test Mode Select Input
NTRST Test Reset Signal Input
Advanced Interrupt Controller - AIC
IRQ External Interrupt Input Input
Secured Advanced Interrupt Controller - SAIC
FIQ Fast Interrupt Input Input
PIO Controller
PA0PAxx Parallel IO Controller I/O
PB0PBxx Parallel IO Controller I/O
PC0PCxx Parallel IO Controller I/O
PD0PDxx Parallel IO Controller I/O
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External Bus Interface - EBI
D[15:0] Data Bus I/O
A[25:0] Address Bus Output
NWAIT External Wait Signal Input Low
Static Memory Controller - HSMC
NCS0NCS3 Chip Select Lines Output Low
NWR0NWR1 Write Signal Output Low
NRD Read Signal Output Low
NWE Write Enable Output Low
NBS0NBS1 Byte Mask Signal Output Low
NANDOE NAND Flash Output Enable Output Low
NANDWE NAND Flash Write Enable Output Low
DDR2/DDR3/LPDDR1/LPDDR2/LPDDR3 Controller
DDR_CK, DDR_CLKN DDR Differential Clock Output
DDR_CKE DDR Clock Enable OutputWhen Backup Self-refresh mode is used, should be tied to GND using 100 K pull-down
High
DDR_CS DDR Controller Chip Select Output Low
DDR_BA[2:0] Bank Select Output Low
DDR_WE DDR Write Enable Output Low
DDR_RAS, DDR_CAS Row and Column Signal Output Low
DDR_A[13:0] DDR Address Bus Output
DDR_D[31:0] DDR Data Bus I/O/-PD
DDR_DQS[3:0],
DDR_DQSN[3:0]Differential Data Strobe I/O- PD
DDR_DQM[3:0] Write Data Mask Output
DDR_CAL DDR/LPDDR Calibration Input
DDR_VREF DDR/LPDDR Reference Input
DDR_RESETN DDR3 Active Low Asynchronous Reset OutputWhen Backup Self-refresh mode is used, should be tied to VDDIODDR using 100 K pull-up
Secure Data Memory Card - SDMMCx [1:0]
SDMMCx_CD SDcard / e.MMC Card Detect Input
SDMMCx_CMD SDcard / e.MMC Command line I/O
SDMMCx_WP SDcard Connector Write Protect Signal Input
SDMMCx_RSTN e.MMC Reset Signal Output
SDMMCx_1V8SEL SDcard Signal Voltage Selection Output
Table 4-1: Signal Description List (Continued)
Signal Name Function Type CommentsActive Level
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SDMMCx_CK SDcard / e.MMC Clock Signal Output
SDMMCx_DAT[7:0] SDcard / e.MMC Data Lines I/O
Flexible Serial Communication Controller - FLEXCOMx [4:0]
FLEXCOMx_IO0 FLEXCOMx Transmit Data I/O
FLEXCOMx_IO1 FLEXCOMx Receive Data I/O
FLEXCOMx_IO2 FLEXCOMx Serial Clock I/O
FLEXCOMx_IO3 FLEXCOMx Clear To Send / Peripheral Chip Select I/O
FLEXCOMx_IO4 FLEXCOMx Request To Send / Peripheral Chip Select Output
Universal Asynchronous Receiver Transmitter - UARTx [4..0]
UTXDx UARTx Transmit Data Output
URXDx UARTx Receive Data Input
Inter-IC Sound Controller - I2SCx [1..0]
I2SCx_MCK Master Clock Output
I2SCx_CK Serial Clock I/O
I2SCx_WS I2S Word Select I/O
I2SCx_DI0 Serial Data Input Input
I2SCx_DO0 Serial Data Output Output
Synchronous Serial Controller - SSCx [1..0]
TDx SSC Transmit Data Output
RDx SSC Receive Data Input
TKx SSC Transmit Clock I/O
RKx SSC Receive Clock I/O
TFx SSC Transmit Frame Sync I/O
RFx SSC Receive Frame Sync I/O
Timer/Counter - TCx [1..0]
TCLK[5..0] TC Channel y External Clock Input Input
TIOA[5..0] TC Channel y I/O Line A I/O
TIOB[5..0] TC Channel y I/O Line B I/O
Quad IO SPI - QSPIx [1..0]
QSPIx_SCK QSPI Serial Clock Output
QSPIx_CS QSPI Chip Select Output
QSPIx_IO[0..3]QSPI I/O QIO0 is QMOSI Master Out - Slave InQIO1 is QMISO Master In - Slave Out
I/O
Table 4-1: Signal Description List (Continued)
Signal Name Function Type CommentsActive Level
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Serial Peripheral Interface - SPIx [1..0]
SPIx_MISO Master In Slave Out I/O
SPIx_MOSI Master Out Slave In I/O
SPIx_SPCK SPI Serial Clock I/O
SPIx_NPCS0 SPI Peripheral Chip Select 0 I/O Low
SPIx_NPCS[3..1] SPI Peripheral Chip Select Output Low
Two-wire Interface - TWIx [1..0]
TWDx Two-wire Serial Data I/O
TWCKx Two-wire Serial Clock I/O
Pulse Width Modulation Controller - PWM
PWMH03 PWM Waveform Output High Output
PWML03 PWM Waveform Output Low Output
PWMFI01 PWM Fault Inputs Input
PWMEXTRG12 PWM External Trigger Input
USB Host High Speed Port - UHPHS
HHSDPA USB Host Port A High Speed Data + Analog
HHSDMA USB Host Port A High Speed Data - Analog
HHSDPB USB Host Port B High Speed Data + Analog
HHSDMB USB Host Port B High Speed Data - Analog
USB Device High Speed Port - UDPHS
DHSDP USB Device High Speed Data + Analog
DHSDM USB Device High Speed Data - Analog
USB High-Speed Inter-Chip Port - HSIC
HHSTROBE USB High-Speed Inter-Chip Strobe I/O
HHDATA USB High-Speed Inter-Chip Data I/O
Ethernet 10/100 - GMAC
GREFCK Reference Clock Input
GTXCK Transmit Clock Input
GRXCK Receive Clock Input
GTXEN Transmit Enable Output
GTX0GTX3 Transmit Data Output
GTXER Transmit Coding Error Output
GRXDV Receive Data Valid Input
GRX0GRX3 Receive Data Input
GRXER Receive Error Input
GCRS Carrier Sense Input
Table 4-1: Signal Description List (Continued)
Signal Name Function Type CommentsActive Level
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GCOL Collision Detected Input
GMDC Management Data Clock Output
GMDIO Management Data Input/Output I/O
GTSUCOMP TSU timer comparison valid Output
LCD Controller - LCDC
LCDDAT[23:0] LCD Data Bus Output
LCDVSYNC LCD Vertical Synchronization Output
LCDHSYNC LCD Horizontal Synchronization Output
LCDPCK LCD Pixel Clock Output
LCDDEN LCD Data Enable Output
LCDPWM LCDPWM for Contrast Control Output
LCDDISP LCD Display ON/OFF Output
Touchscreen Analog-to-Digital Converter - ADC
AD011 12 Analog Inputs Analog
ADTRG ADC Trigger Input
ADVREF ADC Reference Analog
Secure Box Module - SBM
PIOBU07 Tamper I/Os I/O
Image Sensor Controller - ISC
ISC_D0ISC_D11 Image Sensor Data Input
ISC_HSYNC Image Sensor Horizontal Synchro Input
ISC_VSYNC Image Sensor Vertical Synchro Input
ISC_PCK Image Sensor Pixel clock Input
ISC_MCK Image Sensor Main clock Output
ISC_FIELD Field identification signal Input
Audio Class Amplifier - CLASSD
CLASSD_L0 CLASSD Left Output L0 Output
CLASSD_L1 CLASSD Left Output L1 Output
CLASSD_L2 CLASSD Left Output L2 Output
CLASSD_L3 CLASSD Left Output L3 Output
CLASSD_R0 CLASSD Right Output R0 Output
CLASSD_R1 CLASSD Right Output R1 Output
CLASSD_R2 CLASSD Right Output R2 Output
CLASSD_R3 CLASSD Right Output R3 Output
Table 4-1: Signal Description List (Continued)
Signal Name Function Type CommentsActive Level
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Control Area Network - CAN
CANRXx CAN Receive Input
CANTXx CAN Transmit Output
Peripheral Touch Controller (PTC)
PTC_X[7..0] X-lines I/O
PTC_Y[7..0] Y-lines I
Pulse Density Modulation Interface Controller - PDMIC
PDMIC_DAT PDM Data Input
PDMIC_CLK PDM Clock Output
Table 4-1: Signal Description List (Continued)
Signal Name Function Type CommentsActive Level
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5. Automotive Quality GradeThe SAMA5D27C-CNVAO is compliant with the international standard ISO-TS-16949.
This datasheet contains limit values extracted from the results of extensive characterization (temperature and voltage).
The quality and reliability of the SAMA5D27C-CNVAO has been verified during regular product qualification as per AEC-Q100 grade 2 (40C to +105C).
Table 5-1: Temperature Grade Identification for Automotive ProductsTemperature (C) Temperature Identifier Comments
40C to +105C B AEC-Q100 Grade 2
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6. Safety and Security Features
6.1 Design for Safety and IEC60730 Class B Certification
6.1.1 Background InformationThe IEC 60730 standard encompasses all aspects of appliance design. Annex H of the standard covers the aspects most relevant tomicrocontrollers. It details the tests and diagnostics which are intended to ensure safe operation of embedded control hardware and soft-ware. IEC 60730 defines three classifications for electronic control functions:
Class A - Control functions which are not intended to be relied upon for safety of the equipment Class B - Control functions intended to prevent unsafe operation of the controlled equipment Class C - Control functions intended to prevent special hazards such as explosionsSpecific design techniques have been used in the SAMA5D27C-CNVAO to ease compliance with the IEC 60730 Class B Certification andto resolve general-purpose safety concerns. This allows reduced software development and code size as well as savings on external hard-ware circuitry, since built-in self-tests are already embedded in the MPU. Table 6-1 gives the list of peripherals which incorporate thesetechniques, and details whether these features are applicable for the IEC 60730 Class B Certification or for general-purpose safety con-siderations.
6.2 Design for SecurityThe SAMA5D27C-CNVAO embeds peripherals with security features to prevent counterfeiting, to secure external communication, and toauthenticate the system.
Table 6-2 provides the list of peripherals and an overview of their security function. For more information, see the sections on each periph-eral.
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6.3 Safety and IEC 60730 Features
Table 6-1: Safety and IEC 60730 Features List
Peripheral Component Fault/Error/Feature
Requirements for Class BIEC 60730(1)
General Safety
PMC Clock
CPU clock monitoring
- Overclocking detection X
32.768 kHz crystal oscillator frequency monitoring
- Abnormal frequency deviationX X
Main crystal oscillator
- Crystal failure detectionX X
PIOC
I/O Periphery
Programmable configuration lock (active until next VDDCORE reset) to protect against further software modifications (intentional or unintentional)
X
Digital I/O
- Plausibility checkX
ADCCAnalog I/O and ADC converter
- Plausibility checkX
ICM (SHA) Memory and Internal Data
Path
All internal and external memories such as QSPI, DDR, and all memories on SMC X
NAND Flash Controller ECC
Non-volatile memory
- Mutiple error detection (2 to 32) X
System Controller Supply MonitorPower supplies
- VDDCORE, VDDIO, VDDANA, VDDBU abnormal levels
X
WDT,
RSTCWatchdog
Watchdog can be fed by an internal always ON clock
- Program counter stuck at faults.X X
Watchdog configuration can be locked (write-protected)
- Errant writes (Programming errors, errors introduced by system or hardware failures)
X
Watchdog overflow generates a system reset X X
Cortex MMUMemory
Management Unit
Cortex-A5 Memory Management Unit X
MATRIX, AIC, RTC, SYSC, RXLP, ACC,
PMC, PIO, MPDDRC, SMC, CLASSD, SSC,
TWI, UART, SPI, FLEXCOM, QSPI, TC,
PDMIC, ADC
Peripherals
Configuration, Interrupt Enable/Disable, Control registers can be independently write-protected
- Errant writes (Programming errors, errors introduced by system or hardware failures)
X
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Note 1: Class B IEC 60730 Requirements. Annex H - Table H.1 (H.11.12.7 of edition 3).
PWM,
PIOPWM
Fault inputs can be configured to put the PWM outputs in Safe mode
- Programming errors, errors introduced by system or hardware failures
X
PIO controller can lock the PWM I/O
- Programming errors, errors introduced by system or hardware failures
X
Fault inputs can be external (IO) or internal (ADC, TIMER, ACC, etc.)
- Programming errors, errors introduced by system or hardware failures
X
Table 6-1: Safety and IEC 60730 Features List (Continued)
Peripheral Component Fault/Error/Feature
Requirements for Class BIEC 60730(1)
General Safety
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6.4 Security Features
Table 6-2: Security Features Peripheral Function Description Comments
TrustZone Security Enclave Partition secure/non-secure world ARM technology
Cortex MMUMemory
Management Unit
Cortex-A5 Memory Management Unit
PIO
I/O Control/ Peripheral
Access
When a peripheral is not selected (PIO-controlled), I/O lines have no access to the peripheral.
Freeze Capability to freeze either the functional part or the physical part of the configuration.
Once the freeze command is issued, no modifications to the current configuration are possible. Only a hardware reset allows a change to the configuration.
Classical Atmel Software Crypto LIbrary (CASCL)
Cryptography
Software ECC (Asymmetric key algorithm, elliptic curves) Software library(1)
Software RSA (Asymmetric key algorithm)
TDES, TRNGHardware-accelerated Triple DES
FIPS-compliant(2)True Random Number Generator
AES, SHA
Hardware-accelerated AES up to 256 bits
SHA up to 512 and HMAC-SHA
Secure Boot Code encrypted/decrypted, Trusted Code AuthenticationHardware SHA (HMAC) + Software RSA or AES Hardware (CMAC)
AESB AES on-the-fly On-the-fly encryption/decryption for DDR and QSPI memories AES128
Memories Scrambling On-the-fly scrambling/unscrambling for memoriesAll internal and external memories such as QSPI, DDR, and all memories on SMC
ICMMemory
Integrity Check Monitoring
Uses a hardware Secure Hash Algorithm(up to SHA256)
More robust than CRC.
All internal and external memories such as QSPI, DDR, and all memories on SMC can be monitored
SECUMOD
JTAG JTAG entry monitor These tamper pins (JTAG, test, PIOBUs, monitors, etc.) can be configured to immediately erase Backup memories (BUSRAM4KB and BUREG256b), or generate an interrupt or a wakeup signal.
Test Test entry monitor
IO Tamper Pin 8 tamper detection pins. Active and Dynamic modes supported.
Secure Backup SRAM
5 Kbytes scrambled and non-imprinting avoiding data persistance
4 Kbytes erasable on tamper detection
Secure Backup Registers 256-bit register bank, scrambled Erasable on tamper detection
2018 Microchip Technology Inc. Datasheet DS60001532A-page 17
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SAMA5D27C AUTO
Note 1: A PCI-certified Atmel Software Crypto Library (ASCL) is available under NDA. 2: Refer to the sections on each peripheral for details on FIPS compliancy.
RTC RTC
Timestamping of tamper events. Protection against bad configuration (invalid entry for date and time are impossible)
All events are logged in the RTC. Timestamping gives the source of the reset/erase memory/interruption
RTC robustness against glitch attack on 32 kHz crystal oscillator
Secure Fuse
JTAG Access Control Disable JTAG access by fuse bit
Secure Debug Disable
JTAG debug allowed in Normal mode only, not in Secure mode TrustZone
Table 6-2: Security Features (Continued)Peripheral Function Description Comments
DS60001532A-page 18 2018 Microchip Technology Inc.
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SAMA5D27C AUTO
7. Package and Pinout
7.1 PackagesThe SAMA5D27C-CNVAO is available in the package listed in Table 7-1.
The package mechanical characteristics are described in Section 68. Mechanical Characteristics.
7.2 PinoutsNote: I/Os for each peripheral are grouped into IO sets, listed in the column IO Set in the pinout tables below. For all peripherals, it
is mandatory to use I/Os that belong to the same IO set. The timings are not guaranteed when IOs from different IO sets aremixed.
Table 7-1: PackagesPackage Name Pin Count Ball Pitch
LFBGA289 289 0.8 mm
Table 7-2: Pin Description
289-pin
BGA Power Rail I/O Type
Primary Alternate PIO peripheral Reset State(Signal, Dir, PU, PD,
HiZ, ST)(1)(2)Signal Dir Signal Dir Func Signal DirIOSet
U11 VDDSDMMC GPIO_EMMC PA0 I/O
A SDMMC0_CK I/O 1
PIO, I, PU, STB QSPI0_SCK O 1
F D0 I/O 2
P10 VDDSDMMC GPIO_EMMC PA1 I/O
A SDMMC0_CMD I/O 1
PIO, I, PU, STB QSPI0_CS O 1
F D1 I/O 2
T11 VDDSDMMC GPIO_EMMC PA2 I/O
A SDMMC0_DAT0 I/O 1
PIO, I, PU, STB QSPI0_IO0 I/O 1
F D2 I/O 2
R10 VDDSDMMC GPIO_EMMC PA3 I/O
A SDMMC0_DAT1 I/O 1
PIO, I, PU, STB QSPI0_IO1 I/O 1
F D3 I/O 2
U12 VDDSDMMC GPIO_EMMC PA4 I/O
A SDMMC0_DAT2 I/O 1
PIO, I, PU, STB QSPI0_IO2 I/O 1
F D4 I/O 2
T12 VDDSDMMC GGPIO_EMMC PA5 I/O
A SDMMC0_DAT3 I/O 1
PIO, I, PU, STB QSPI0_IO3 I/O 1
F D5 I/O 2
R12 VDDSDMMC GPIO_EMMC PA6 I/O
A SDMMC0_DAT4 I/O 1
PIO, I, PU, ST
B QSPI1_SCK O 1
D TIOA5 I/O 1
E FLEXCOM2_IO0 I/O 1
F D6 I/O 2
2018 Microchip Technology Inc. Datasheet DS60001532A-page 19
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SAMA5D27C AUTO
T13 VDDSDMMC GPIO_EMMC PA7 I/O
A SDMMC0_DAT5 I/O 1
PIO, I, PU, ST
B QSPI1_IO0 I/O 1
D TIOB5 I/O 1
E FLEXCOM2_IO1 I/O 1
F D7 I/O 2
N10 VDDSDMMC GPIO_EMMC PA8 I/O
A SDMMC0_DAT6 I/O 1
PIO, I, PU, ST
B QSPI1_IO1 I/O 1
D TCLK5 I 1
E FLEXCOM2_IO2 I/O 1
F NWE/NANDWE O 2
N11 VDDSDMMC GPIO_EMMC PA9 I/O
A SDMMC0_DAT7 I/O 1
PIO, I, PU, ST
B QSPI1_IO2 I/O 1
D TIOA4 I/O 1
E FLEXCOM2_IO3 O 1
F NCS3 O 2
U13 VDDSDMMC GPIO_EMMC PA10 I/O
A SDMMC0_RSTN O 1
PIO, I, PU, ST
B QSPI1_IO3 I/O 1
D TIOB4 I/O 1
E FLEXCOM2_IO4 O 1
F A21/NANDALE O 2
P15 VDDIOP1 GPIO PA11 I/O
A SDMMC0_1V8SEL O 1
PIO, I, PU, STB QSPI1_CS O 1
D TCLK4 I 1
F A22/NANDCLE O 2
N15 VDDIOP1 GPIO PA12 I/O
A SDMMC0_WP I 1
PIO, I, PU, STB IRQ I 1
F NRD/NANDOE O 2
P16 VDDIOP1 GPIO PA13 I/O
A SDMMC0_CD I 1
PIO, I, PU, STE FLEXCOM3_IO1 I/O 1
F D8 I/O 2
M14 VDDIOP1 GPIO_QSPI PA14 I/O
A SPI0_SPCK I/O 1
PIO, I, PU, ST
B TK1 I/O 1
C QSPI0_SCK O 2
D I2SC1_MCK O 2
E FLEXCOM3_IO2 I/O 1
F D9 I/O 2
Table 7-2: Pin Description (Continued)
289-pin
BGA Power Rail I/O Type
Primary Alternate PIO peripheral Reset State(Signal, Dir, PU, PD,
HiZ, ST)(1)(2)Signal Dir Signal Dir Func Signal DirIOSet
DS60001532A-page 20 2018 Microchip Technology Inc.
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SAMA5D27C AUTO
N16 VDDIOP1 GPIO PA15 I/O
A SPI0_MOSI I/O 1
PIO, I, PU, ST
B TF1 I/O 1
C QSPI0_CS O 2
D I2SC1_CK I/O 2
E FLEXCOM3_IO0 I/O 1
F D10 I/O 2
M10 VDDIOP1 GPIO_IO PA16 I/O
A SPI0_MISO I/O 1
PIO, I, PU, ST
B TD1 O 1
C QSPI0_IO0 I/O 2
D I2SC1_WS I/O 2
E FLEXCOM3_IO3 O 1
F D11 I/O 2
N17 VDDIOP1 GPIO_IO PA17 I/O
A SPI0_NPCS0 I/O 1
PIO, I, PU, ST
B RD1 I 1
C QSPI0_IO1 I/O 2
D I2SC1_DI0 I 2
E FLEXCOM3_IO4 O 1
F D12 I/O 2
U14 VDDIOP1 GPIO_IO PA18 I/O
A SPI0_NPCS1 O 1
PIO, I, PU, ST
B RK1 I/O 1
C QSPI0_IO2 I/O 2
D I2SC1_DO0 O 2
E SDMMC1_DAT0 I/O 1
F D13 I/O 2
T14 VDDIOP1 GPIO_IO PA19 I/O
A SPI0_NPCS2 O 1
PIO, I, PU, ST
B RF1 I/O 1
C QSPI0_IO3 I/O 2
D TIOA0 I/O 1
E SDMMC1_DAT1 I/O 1
F D14 I/O 2
P12 VDDIOP1 GPIO_IO PA20 I/O
A SPI0_NPCS3 O 1
PIO, I, PU, STD TIOB0 I/O 1
E SDMMC1_DAT2 I/O 1
F D15 I/O 2
Table 7-2: Pin Description (Continued)
289-pin
BGA Power Rail I/O Type
Primary Alternate PIO peripheral Reset State(Signal, Dir, PU, PD,
HiZ, ST)(1)(2)Signal Dir Signal Dir Func Signal DirIOSet
2018 Microchip Technology Inc. Datasheet DS60001532A-page 21
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SAMA5D27C AUTO
R13 VDDIOP1 GPIO_IO PA21 I/O
A IRQ I 2
PIO, I, PU, ST
B PCK2 O 3
D TCLK0 I 1
E SDMMC1_DAT3 I/O 1
F NANDRDY I 2
U15 VDDIOP1 GPIO_QSPI PA22 I/O
A FLEXCOM1_IO2 I/O 1
PIO, I, PU, ST
B D0 I/O 1
C TCK I 4
D SPI1_SPCK I/O 2
E SDMMC1_CK I/O 1
F QSPI0_SCK O 3
U16 VDDIOP1 GPIO PA23 I/O
A FLEXCOM1_IO1 I/O 1
PIO, I, PU, ST
B D1 I/O 1
C TDI I 4
D SPI1_MOSI I/O 2
F QSPI0_CS O 3
T15 VDDIOP1 GPIO_IO PA24 I/O
A FLEXCOM1_IO0 I/O 1
PIO, I, PU, ST
B D2 I/O 1
C TDO O 4
D SPI1_MISO I/O 2
F QSPI0_IO0 I/O 3
U17 VDDIOP1 GPIO_IO PA25 I/O
A FLEXCOM1_IO3 O 1
PIO, I, PU, ST
B D3 I/O 1
C TMS I 4
D SPI1_NPCS0 I/O 2
F QSPI0_IO1 I/O 3
P13 VDDIOP1 GPIO_IO PA26 I/O
A FLEXCOM1_IO4 O 1
PIO, I, PU, ST
B D4 I/O 1
C NTRST I 4
D SPI1_NPCS1 O 2
F QSPI0_IO2 I/O 3
T16 VDDIOP1 GPIO_IO PA27 I/O
A TIOA1 I/O 2
PIO, I, PU, ST
B D5 I/O 1
C SPI0_NPCS2 O 2
D SPI1_NPCS2 O 2
E SDMMC1_RSTN O 1
F QSPI0_IO3 I/O 3
Table 7-2: Pin Description (Continued)
289-pin
BGA Power Rail I/O Type
Primary Alternate PIO peripheral Reset State(Signal, Dir, PU, PD,
HiZ, ST)(1)(2)Signal Dir Signal Dir Func Signal DirIOSet
DS60001532A-page 22 2018 Microchip Technology Inc.
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SAMA5D27C AUTO
R16 VDDIOP1 GPIO PA28 I/O
A TIOB1 I/O 2
PIO, I, PU, ST
B D6 I/O 1
C SPI0_NPCS3 O 2
D SPI1_NPCS3 O 2
E SDMMC1_CMD I/O 1
F CLASSD_L0 O 1
T17 VDDIOP1 GPIO PA29 I/O
A TCLK1 I 2
PIO, I, PU, ST
B D7 I/O 1
C SPI0_NPCS1 O 2
E SDMMC1_WP I 1
F CLASSD_L1 O 1
R15 VDDIOP1 GPIO PA30 I/O
B NWE/NANDWE O 1
PIO, I, PU, ST
C SPI0_NPCS0 I/O 2
D PWMH0 O 1
E SDMMC1_CD I 1
F CLASSD_L2 O 1
R17 VDDIOP1 GPIO PA31 I/O
B NCS3 O 1
PIO, I, PU, STC SPI0_MISO I/O 2
D PWML0 O 1
F CLASSD_L3 O 1
J8 VDDIOP0 GPIO PB0 I/O
B A21/NANDALE O 1
PIO, I, PU, STC SPI0_MOSI I/O 2
D PWMH1 O 1
A8 VDDIOP0 GPIO PB1 I/O
B A22/NANDCLE O 1
PIO, I, PU, STC SPI0_SPCK I/O 2
D PWML1 O 1
F CLASSD_R0 O 1
A7 VDDIOP0 GPIO PB2 I/O
B NRD/NANDOE O 1
PIO, I, PU, STD PWMFI0 I 1
F CLASSD_R1 O 1
A6 VDDIOP0 GPIO PB3 I/O
A URXD4 I 1
PIO, I, PU, ST
B D8 I/O 1
C IRQ I 3
D PWMEXTRG1 I 1
F CLASSD_R2 O 1
Table 7-2: Pin Description (Continued)
289-pin
BGA Power Rail I/O Type
Primary Alternate PIO peripheral Reset State(Signal, Dir, PU, PD,
HiZ, ST)(1)(2)Signal Dir Signal Dir Func Signal DirIOSet
2018 Microchip Technology Inc. Datasheet DS60001532A-page 23
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SAMA5D27C AUTO
B6 VDDIOP0 GPIO PB4 I/O
A UTXD4 O 1
PIO, I, PU, STB D9 I/O 1
C FIQ I 4
F CLASSD_R3 O 1
B7 VDDIOP0 GPIO_QSPI PB5 I/O
A TCLK2 I 1
PIO, I, PU, ST
B D10 I/O 1
C PWMH2 O 1
D QSPI1_SCK O 2
F GTSUCOMP O 3
C7 VDDIOP0 GPIO PB6 I/O
A TIOA2 I/O 1
PIO, I, PU, ST
B D11 I/O 1
C PWML2 O 1
D QSPI1_CS O 2
F GTXER O 3
C6 VDDIOP0 GPIO_IO PB7 I/O
A TIOB2 I/O 1
PIO, I, PU, ST
B D12 I/O 1
C PWMH3 O 1
D QSPI1_IO0 I/O 2
F GRXCK I 3
A5 VDDIOP0 GPIO_IO PB8 I/O
A TCLK3 I 1
PIO, I, PU, ST
B D13 I/O 1
C PWML3 O 1
D QSPI1_IO1 I/O 2
F GCRS I 3
A4 VDDIOP0 GPIO_IO PB9 I/O
A TIOA3 I/O 1
PIO, I, PU, ST
B D14 I/O 1
C PWMFI1 I 1
D QSPI1_IO2 I/O 2
F GCOL I 3
H8 VDDIOP0 GPIO_IO PB10 I/O
A TIOB3 I/O 1
PIO, I, PU, ST
B D15 I/O 1
C PWMEXTRG2 I 1
D QSPI1_IO3 I/O 2
F GRX2 I 3
Table 7-2: Pin Description (Continued)
289-pin
BGA Power Rail I/O Type
Primary Alternate PIO peripheral Reset State(Signal, Dir, PU, PD,
HiZ, ST)(1)(2)Signal Dir Signal Dir Func Signal DirIOSet
DS60001532A-page 24 2018 Microchip Technology Inc.
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SAMA5D27C AUTO
B5 VDDIOP0 GPIO PB11 I/O
A LCDDAT0 O 1
PIO, I, PU, ST
B A0/NBS0 O 1
C URXD3 I 3
D PDMIC_DAT 2
F GRX3 I 3
D6 VDDIOP0 GPIO PB12 I/O
A LCDDAT1 O 1
PIO, I, PU, ST
B A1 O 1
C UTXD3 O 3
D PDMIC_CLK 2
F GTX2 O 3
B4 VDDIOP0 GPIO PB13 I/O
A LCDDAT2 O 1
PIO, I, PU, STB A2 O 1
C PCK1 O 3
F GTX3 O 3
C5 VDDIOP0 GPIO_QSPI PB14 I/O
A LCDDAT3 O 1
PIO, I, PU, ST
B A3 O 1
C TK1 I/O 2
D I2SC1_MCK O 1
E QSPI1_SCK O 3
F GTXCK I/O 3
H7 VDDIOP0 GPIO PB15 I/O
A LCDDAT4 O 1
PIO, I, PU, ST
B A4 O 1
C TF1 I/O 2
D I2SC1_CK I/O 1
E QSPI1_CS O 3
F GTXEN O 3
D5 VDDIOP0 GPIO_IO PB16 I/O
A LCDDAT5 O 1
PIO, I, PU, ST
B A5 O 1
C TD1 O 2
D I2SC1_WS I/O 1
E QSPI1_IO0 I/O 3
F GRXDV I 3
Table 7-2: Pin Description (Continued)
289-pin
BGA Power Rail I/O Type
Primary Alternate PIO peripheral Reset State(Signal, Dir, PU, PD,
HiZ, ST)(1)(2)Signal Dir Signal Dir Func Signal DirIOSet
2018 Microchip Technology Inc. Datasheet DS60001532A-page 25
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SAMA5D27C AUTO
C4 VDDIOP0 GPIO_IO PB17 I/O
A LCDDAT6 O 1
PIO, I, PU, ST
B A6 O 1
C RD1 I 2
D I2SC1_DI0 I 1
E QSPI1_IO1 I/O 3
F GRXER I 3
A3 VDDIOP0 GPIO_IO PB18 I/O
A LCDDAT7 O 1
PIO, I, PU, ST
B A7 O 1
C RK1 I/O 2
D I2SC1_DO0 O 1
E QSPI1_IO2 I/O 3
F GRX0 I 3
D4 VDDIOP0 GPIO_IO PB19 I/O
A LCDDAT8 O 1
PIO, I, PU, ST
B A8 O 1
C RF1 I/O 2
D TIOA3 I/O 2
E QSPI1_IO3 I/O 3
F GRX1 I 3
B3 VDDIOP0 GPIO PB20 I/O
A LCDDAT9 O 1
PIO, I, PU, ST
B A9 O 1
C TK0 I/O 1
D TIOB3 I/O 2
E PCK1 O 4
F GTX0 O 3
A2 VDDIOP0 GPIO PB21 I/O
A LCDDAT10 O 1
PIO, I, PU, ST
B A10 O 1
C TF0 I/O 1
D TCLK3 I 2
E FLEXCOM3_IO2 I/O 3
F GTX1 O 3
C3 VDDIOP0 GPIO PB22 I/O
A LCDDAT11 O 1
PIO, I, PU, ST
B A11 O 1
C TD0 O 1
D TIOA2 I/O 2
E FLEXCOM3_IO1 I/O 3
F GMDC O 3
Table 7-2: Pin Description (Continued)
289-pin
BGA Power Rail I/O Type
Primary Alternate PIO peripheral Reset State(Signal, Dir, PU, PD,
HiZ, ST)(1)(2)Signal Dir Signal Dir Func Signal DirIOSet
DS60001532A-page 26 2018 Microchip Technology Inc.
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SAMA5D27C AUTO
A1 VDDIOP0 GPIO PB23 I/O
A LCDDAT12 O 1
PIO, I, PU, ST
B A12 O 1
C RD0 I 1
D TIOB2 I/O 2
E FLEXCOM3_IO0 I/O 3
F GMDIO I/O 3
E5 VDDIOP0 GPIO PB24 I/O
A LCDDAT13 O 1
PIO, I, PU, ST
B A13 O 1
C RK0 I/O 1
D TCLK2 I 2
E FLEXCOM3_IO3 O 3
F ISC_D10 I 3
B2 VDDIOP0 GPIO PB25 I/O
A LCDDAT14 O 1
PIO, I, PU, ST
B A14 O 1
C RF0 I/O 1
E FLEXCOM3_IO4 O 3
F ISC_D11 I 3
E4 VDDIOP0 GPIO PB26 I/O
A LCDDAT15 O 1
PIO, I, PU, ST
B A15 O 1
C URXD0 I 1
D PDMIC_DAT 1
F ISC_D0 I 3
B1 VDDIOP0 GPIO PB27 I/O
A LCDDAT16 O 1
PIO, I, PU, ST
B A16 O 1
C UTXD0 O 1
D PDMIC_CLK 1
F ISC_D1 I 3
C2 VDDIOP0 GPIO PB28 I/O
A LCDDAT17 O 1
PIO, I, PU, ST
B A17 O 1
C FLEXCOM0_IO0 I/O 1
D TIOA5 I/O 2
F ISC_D2 I 3
D3 VDDIOP0 GPIO PB29 I/O
A LCDDAT18 O 1
PIO, I, PU, ST
B A18 O 1
C FLEXCOM0_IO1 I/O 1
D TIOB5 I/O 2
F ISC_D3 I 3
Table 7-2: Pin Description (Continued)
289-pin
BGA Power Rail I/O Type
Primary Alternate PIO peripheral Reset State(Signal, Dir, PU, PD,
HiZ, ST)(1)(2)Signal Dir Signal Dir Func Signal DirIOSet
2018 Microchip Technology Inc. Datasheet DS60001532A-page 27
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SAMA5D27C AUTO
D2 VDDIOP0 GPIO PB30 I/O
A LCDDAT19 O 1
PIO, I, PU, ST
B A19 O 1
C FLEXCOM0_IO2 I/O 1
D TCLK5 I 2
F ISC_D4 I 3
C1 VDDIOP0 GPIO PB31 I/O
A LCDDAT20 O 1
PIO, I, PU, ST
B A20 O 1
C FLEXCOM0_IO3 O 1
D TWD0 I/O 1
F ISC_D5 I 3
P17 VDDIOP1 GPIO PC0 I/O
A LCDDAT21 O 1
PIO, I, PU, ST
B A23 O 1
C FLEXCOM0_IO4 O 1
D TWCK0 I/O 1
F ISC_D6 I 3
N12 VDDIOP1 GPIO PC1 I/O
A LCDDAT22 O 1
PIO, I, PU, ST
B A24 O 1
C CANTX0 O 1
D SPI1_SPCK I/O 1
E I2SC0_CK I/O 1
F ISC_D7 I 3
N14 VDDIOP1 GPIO PC2 I/O
A LCDDAT23 O 1
PIO, I, PU, ST
B A25 O 1
C CANRX0 I 1
D SPI1_MOSI I/O 1
E I2SC0_MCK O 1
F ISC_D8 I 3
M15 VDDIOP1 GPIO PC3 I/O
A LCDPWM O 1
PIO, I, PU, ST
B NWAIT I 1
C TIOA1 I/O 1
D SPI1_MISO I/O 1
E I2SC0_WS I/O 1
F ISC_D9 I 3
Table 7-2: Pin Description (Continued)
289-pin
BGA Power Rail I/O Type
Primary Alternate PIO peripheral Reset State(Signal, Dir, PU, PD,
HiZ, ST)(1)(2)Signal Dir Signal Dir Func Signal DirIOSet
DS60001532A-page 28 2018 Microchip Technology Inc.
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SAMA5D27C AUTO
M11 VDDIOP1 GPIO PC4 I/O
A LCDDISP O 1
PIO, I, PU, ST
B NWR1/NBS1 O 1
C TIOB1 I/O 1
D SPI1_NPCS0 I/O 1
E I2SC0_DI0 I 1
F ISC_PCK I 3
L10 VDDIOP1 GPIO PC5 I/O
A LCDVSYNC O 1
PIO, I, PU, ST
B NCS0 O 1
C TCLK1 I 1
D SPI1_NPCS1 O 1
E I2SC0_DO0 O 1
F ISC_VSYNC I 3
K10 VDDIOP1 GPIO PC6 I/O
A LCDHSYNC O 1
PIO, I, PU, ST
B NCS1 O 1
C TWD1 I/O 1
D SPI1_NPCS2 O 1
F ISC_HSYNC I 3
M16 VDDIOP1 GPIO_CLK PC7 I/O
A LCDPCK O 1
PIO, I, PU, ST
B NCS2 O 1
C TWCK1 I/O 1
D SPI1_NPCS3 O 1
E URXD1 I 2
F ISC_MCK O 3
J10 VDDIOP1 GPIO PC8 I/O
A LCDDEN O 1
PIO, I, PU, ST
B NANDRDY I 1
C FIQ I 1
D PCK0 O 3
E UTXD1 O 2
F ISC_FIELD I 3
D1 VDDISC GPIO PC9 I/O
A FIQ I 3
PIO, I, PU, STB GTSUCOMP O 1
C ISC_D0 I 1
D TIOA4 I/O 2
Table 7-2: Pin Description (Continued)
289-pin
BGA Power Rail I/O Type
Primary Alternate PIO peripheral Reset State(Signal, Dir, PU, PD,
HiZ, ST)(1)(2)Signal Dir Signal Dir Func Signal DirIOSet
2018 Microchip Technology Inc. Datasheet DS60001532A-page 29
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SAMA5D27C AUTO
E3 VDDISC GPIO PC10 I/O
A LCDDAT2 O 2
PIO, I, PU, ST
B GTXCK I/O 1
C ISC_D1 I 1
D TIOB4 I/O 2
E CANTX0 O 2
E2 VDDISC GPIO PC11 I/O
A LCDDAT3 O 2
PIO, I, PU, ST
B GTXEN O 1
C ISC_D2 I 1
D TCLK4 I 2
E CANRX0 I 2
F A0/NBS0 O 2
E1 VDDISC GPIO PC12 I/O
A LCDDAT4 O 2
PIO, I, PU, ST
B GRXDV I 1
C ISC_D3 I 1
D URXD3 I 1
E TK0 I/O 2
F A1 O 2
F3 VDDISC GPIO PC13 I/O
A LCDDAT5 O 2
PIO, I, PU, ST
B GRXER I 1
C ISC_D4 I 1
D UTXD3 O 1
E TF0 I/O 2
F A2 O 2
F5 VDDISC GPIO PC14 I/O
A LCDDAT6 O 2
PIO, I, PU, ST
B GRX0 I 1
C ISC_D5 I 1
E TD0 O 2
F A3 O 2
F2 VDDISC GPIO PC15 I/O
A LCDDAT7 O 2
PIO, I, PU, ST
B GRX1 I 1
C ISC_D6 I 1
E RD0 I 2
F A4 O 2
Table 7-2: Pin Description (Continued)
289-pin
BGA Power Rail I/O Type
Primary Alternate PIO peripheral Reset State(Signal, Dir, PU, PD,
HiZ, ST)(1)(2)Signal Dir Signal Dir Func Signal DirIOSet
DS60001532A-page 30 2018 Microchip Technology Inc.
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SAMA5D27C AUTO
G6 VDDISC GPIO PC16 I/O
A LCDDAT10 O 2
PIO, I, PU, ST
B GTX0 O 1
C ISC_D7 I 1
E RK0 I/O 2
F A5 O 2
F1 VDDISC GPIO PC17 I/O
A LCDDAT11 O 2
PIO, I, PU, ST
B GTX1 O 1
C ISC_D8 I 1
E RF0 I/O 2
F A6 O 2
H6 VDDISC GPIO PC18 I/O
A LCDDAT12 O 2
PIO, I, PU, ST
B GMDC O 1
C ISC_D9 I 1
E FLEXCOM3_IO2 I/O 2
F A7 O 2
G2 VDDISC GPIO PC19 I/O
A LCDDAT13 O 2
PIO, I, PU, ST
B GMDIO I/O 1
C ISC_D10 I 1
E FLEXCOM3_IO1 I/O 2
F A8 O 2
G3 VDDISC GPIO PC20 I/O
A LCDDAT14 O 2
PIO, I, PU, ST
B GRXCK I 1
C ISC_D11 I 1
E FLEXCOM3_IO0 I/O 2
F A9 O 2
G1 VDDISC GPIO PC21 I/O
A LCDDAT15 O 2
PIO, I, PU, ST
B GTXER O 1
C ISC_PCK I 1
E FLEXCOM3_IO3 O 2
F A10 O 2
H2 VDDISC GPIO PC22 I/O
A LCDDAT18 O 2
PIO, I, PU, ST
B GCRS I 1
C ISC_VSYNC I 1
E FLEXCOM3_IO4 O 2
F A11 O 2
Table 7-2: Pin Description (Continued)
289-pin
BGA Power Rail I/O Type
Primary Alternate PIO peripheral Reset State(Signal, Dir, PU, PD,
HiZ, ST)(1)(2)Signal Dir Signal Dir Func Signal DirIOSet
2018 Microchip Technology Inc. Datasheet DS60001532A-page 31
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SAMA5D27C AUTO
G5 VDDISC GPIO PC23 I/O
A LCDDAT19 O 2
PIO, I, PU, STB GCOL I 1
C ISC_HSYNC I 1
F A12 O 2
H1 VDDISC GPIO_CLK PC24 I/O
A LCDDAT20 O 2
PIO, I, PU, STB GRX2 I 1
C ISC_MCK O 1
F A13 O 2
H5 VDDISC GPIO PC25 I/O
A LCDDAT21 O 2
PIO, I, PU, STB GRX3 I 1
C ISC_FIELD I 1
F A14 O 2
J9 VDDIOP2 GPIO PC26 I/O
A LCDDAT22 O 2
PIO, I, PU, STB GTX2 O 1
D CANTX1 O 1
F A15 O 2
H9 VDDIOP2 GPIO PC27 I/O
A LCDDAT23 O 2
PIO, I, PU, ST
B GTX3 O 1
C PCK1 O 2
D CANRX1 I 1
E TWD0 I/O 2
F A16 O 2
E8 VDDIOP2 GPIO PC28 I/O
A LCDPWM O 2
PIO, I, PU, ST
B FLEXCOM4_IO0 I/O 1
C PCK2 O 1
E TWCK0 I/O 2
F A17 O 2
G8 VDDIOP2 GPIO PC29 I/O
A LCDDISP O 2
PIO, I, PU, STB FLEXCOM4_IO1 I/O 1
F A18 O 2
F8 VDDIOP2 GPIO PC30 I/O
A LCDVSYNC O 2
PIO, I, PU, STB FLEXCOM4_IO2 I/O 1
F A19 O 2
D8 VDDIOP2 GPIO PC31 I/O
A LCDHSYNC O 2
PIO, I, PU, STB FLEXCOM4_IO3 O 1
C URXD3 I 2
F A20 O 2
Table 7-2: Pin Description (Continued)
289-pin
BGA Power Rail I/O Type
Primary Alternate PIO peripheral Reset State(Signal, Dir, PU, PD,
HiZ, ST)(1)(2)Signal Dir Signal Dir Func Signal DirIOSet
DS60001532A-page 32 2018 Microchip Technology Inc.
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SAMA5D27C AUTO
G10 VDDIOP2 GPIO_CLK PD0 I/O
A LCDPCK O 2
PIO, I, PU, ST
B FLEXCOM4_IO4 O 1
C UTXD3 O 2
D GTSUCOMP O 2
F A23 O 2
E10 VDDIOP2 GPIO PD1 I/O
A LCDDEN O 2
PIO, I, PU, STD GRXCK I 2
F A24 O 2
G9 VDDIOP2 GPIO_CLK PD2 I/O
A URXD1 I 1
PIO, I, PU, STD GTXER O 2
E ISC_MCK O 2
F A25 O 2
K1 VDDANA GPIO_AD PD3 I/O PTC_X0
A UTXD1 O 1
PIO, I, PU, ST
B FIQ I 2
D GCRS I 2
E ISC_D11 I 2
F NWAIT I 2
J6 VDDANA GPIO_AD PD4 I/O PTC_X1
A TWD1 I/O 2
PIO, I, PU, ST
B URXD2 I 1
D GCOL I 2
E ISC_D10 I 2
F NCS0 O 2
J4 VDDANA GPIO_AD PD5 I/O PTC_X2
A TWCK1 I/O 2
PIO, I, PU, ST
B UTXD2 O 1
D GRX2 I 2
E ISC_D9 I 2
F NCS1 O 2
J2 VDDANA GPIO_AD PD6 I/O PTC_X3
A TCK I 2
PIO, I, PU, ST
B PCK1 O 1
D GRX3 I 2
E ISC_D8 I 2
F NCS2 O 2
J7 VDDANA GPIO_AD PD7 I/O PTC_X4
A TDI I 2
PIO, I, PU, ST
C UTMI_RXVAL O 1
D GTX2 O 2
E ISC_D0 I 2
F NWR1/NBS1 O 2
Table 7-2: Pin Description (Continued)
289-pin
BGA Power Rail I/O Type
Primary Alternate PIO peripheral Reset State(Signal, Dir, PU, PD,
HiZ, ST)(1)(2)Signal Dir Signal Dir Func Signal DirIOSet
2018 Microchip Technology Inc. Datasheet DS60001532A-page 33
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J1 VDDANA GPIO_AD PD8 I/O PTC_X5
A TDO O 2
PIO, I, PU, ST
C UTMI_RXERR O 1
D GTX3 O 2
E ISC_D1 I 2
F NANDRDY I 2
K9 VDDANA GPIO_AD PD9 I/O PTC_X6
A TMS I 2
PIO, I, PU, STC UTMI_RXACT O 1
D GTXCK I/O 2
E ISC_D2 I 2
J3 VDDANA GPIO_AD PD10 I/O PTC_X7
A NTRST I 2
PIO, I, PU, STC UTMI_HDIS O 1
D GTXEN O 2
E ISC_D3 I 2
M1 VDDANA GPIO_AD PD11 I/O PTC_Y0
A TIOA1 I/O 3
PIO, I, PU, ST
B PCK2 O 2
C UTMI_LS0 O 1
D GRXDV I 2
E ISC_D4 I 2
F ISC_MCK O 4
K8 VDDANA GPIO_AD PD12 I/O PTC_Y1
A TIOB1 I/O 3
PIO, I, PU, ST
B FLEXCOM4_IO0 I/O 2
C UTMI_LS1 O 1
D GRXER I 2
E ISC_D5 I 2
F ISC_D4 I 4
L2 VDDANA GPIO_AD PD13 I/O PTC_Y2
A TCLK1 I 3
PIO, I, PU, ST
B FLEXCOM4_IO1 I/O 2
C UTMI_CDRCPSEL0 I 1
D GRX0 I 2
E ISC_D6 I 2
F ISC_D5 I 4
K4 VDDANA GPIO_AD PD14 I/O PTC_Y3
A TCK I 1
A, PU, ST
B FLEXCOM4_IO2 I/O 2
C UTMI_CDRCPSEL1 I 1
D GRX1 I 2
E ISC_D7 I 2
F ISC_D6 I 4
Table 7-2: Pin Description (Continued)
289-pin
BGA Power Rail I/O Type
Primary Alternate PIO peripheral Reset State(Signal, Dir, PU, PD,
HiZ, ST)(1)(2)Signal Dir Signal Dir Func Signal DirIOSet
DS60001532A-page 34 2018 Microchip Technology Inc.
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SAMA5D27C AUTO
K7 VDDANA GPIO_AD PD15 I/O PTC_Y4
A TDI I 1
PIO, I, PU, ST
B FLEXCOM4_IO3 O 2
C UTMI_CDRCPDIVEN I 1
D GTX0 O 2
E ISC_PCK I 2
F ISC_D7 I 4
L1 VDDANA GPIO_AD PD16 I/O PTC_Y5
A TDO O 1
PIO, I, PU, ST
B FLEXCOM4_IO4 O 2
C UTMI_CDRBISTEN I 1
D GTX1 O 2
E ISC_VSYNC I 2
F ISC_D8 I 4
K2 VDDANA GPIO_AD PD17 I/O PTC_Y6
A TMS I 1
A, PU, ST
C UTMI_CDRCPSELDIV O 1
D GMDC O 2
E ISC_HSYNC I 2
F ISC_D9 I 4
J5 VDDANA GPIO_AD PD18 I/O PTC_Y7
A NTRST I 1
PIO, I, PU, STD GMDIO I/O 2
E ISC_FIELD I 2
F ISC_D10 I 4
K6 VDDANA GPIO_AD PD19 I/O AD0
A PCK0 O 1
PIO, I, PU, ST
B TWD1 I/O 3
C URXD2 I 3
E I2SC0_CK I/O 2
F ISC_D11 I 4
M2 VDDANA GPIO_AD PD20 I/O AD1
A TIOA2 I/O 3
PIO, I, PU, ST
B TWCK1 I/O 3
C UTXD2 O 3
E I2SC0_MCK O 2
F ISC_PCK I 4
N1 VDDANA GPIO_AD PD21 I/O AD2
A TIOB2 I/O 3
PIO, I, PU, ST
B TWD0 I/O 4
C FLEXCOM4_IO0 I/O 3
E I2SC0_WS I/O 2
F ISC_VSYNC I 4
Table 7-2: Pin Description (Continued)
289-pin
BGA Power Rail I/O Type
Primary Alternate PIO peripheral Reset State(Signal, Dir, PU, PD,
HiZ, ST)(1)(2)Signal Dir Signal Dir Func Signal DirIOSet
2018 Microchip Technology Inc. Datasheet DS60001532A-page 35
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L4 VDDANA GPIO_AD PD22 I/O AD3
A TCLK2 I 3
PIO, I, PU, ST
B TWCK0 I/O 4
C FLEXCOM4_IO1 I/O 3
E I2SC0_DI0 I 2
F ISC_HSYNC I 4
M3 VDDANA GPIO_AD PD23 I/O AD4
A URXD2 I 2
PIO, I, PU, STC FLEXCOM4_IO2 I/O 3
E I2SC0_DO0 O 2
F ISC_FIELD I 4
L7 VDDANA GPIO_AD PD24 I/O AD5 A UTXD2 O 2
PIO, I, PU, STC FLEXCOM4_IO3 O 3
L6 VDDANA GPIO_AD PD25 I/O AD6 A SPI1_SPCK I/O 3
PIO, I, PU, STC FLEXCOM4_IO4 O 3
N2 VDDANA GPIO_AD PD26 I/O AD7 A SPI1_MOSI I/O 3
PIO, I, PU, STC FLEXCOM2_IO0 I/O 2
L8 VDDANA GPIO_AD PD27 I/O AD8
A SPI1_MISO I/O 3
PIO, I, PU, STB TCK I 3
C FLEXCOM2_IO1 I/O 2
M4 VDDANA GPIO_AD PD28 I/O AD9
A SPI1_NPCS0 I/O 3
PIO, I, PU, STB TDI I 3
C FLEXCOM2_IO2 I/O 2
N3 VDDANA GPIO_AD PD29 I/O AD10
A SPI1_NPCS1 O 3
PIO, I, PU, ST
B TDO O 3
C FLEXCOM2_IO3 O 2
D TIOA3 I/O 3
E TWD0 I/O 3
L9 VDDANA GPIO_AD PD30 I/O AD11
A SPI1_NPCS2 O 3
PIO, I, PU, ST
B TMS I 3
C FLEXCOM2_IO4 O 2
D TIOB3 I/O 3
E TWCK0 I/O 3
M7 VDDANA GPIO PD31 I/O
A ADTRG I 1
PIO, I, PU, ST
B NTRST I 3
C IRQ I 4
D TCLK3 I 3
E PCK0 O 2
L5 VDDANA power VDDANA I
Table 7-2: Pin Description (Continued)
289-pin
BGA Power Rail I/O Type
Primary Alternate PIO peripheral Reset State(Signal, Dir, PU, PD,
HiZ, ST)(1)(2)Signal Dir Signal Dir Func Signal DirIOSet
DS60001532A-page 36 2018 Microchip Technology Inc.
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SAMA5D27C AUTO
K5 GNDANA ground GNDANA I
M6 VDDANA ADVREF I
K3 VDDANA power VDDANA I
L3 GNDANA ground GNDANA I
H16,D16 VDDIODDR DDR DDR_VREF
B12 VDDIODDR DDR DDR_D0
A12 VDDIODDR DDR DDR_D1
C12 VDDIODDR DDR DDR_D2
A13 VDDIODDR DDR DDR_D3
A14 VDDIODDR DDR DDR_D4
C13 VDDIODDR DDR DDR_D5
A15 VDDIODDR DDR DDR_D6
B15 VDDIODDR DDR DDR_D7
G17 VDDIODDR DDR DDR_D8
G16 VDDIODDR DDR DDR_D9
H17 VDDIODDR DDR DDR_D10
K17 VDDIODDR DDR DDR_D11
K16 VDDIODDR DDR DDR_D12
J13 VDDIODDR DDR DDR_D13
K14 VDDIODDR DDR DDR_D14
K15 VDDIODDR DDR DDR_D15
B8 VDDIODDR DDR DDR_D16
B9 VDDIODDR DDR DDR_D17
C9 VDDIODDR DDR DDR_D18
A9 VDDIODDR DDR DDR_D19
A10 VDDIODDR DDR DDR_D20
D10 VDDIODDR DDR DDR_D21
B11 VDDIODDR DDR DDR_D22
A11 VDDIODDR DDR DDR_D23
J12 VDDIODDR DDR DDR_D24
H10 VDDIODDR DDR DDR_D25
J11 VDDIODDR DDR DDR_D26
K11 VDDIODDR DDR DDR_D27
L13 VDDIODDR DDR DDR_D28
L11 VDDIODDR DDR DDR_D29
L12 VDDIODDR DDR DDR_D30
M17 VDDIODDR DDR DDR_D31
Table 7-2: Pin Description (Continued)
289-pin
BGA Power Rail I/O Type
Primary Alternate PIO peripheral Reset State(Signal, Dir, PU, PD,
HiZ, ST)(1)(2)Signal Dir Signal Dir Func Signal DirIOSet
2018 Microchip Technology Inc. Datasheet DS60001532A-page 37
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F12 VDDIODDR DDR DDR_A0
C17 VDDIODDR DDR DDR_A1
B17 VDDIODDR DDR DDR_A2
B16 VDDIODDR DDR DDR_A3
C16 VDDIODDR DDR DDR_A4
G14 VDDIODDR DDR DDR_A5
F14 VDDIODDR DDR DDR_A6
F11 VDDIODDR DDR DDR_A7
C14 VDDIODDR DDR DDR_A8
D13 VDDIODDR DDR DDR_A9
C15 VDDIODDR DDR DDR_A10
A16 VDDIODDR DDR DDR_A11
A17 VDDIODDR DDR DDR_A12
G11 VDDIODDR DDR DDR_A13
E17 VDDIODDR DDR DDR_CLK
D17 VDDIODDR DDR DDR_CLKN
F16 VDDIODDR DDR DDR_CKE
E16 VDDIODDR DDR DDR_RESETN
G13 VDDIODDR DDR DDR_CS
F15 VDDIODDR DDR DDR_WE
F13 VDDIODDR DDR DDR_RAS
G12 VDDIODDR DDR DDR_CAS
C11 VDDIODDR DDR DDR_DQM0
G15 VDDIODDR DDR DDR_DQM1
C8 VDDIODDR DDR DDR_DQM2
H11 VDDIODDR DDR DDR_DQM3
B13 VDDIODDR DDR DDR_DQS0
J17 VDDIODDR DDR DDR_DQS1
C10 VDDIODDR DDR DDR_DQS2
L17 VDDIODDR DDR DDR_DQS3
B14 VDDIODDR DDR DDR_DQSN0
J16 VDDIODDR DDR DDR_DQSN1
B10 VDDIODDR DDR DDR_DQSN2
L16 VDDIODDR DDR DDR_DQSN3
H12 VDDIODDR DDR DDR_BA0
H13 VDDIODDR DDR DDR_BA1
F17 VDDIODDR DDR DDR_BA2
Table 7-2: Pin Description (Continued)
289-pin
BGA Power Rail I/O Type
Primary Alternate PIO peripheral Reset State(Signal, Dir, PU, PD,
HiZ, ST)(1)(2)Signal Dir Signal Dir Func Signal DirIOSet
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SAMA5D27C AUTO
E13 VDDIODDR DDR DDR_CAL
L15, J15, H15, E15, D15, D12, D11
VDDIODDR power VDDIODDR I
L14, J14, H14, E14, D14, E12, E11
GNDIODDR power GNDIODDR I
H3, N5, N9, K13,
D9, D7
VDDCORE power VDDCORE I
H4, M5, M9, K12,
E9, E7
GNDCORE ground GNDCORE I
E6, F7 VDDIOP0 power VDDIOP0 I
F6, G7 GNDIOP0 ground GNDIOP0 I
R14, N13 VDDIOP1 power VDDIOP1 I
M13, P14 GNDIOP1 ground GNDIOP1 I
F10 VDDIOP2 power VDDIOP2 I
F9 GNDIOP2 ground GNDIOP2 I
P11 VDDSDMMC power VDDSDMMC I
R11 GNDSDMMC ground GNDSDMMC I
F4 VDDISC power VDDISC I
G4 GNDISC ground GNDISC I
M12 VDDFUSE power VDDFUSE I
U4 VDDPLLA power VDDPLLA I
U5 GNDPLLA ground GNDPLLA I
T3 VDDAUDIOPLL power VDDAUDIOPLL I
T5 GNDDPLL ground GNDDPLL I
T4 GNDAUDIOPLL ground GNDAUDIOPLL I
U3 VDDAUDIOPLL CLK_AUDIO
U7 VDDOSC XIN
Table 7-2: Pin Description (Continued)
289-pin
BGA Power Rail I/O Type
Primary Alternate PIO peripheral Reset State(Signal, Dir, PU, PD,
HiZ, ST)(1)(2)Signal Dir Signal Dir Func Signal DirIOSet
2018 Microchip Technology Inc. Datasheet DS60001532A-page 39
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SAMA5D27C AUTO
Note 1: Signal = PIO if GPIO; Dir = Direction; PU = Pull-up; PD = Pull-down; HiZ = High impedance; ST = Schmitt Trigger
U6 VDDOSC XOUT
T7 VDDOSC VDDOSC
T6 GNDOSC power GNDOSC I
P8 VDDUTMII power VDDUTMII I
R9 VDDHSIC power VDDHSIC I
P9 GNDUTMII power GNDUTMII I
T8 VDDUTMII HHSDPA I
R8 VDDUTMII HHSDMA
U8 VDDUTMII HHSDPB
U9 VDDUTMII HHSDMB
T9 VDDHSIC HHSDPDATC
U10 VDDHSIC HHSDMSTRC
P7 VDDUTMIC power VDDUTMIC I
R7 GNDUTMIC power GNDUTMIC I
T10 VDDSDMMC SDCAL
R6 VDDUTMIC VBG
P3 VDDBU TST
U2 VDDBU NRST(3)
T2 VDDBU JTAGSEL
P4 VDDBU WKUP
N4 VDDBU RXD
R1 VDDBU SHDN
R3 VDDBU PIOBU0
N8 VDDBU PIOBU1
R2 VDDBU PIOBU2
R5 VDDBU PIOBU3
R4 VDDBU PIOBU4
P5 VDDBU PIOBU5
P6 VDDBU PIOBU6
M8 VDDBU PIOBU7
N7 VDDBU power VDDBU I
N6 GNDBU ground GNDBU I
P1 VDDBU XIN32
P2 VDDBU XOUT32
T1 VDDBU COMPP I
U1 VDDBU COMPN I
Table 7-2: Pin Description (Continued)
289-pin
BGA Power Rail I/O Type
Primary Alternate PIO peripheral Reset State(Signal, Dir, PU, PD,
HiZ, ST)(1)(2)Signal Dir Signal Dir Func Signal DirIOSet
DS60001532A-page 40 2018 Microchip Technology Inc.
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SAMA5D27C AUTO
2: The reset state of GPIOs is not guaranteed during the powerup phase. During this phase, the GPIOs are in input pullup modeand they take their reset value only after VDDCORE POR reset has been released. If a GPIO must be at level zero at powerup,it is recommended to connect an external pulldown to guarantee this state.
3: For NRST usage, refer to Section 69.5 Reset and Test.
2018 Microchip Technology Inc. Datasheet DS60001532A-page 41
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8. Power Considerations
8.1 Power Supplies
8.2 Powerup ConsiderationsAt powerup, from a supply sequencing perspective, the power supply inputs are categorized into two groups:
Group 1 (core group) contains VDDCORE, VDDUTMIC, VDDHSIC and VDDPLLA. Group 2 (periphery group) contains all other power supply inputs except VDDFUSE.Figure 8-1 shows the recommended powerup sequence. Note that:
VDDBU, when supplied from a battery, is an always-on supply input and is therefore not part of the power supply sequencing. When no backup battery is present in the application, VDDBU is part of Group 2.
VDDFUSE is the only power supply that may be left unpowered during operation. This is possible if and only if the application does not access the Customer Fuse Matrix in Write mode. It is good practice to turn on VDDFUSE only when the Customer Fuse Matrix is accessed in Write mode, and to turn off VDDFUSE otherwise.
VDDIODDR may be nominally supplied at 1.2V when the device is equipped with an LPDDR2 or LPDDR3 memory. In this case, VDDIODDR can be considered as part of Group 1.
Table 8-1: Power Supplies
NameVoltage Range, Nominal
AssociatedGround Powers
VDDCORE 1.10V 1.32V, 1.20V GNDCORE Core, including the processor, the embedded memories and the peripherals
VDDPLLA 1.10V 1.32V, 1.20V GNDPLLA PLLA Cell
VDDUTMIC 1.10V 1.32V, 1.20V GNDUTMII USB device and host UTMI+ core
VDDHSIC 1.10V 1.30V, 1.20V GNDUTMII USB High-Speed Inter-Chip
VDDIODDR
1.70V 1.90V, 1.80V
1.14V 1.30V, 1.20V
1.29V 1.45V, 1.35V
1.43V 1.57V, 1.50V
GNDIODDR
LPDDR1 / DDR2 Interface I/O lines
LPDDR2 / LPDDR3 Interface I/O lines
DDR3L Interface I/O lines
DDR3 Interface I/O lines
VDDIOP0 1.65V 3.60V GNDIOP0 Peripheral I/O lines
VDDIOP1 1.65V 3.60V GNDIOP1 Peripheral I/O lines
VDDIOP2 1.65V 3.60V GNDIOP2 Peripheral I/O lines
VDDISC 1.65V 3.60V GNDISC Image Sensor I/O lines
VDDSDMMC 1.65V 3.60V GNDSDMMC SDMMC I/O lines
VDDUTMII 3.00V 3.60V, 3.30V GNDUTMII USB device and host UTMI+ interface
VDDOSC 1.65V 3.60V GNDOSC Main Oscillator Cell and PLL UTMI. If PLL UTMI or USB is used, the range is restricted to 3.00V3.60V
VDDAUDIOPLL 3.00V 3.60V, 3.30VGNDAUDIOPLL
GNDDPLLAudio PLL
VDDANA 1.65V 3.60V, 3.30V GNDANA VDD Analog
VDDFUSE 2.25V 2.75V, 2.50V GNDFUSEFuse box for programming. It can be tied to ground with a 100 resistor for fuse reading only. It must be powered for fuse programming and to switch to Secure Mode.
VDDBU 1.65V 3.60V GNDBU Slow Clock Oscillator, the internal 64-kHz RC Oscillator and a part of the System Controller
DS60001532A-page 42 2018 Microchip Technology Inc.
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SAMA5D27C AUTO
Figure 8-1: Recommended Powerup Sequence
Note 1: An established supply refers to a power supply established at 90% of its final value.2: Also applies to VDDIODDR when considered as part of Group 1.
Table 8-2: Powerup Timing Specification Symbol Parameter Conditions Min Max Unit
t1 Group 2 to Group 1 delayDelay from the last Group 2 established(1) supply to the first Group1 supply turn-on 0
mst2 Group 1 delay(2) Delay from the first group 1 established supply to the
last Group 1 established supply 1
t3 VDDFUSE to VDDBU delay Delay from VDDBU established to VDDFUSE turn-on 1
tRSTPU Reset delay at powerup From the last established supply to NRST high 1
VDDANA
VDDOSC
VDDUTMII
VDDAUDIOPLL
VDDIOP0
Group 2No specific order and no specific timing required among these channels
VDDIOP1
VDDBU
VDDIODDR
VDDCORE
VDDPLLA
t3
VDDHSIC
t2
tRSTPU
time
NRST
VDDUTMIC
VDDIOP2
VDDISC
VDDSDMMC
VDDFUSE Group 1
t1
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8.3 Powerdown ConsiderationsFigure 8-2 shows the powerdown sequence that starts by asserting the NRST line to 0. Once NRST is asserted, the supply inputs can beimmediately shutdown without any specific timing or order. VDDBU may not be shutdown if the application uses a backup battery on thissupply input. In applications where VDDFUSE is powered, it is mandatory to shutdown VDDFUSE prior to removing any other supply.VDDFUSE can be removed before or after asserting the NRST signal.
Figure 8-2: Recommended Powerdown Sequence
8.4 Power Supply Sequencing at Backup Mode Entry and Exit
8.4.1 VDDBU Power ArchitectureThe backup power switch aims at optimizing the power consumption on VDDBU source by switching the supply of the backup digital part(BUREG memories + 64-kHz RC oscillator) to VDDANA.
When enabled, the backup power source can be automatically switched to VDDANA, which reduces power consumption on VDDBU.Then, VDDBU powers the pads, VDDBU POR and 32-kHz crystal.
The power source (VDDANA or VDDBU) can be selected manually or can be set to work automatically by programming an SFRBU register(refer to SFRBU_PSWBUCTRL in Section 21. Special Function Registers Backup (SFRBU)).
Table 8-3: Powerdown Timing Specification Symbol Parameter Conditions Min Max Unit
tRSTPD Reset delay at powerdown From NRST low to the first supply turn-off 0 ms
t1 VDDFUSE delay at shutdown From VDDFUSE < 1V to the first supply turn-off 0
tRSTPD
VDDAUDIOPLL
VDDIOP0
VDDANA
VDDOSC
time
NRST
VDDIOP1
VDDIOP2
VDDISC
VDDSDMMC
VDDIODDR
VDDUTMII
No specific order and no specific timing required
among the channels
VDDBU
VDDFUSE
VDDCORE
VDDPLLA
VDDHSIC
VDDUTMIC
t1
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8.4.2 Backup Mode EntryFigure 8-3 shows the recommended power down sequence to place the device either in Backup mode or in Backup mode with its DDR inself-refresh. The SHDN signal, output of Shutdown Controller (SHDWC), signals the shutdown request to the power supply. This outputis supplied by VDDBU that is present in Backup mode. Placing the external DDR memory in self-refresh while in Backup mode, requiresto maintain also VDDIODDR. One possible way to signal this additional need to the power supply is to position one of the general purposeI/Os supplied by VDDBU (PIOBUx) in a predefined state.
Figure 8-3: Recommended Backup Mode Entry
Table 8-4: Powerdown Timing Specification Symbol Parameter Conditions Min Max Unit
tRSTPD Reset delay at powerdown From NRST low to the first supply turn-off 0 ms
VDDAUDIOPLL
VDDIOP0
VDDANA
VDDOSC
time
NRST
VDDIOP1
VDDIOP2
VDDISC
VDDSDMMC
VDDFUSE
VDDUTMII
VDDBU
VDDIODDR
VDDCORE
VDDPLLA
VDDHSIC
VDDUTMIC
tRSTPD
SHDN
Shutdown Requestin SHDWC
PIOBUx
No specific order and no specific timing required
among the channels
PIOBUx signals tomaintain or shutdown
VDDIODDR
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8.4.3 Backup Mode Exit (Wakeup)Figure 8-4 shows the recommended powerup sequence to wake up the device from Backup mode. Upon a wakeup event, the ShutdownController toggles its SHDN output back to VDDBU to request the power supply to restart. Except VDDIODDR which may already be pres-ent if the external DDR memory was placed in Self-refresh mode, this powerup sequence is the same as the one of Figure 8-1. In particular,the definitions of Group 1 and Group 2 are the same.
Figure 8-4: Recommended Power Supply Sequencing at Wakeup
Note 1: An established supply refers to a power supply established at 90% of its final value.2: Also applies to VDDIODDR when considered as part of Group 1.
Table 8-5: Powerup Timing Specification Symbol Parameter Conditions Min Max Unit
t1 Group 2 to Group 1 delayDelay from the last Group 2 established(1) supply to the first Group1 supply turn-on 1
mst2 Group 1 delay(2)Delay from the first group 1 established supply to the last Group 1 established supply 1
tRSTPU Reset delay at powerup From the last established supply to NRST high. 1
VDDANA
VDDOSC
VDDUTMII
VDDAUDIOPLL
VDDIOP0
Group 2No specific order and no specific timing required among these channels
VDDIOP1
VDDBU
VDDIODDR
VDDCORE
VDDPLLA
t1
VDDHSIC
t2tRSTPU
time
NRST
VDDUTMIC
Group 1
VDDIOP2
VDDISC
VDDSDMMC
VDDFUSE
SHDN
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9. Memories
Figure 9-1: Memory Mapping
PTC
PTC
Address memory space
Internal memories
0x00000000
EBI Chip Select 0
0x10000000
DDR Chip Select
0x20000000
DDRAESB Chip Select
0x40000000
EBI Chip Select 1
0x60000000
EBI Chip Select 2
0x70000000
EBI Chip Select 3
0x80000000
QSPI0 AESB MEM
0x90000000
QSPI1 AESB MEM
0x98000000
SDMMC0
31;71
0xA0000000
SDMMC1
32;72
0xB0000000
NFC command Register
0xC0000000
QSPI0 MEM
0xD0000000
QSPI1 MEM
0xD8000000
Internal peripherals
0xF0000000
Internal memories
ROM0x00000000
ECC ROM0x00040000
NFC (SRAM)0x00100000
SRAM00x00200000
SRAM10x00220000
UDPHS (RAM)0x00300000
UHPHS (OHCI)0x00400000
UHPHS (EHCI)0x00500000
AXIMX0x00600000
DAP0x00700000
0x00800000
L2CC63
0x00A00000
Undefined (Abort)0x00C00000
0x0FFFFFFF
Internal peripherals
LCDC45
0xF0000000
XDMAC17
0xF0004000
ISC46
0xF0008000
MPDDRC13
0xF000C000
XDMAC06
0xF0010000
PMC+74
0xF0014000
H64MX15
0xF0018000
AESB10
0xF001C000
QSPI052
0xF0020000
QSPI153
0xF0024000
SHA12
0xF0028000
AES9
0xF002C000
SPI033
0xF8000000
SSC043
0xF8004000
GMAC5;66;67
0xF8008000
TC0_CH00xF800C000
35TC0_CH1
+0x40
36
TC0_CH2+0x80
TC1_CH30xF8010000
TC1_CH4+0x40
TC1_CH5+0x80
HSMC17
0xF8014000
PDMIC48
0xF8018000
UART024
0xF801C000
0xF8020000
offset
ID(+ : wired-or)
peripheralblock
UART125
UART226
0xF8024000
TWIHS029
0xF8028000
PWM38
0xF802C000
SFR60
0xF8030000
FLEXCOM019
0xF8034000
FLEXCOM120
0xF8038000
SAIC0;61
0xF803C000
ICM8
0xF8040000
SECURAM51
0xF8044000
SYSCRSTC
0xF8048000
+74SYSC
SHDWC+0x10
SYSCPIT
+0x30
3SYSC
WDT+0x40
4SYSC
SCKC+0x50
SYSCRTC
+0xb0
+74
RXLP76
0xF8049000
ACC75
0xF804A000
RESERVED
0xF804B000
SFC50
0xF804C000
I2SC054
0xF8050000
CAN056;64
0xF8054000
SPI134
0xFC000000
SSC144
0xFC004000
UART327
0xFC008000
UART428
0xFC00C000
0xFC014000FLEXCOM3
22FLEXCOM4
23
0xFC018000
TRNG47
0xFC01C000
AIC49;62
0xFC020000
RESERVED0xFC024000
TWIHS130
0xFC028000
UDPHS42
0xFC02C000
ADC40
0xFC030000
RESERVED0xFC034000
PIOA18
0xFC038000
H32MX14
0xFC03C000
SECUMOD16
0xFC040000
TDES11
0xFC044000
CLASSD59
0xFC048000
I2SC155
0xFC04C000
CAN157;65
0xFC050000
UTMI0xFC054000
RESERVED0xFC058000
SFRBU77
0xFC05C000
0xFC060000
RESERVED0xFC064000
RESERVED0xFC068000
CHIPID78
0xFC069000
RESERVED0xFC06A000
0xFFFFFFFF
58
FLEXCOM221
0xFC010000
+0xE4SYSCWP
SYSC
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9.1 Embedded Memories
9.1.1 Internal SRAMThe SAMA5D27C-CNVAO embeds a total of 128 Kbytes of high-speed SRAM. After reset, and until the Remap command is performed,the SRAM is accessible at address 0x0020 0000. When the AXI Bus Matrix is remapped, the SRAM is also available at address 0x0.
The device features a second 128-Kbyte SRAM that can be allocated either to the L2 cache controller or used as an internal SRAM. Afterreset, this block is connected to the system SRAM, making the two 128-Kbyte RAMs contiguous. The SRAM_SEL bit, located in theSFR_L2CC_HRAMC register, is used to reassign this memory as a L2 cache memory.
9.1.2 Internal ROMThe product embeds one 160-Kbyte secured internal ROM mapped at address 0 after reset. The ROM contains a standard and securebootloader as well as the BCH (Bose, Chaudhuri and Hocquenghem) code tables for NAND Flash ECC correction. The memory area con-taining the secure boot is automatically hidden after the execution of the secure boot while the one containing the code tables for ECCremains visible.
9.1.3 Boot StrategiesFor standard boot strategies, refer to Section 17. Standard Boot Strategies of this datasheet.
For secure boot strategies, refer to the document SAMA5D2x Secure Boot Strategy, document no. 44040 (Non-Disclosure Agreementrequired).
9.2 External MemoryThe SAMA5D27C-CNVAO offers connections to a wide range of external memories or to parallel peripherals.
9.2.1 External Bus InterfaceThe External Bus Interface (EBI) is a 16-bit wide interface working at MCK/2.
The EBI supports:
Static memories 8-bit NAND Flash with 32-bit BCH ECC 16-bit NAND FlashEBI I/Os accept three drive levels (Low, Medium, High) to avoid overshoots and provide the best performances according to the bus loadand external memories voltage.
The drive levels are configured with the DRVSTR field in the PIO Configuration Register (PIO_CFGRx) if the corresponding line is non-secure or the Secure PIO Configuration Register (S_PIO_CFGRx) if the I/O line is secure.
At reset, the selected drive is low. The user must make sure to program the correct drive according to the device load. The I/O embedsserial resistors for impedance matching.
9.2.2 Supported Memories on DDR2/DDR3/LPDDR1/LPDDR2/LPDDR3 Interface 16-bit or 32-bit external interface 512 Mbytes of address space on DDR CS and DDR/AES CS in 32-bit mode 256 Mbytes of address space on DDR CS and DDR/AES CS in 16-bit mode Supports 16-bit or 32-bit 8-bank DDR2, DDR3, LPDDR1, LPDDR2 and LPDDR3 memories Automatic drive level control Multiport Scramblable data path Port 0 of this interface has an embedded automatic AES encryption and decryption mechanism (refer to Section 60. Advanced
Encryption Standard Bridge (AESB)). Writing to or reading from the address 0x40000000 may trigger the encryption and decryption mechanism depending on the AESB on External Memories configuration.
TrustZone: The multiport feature of this interface implies TrustZone configuration constraints. Refer to Section 19.12 TrustZone Extension to AHB and APB for more details.
9.2.3 Supported Memories on Static Memories and NAND Flash InterfacesThe Static Memory Controller is dedicated to interfacing external memory devices:
Asynchronous SRAM-like memories and parallel peripherals
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NAND Flash (MLC and SLC) 8-bit datapathThe Static Memory Controller is able to drive up to four chip select. NCS3 is dedicated to the NAND Flash control.
The HSMC embeds a NAND Flash Controller (NFC). The NFC can handle automatic transfers, sending the commands and address cyclesto the NAND Flash and transferring the contents of the page (for read and write) to the NFC SRAM. It minimizes the processor overhead.
In order to improve overall system performance, the DATA phase of the transfer can be DMA-assisted. The static memory embeds theNAND Flash Error Correcting Code controller with the following features:
Algorithm based on BCH codes Supports also SLC 1-bit (BCH 2-bit), SLC 4-bit (BCH 4-bit) Programmable Error Correcting Capability
- 2-bit, 4-bit, 8-bit and 16-bit errors for 512 bytes/sector (4-Kbyte page)- 24-bit error for 1024 bytes/sector (8-Kbyte page)
Programmable sector size: 512 bytes or 1024 bytes Programmable number of sectors per page: 1, 2, 4 or 8 blocks of data per page Programmable spare area size Supports spare area ECC protection Supports 8-Kbyte page size using 1024 bytes/sector and 4-Kbyte page size using 512 bytes/sector Error detection is interrupt-driven Provides hardware acceleration for error location Finds roots of error-locator polynomial Programmable number of roots
9.2.4 DDR and SDMMC I/Os Calibration
9.2.4.1 DDR I/O CalibrationThe DDR2/DDR3/LPDDR1/LPDDR2/LPDDR3/DDR3L I/Os embed an automatic impedance matching control to avoid overshoots andreach the best performance levels depending on the bus load and external memories. A serial termination connection scheme, where thedriver has an output impedance matched to the characteristic impedance of the line, is used to improve signal quality and reduce EMI.
One specific analog input, DDR_CAL, is used to calibrate all DDR / IOs.
The MPDDRC supports the ZQ calibration procedure used to calibrate the DDR I/O drive strength and the commands to setup the externalDDR device drive strength (refer to Section 37. Multiport DDR-SDRAM Controller (MPDDRC)). The calibration cell supports all the mem-ory types listed above.
Figure 9-2: DDR Calibration Cell
The calibration cell provides an input pin, DDR_CAL, loaded with one of the following resistor RZQ values:
Calibration Cell
DDR I/O
DDR I/O
RZQ
CZQ
PCB Trace
PCB Trace
DDRMemory
CAL_CTRL
cal_nmoscal_pmos
drive
DDR_CAL
MPDDRCCALCODEN/CALCODEP
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- 24 K for LPDDR2/LPDDR3- 23 K for DDR3L- 22 K for DDR3- 21 K for DDR2/LPDDR1
The typical value for CZQ is 22 pF.
LPDDR2 Power Fail ManagementThe DDR controller (MPDDRC) is used to manage the LPDDR memory when an uncontrolled power off occurs.
The DDR power rail must be monitored externally and generate an interrupt when a power fail condition is triggered. The interrupt handlermust apply the sequence defined in the MPDDRC Low-power register (MPDDRC_LPR) by setting bit LPDDR2_PWOFF (LPDDR2 PowerOff bit).
9.2.4.2 SDMMC I/O CalibrationThe device also embeds an SDMMC I/O calibration cell. The purpose of this block is to provide to e.MMC/SD I/Os an output impedancereference to limit the impact of process, voltage and temperature on the drivers output impedance. The impedance control is required athigh frequency in order to improve signal quality.
The control and procedure to setup the SDMMC calibration cell is described in Section 52. Secure Digital MultiMedia Card Controller(SDMMC).
Figure 9-3: SDMMC I/O Calibration Cell
The calibration cell provides an input pin SDCAL loaded with a 20 K resistor for 1.8V memories and a 16.9 K resistor for 3.3V memories.
According to the e.MMC specification, the output impedance calibration is mandatory for HS200 mode (1.8V) when it is not for other modes(3.3V).
In addition, according to the SD specification, the output impedance calibration is mandatory for 1.8V signaling when it is not for 3.3Vsignaling.
Thus, the calibration cell design is oriented to get the highest accuracy under 1.8V.
In case of interfacing which would need to operate under both 1.8V and 3.3V, external devices RZQ and CZQ must get values related tothe 1.8V mode. The typical value for CZQ is 22 pF.
Calibration Cell
SDMMC I/O
SDMMC I/O
RZQ
CZQ
PCB Trace
PCB Trace
SD/MMCMemory
CAL_CTRL
cal_nmoscal_pmos
drive
SDCAL
SDMMC
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10. Event SystemThe events generated by peripherals are designed to be directly routed to peripherals managing/using these events without processorintervention. Peripherals receiving events contain logic by which to select the one required.
10.1 Real-time Event List Timers, PWM, IO peripherals generate event triggers which are directly routed to event managers such as ADC, for example, to start
measurement/conversion without processor intervention. ADC is connected to nine trigger inputs defined as two groups:
- One group of eight elements for Timer Counter (TC0 to TC4), ADTRIG and PMW0 event0, PWM0 event1- One group of one element for low-rate trigger, RTC
UART, USART, SPI, TWI, PWM, CLASSD, AES, SHA, ADC, PIO, TIMER (Capture mode) generate event triggers directly connected to DMA controllers (XDMAC) for data transfer without processor intervention.
PWM safety events (faults) are in combinational form and directly routed from event generators (ADC, ACC, PMC, TIMER) to the PWM module.
PWM receives external triggers to provide PFC, DC/DC functions. PWM output comparators generate events directly connected to TIMER. PMC safety event (clock failure detection) can be programmed to switch the MCK on a reliable main RC internal clock without pro-
cessor intervention.
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10.2 Real-time Event Mapping
Note 1: Refer to Section 34.17 Main Crystal Oscillator Failure Detection.2: Refer to Section 57.5.4 Fault Inputs and Section 57.6.2.7 Fault Protection.3: Refer to Section 65.5.5 Fault Output.4: Refer to Section 55.6.18 Fault Mode.5: Refer to Section 65.7.25 ADC Trigger Register.6: Refer to Section 27.5.8 Waveform Generation.7: Refer to Section 57.6.3 PWM Comparison Units and Section 57.6.4 PWM Event Lines.8: Refer to Section 55.6.14 Synchronization with PWM.9: Refer to Section 57.6.2.2 Comparator.
Table 10-1: Real-time Event Mapping ListFunction Application Description Event Source Event Destination
Safety
General-purposeAutomatic switch to reliable main RC oscillator in case of main crystal clock failure(1)
Power Management Controller (PMC)
PMC
General-purpose, motor control, power factor
correction (PFC)
Puts the PWM outputs in Safe mode (main crystal clock failure detection)(1)(2)
PWM
Motor control, PFCPuts the PWM outputs in Safe mode (overspeed, overcurrent detection, etc.)(2)(3)
ADC
Motor control Puts the PWM outputs in Safe mode (overspeed detection through TIMER quadrature decoder)(2)(4)
Timer Counter Block(TC 0, 1, 2)
Timer Counter Block(TC 3, 4, 5)
General-purpose Puts the PWM outputs in Safe mode (general-purpose fault inputs)(2) 2 IOs (PWM_Flx)
Measurement trigger
General-purpose Programmable delay in PWM(7)PWM Event Line 0
ADC
PWM Event Line 1
General-purpose Trigger source selection in ADC(5)
IO (ADC_ADTRG)
TC Output 0
TC Output 1
TC Output 2
TC Output 3
TC Output 4 RTCOUT0
General-purpose Low-speed measurement(6) RTC RTCOUT1
GTSUCOMP synchronous
clock generation
trigger
Audio Trigger source selection in TC GMAC GTSUCOMP Line TC5
Delay measurement Motor control
Delay measurement between PWM outputs and TC inputs externally connected to power transistor bridge driver.(8)(9)
PWM Compare Line 0 TC Input (A/B) 0
PWM Compare Line 1 TC Input (A/B) 1
PWM Compare Line 2 TC Input (A/B) 2
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11. System ControllerThe system controller is a set of peripherals handling key elements of the system, such as power, resets, clocks, time, interrupts, watch-dog, etc.
The system controllers peripherals are all mapped between addresses 0xF8049000 and 0xF8048000.
Figure 11-1 shows the system controller block diagram.
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Figure 11-1: System Controller Block Diagram
NRST
SLCK
Advanced Interrupt Controller
Periodic Interval Timer
Reset Controller
periph_nreset
WatchdogTimer
wdt_fault
Power Management
Controller
XIN
XOUTMAINCK
PLLACK
pit_irqMCK
proc_nreset
wdt_irq
periph_irq[70, 69, 68, 18]periph_nreset
periph_clk[id]
PCKGCLK
MCK
pmc_irq
nirq
periph_clk[id]
pck[02]
inout
enable
SLCK
irq
fiqperiph_irq[id]
nonsecure_peripheral_irq[]
periph_nreset
periph_clk[id]
jtag_nreset
proc_nreset
periph_nreset
int
pit_irq
pmc_irq
wdt_irq
SLCK
Boundary Scan TAP Controller
jtag_nreset
debug
PCK
debugidle
debug
Bus Matrix
MCK
periph_nreset
proc_nreset
periph_nreset
idle
ShutdownController
SLCK
backup_nreset
SHDNWKUP
backup_nreset
XIN32
XOUT32
VDDBU Powered
ntrst
VDDCOREPOR
824 MHzMain
Oscillator
PLLA
VDDBUPOR
32.768 kHzCrystal
Oscillator
UPLL
por_ntrst
UPLLCK
USB High SpeedDevice Port
UPLLCK
periph_nreset
per