sam d21el / sam d21glww1.microchip.com/downloads/en/devicedoc/40001883a.pdf · 32-bit arm-based...

32-bit ARM-BasedMicrocontrollers

SAM D21EL / SAM D21GL

Introduction

The SAM D21L is a series of low-power microcontrollers using the 32-bit ARM® Cortex®-M0+ processor,and ranging from 32- to 48-pins with up to 64KB Flash and 8KB of SRAM. The SAM D21L devicesoperate at a maximum frequency of 48MHz and reach 2.46 CoreMark®/MHz. They are designed forsimple and intuitive migration with identical peripheral modules, hex compatible code, identical linearaddress map and pin compatible migration paths between all devices in the product series. All devicesinclude intelligent and flexible peripherals, Event System for inter-peripheral signaling, and support forcapacitive touch button, slider and wheel user interfaces.

Features

• Processor– ARM Cortex-M0+ CPU running at up to 48MHz

• Single-cycle hardware multiplier• Micro Trace Buffer (MTB)

• Memories– 32/64KB in-system self-programmable Flash– 4/8KB SRAM Memory

• System– Power-on reset (POR) and brown-out detection (BOD)– Internal and external clock options with 48MHz Digital Frequency Locked Loop (DFLL48M)

and 48MHz to 96MHz Fractional Digital Phase Locked Loop (FDPLL96M)– External Interrupt Controller (EIC)– 16 external interrupts– One non-maskable interrupt– Two-pin Serial Wire Debug (SWD) programming, test and debugging interface

• Low Power– Idle and standby sleep modes– SleepWalking peripherals

• Peripherals– 12-channel Direct Memory Access Controller (DMAC)– 12-channel Event System– Up to five 16-bit Timer/Counters (TC), configurable as either:

• One 16-bit TC with two compare/capture channels• One 8-bit TC with two compare/capture channels• One 32-bit TC with two compare/capture channels, by using two TCs

– Three 24-bit Timer/Counters for Control (TCC), with extended functions:

© 2017 Microchip Technology Inc. Datasheet Complete 40001883A-page 1

• Up to four compare channels with optional complementary output• Generation of synchronized pulse width modulation (PWM) pattern across port pins• Deterministic fault protection, fast decay and configurable dead-time between

complementary output• Dithering that increase resolution with up to 5 bit and reduce quantization error

– 32-bit Real Time Counter (RTC) with clock/calendar function– Watchdog Timer (WDT)– CRC-32 generator– Up to six Serial Communication Interfaces (SERCOM), each configurable to operate as either:

• USART with full-duplex and single-wire half-duplex configuration• I2C up to 3.4MHz• SPI• LIN slave

– One 12-bit, 350ksps Analog-to-Digital Converter (ADC) with up to 18 channels• Differential and single-ended input• 1/2x to 16x programmable gain stage• Automatic offset and gain error compensation• Oversampling and decimation in hardware to support 13-, 14-, 15- or 16-bit resolution

– 10-bit, 350ksps Digital-to-Analog Converter (DAC)– Four Analog Comparators (AC) with window compare function

• I/O– Up to 38 programmable I/O pins

• Packages– 48-pin TQFP, QFN– 32-pin QFN

• Operating Voltage– 1.62V – 3.63V

32-bit ARM-Based Microcontrollers


Table of Contents

Introduction......................................................................................................................1

Features.......................................................................................................................... 1

1. Description...............................................................................................................11

2. Configuration Summary...........................................................................................12

3. Ordering Information................................................................................................133.1. SAM D21ExL..............................................................................................................................133.2. SAM D21GxL............................................................................................................................. 133.3. Device Identification................................................................................................................... 13

4. Block Diagram......................................................................................................... 15

5. Pinout...................................................................................................................... 175.1. SAM D21GxL............................................................................................................................. 175.2. SAM D21ExL..............................................................................................................................18

6. Signal Descriptions List........................................................................................... 19

7. I/O Multiplexing and Considerations........................................................................217.1. Multiplexed Signals.................................................................................................................... 217.2. Other Functions..........................................................................................................................22

8. Power Supply and Start-Up Considerations............................................................ 258.1. Power Domain Overview............................................................................................................258.2. Power Supply Considerations.................................................................................................... 258.3. Power-Up................................................................................................................................... 278.4. Power-On Reset and Brown-Out Detector.................................................................................27

9. Product Mapping..................................................................................................... 29

10. Memories.................................................................................................................3010.1. Embedded Memories................................................................................................................. 3010.2. Physical Memory Map................................................................................................................3010.3. NVM Calibration and Auxiliary Space........................................................................................ 31

11. Processor And Architecture.....................................................................................3411.1. Cortex M0+ Processor............................................................................................................... 3411.2. Nested Vector Interrupt Controller..............................................................................................3511.3. Micro Trace Buffer......................................................................................................................3711.4. High-Speed Bus System............................................................................................................ 3811.5. AHB-APB Bridge........................................................................................................................ 4011.6. PAC - Peripheral Access Controller........................................................................................... 41


12. Peripherals Configuration Summary........................................................................52

13. DSU - Device Service Unit...................................................................................... 5413.1. Overview.................................................................................................................................... 5413.2. Features..................................................................................................................................... 5413.3. Block Diagram............................................................................................................................5413.4. Signal Description...................................................................................................................... 5413.5. Product Dependencies...............................................................................................................5513.6. Debug Operation........................................................................................................................5613.7. Chip Erase..................................................................................................................................5713.8. Programming..............................................................................................................................5813.9. Intellectual Property Protection.................................................................................................. 5813.10. Device Identification...................................................................................................................6013.11. Functional Description................................................................................................................6113.12. Register Summary..................................................................................................................... 6613.13. Register Description...................................................................................................................68

14. Clock System...........................................................................................................8414.1. Clock Distribution....................................................................................................................... 8414.2. Synchronous and Asynchronous Clocks....................................................................................8514.3. Register Synchronization........................................................................................................... 8514.4. Enabling a Peripheral.................................................................................................................9014.5. Disabling a Peripheral................................................................................................................ 9014.6. On-demand, Clock Requests..................................................................................................... 9014.7. Power Consumption vs. Speed..................................................................................................9114.8. Clocks after Reset......................................................................................................................91

15. GCLK - Generic Clock Controller............................................................................ 9215.1. Overview.................................................................................................................................... 9215.2. Features..................................................................................................................................... 9215.3. Block Diagram............................................................................................................................9215.4. Signal Description...................................................................................................................... 9315.5. Product Dependencies...............................................................................................................9315.6. Functional Description................................................................................................................9415.7. Register Summary......................................................................................................................9915.8. Register Description.................................................................................................................100

16. PM – Power Manager............................................................................................ 11116.1. Overview...................................................................................................................................11116.2. Features....................................................................................................................................11116.3. Block Diagram.......................................................................................................................... 11216.4. Signal Description.....................................................................................................................11216.5. Product Dependencies............................................................................................................. 11216.6. Functional Description.............................................................................................................. 11416.7. Register Summary....................................................................................................................12116.8. Register Description.................................................................................................................121

17. SYSCTRL – System Controller............................................................................. 134



17.1. Overview.................................................................................................................................. 13417.2. Features................................................................................................................................... 13417.3. Block Diagram..........................................................................................................................13617.4. Signal Description.................................................................................................................... 13617.5. Product Dependencies.............................................................................................................13617.6. Functional Description..............................................................................................................13817.7. Register Summary....................................................................................................................15317.8. Register Description.................................................................................................................154

18. WDT – Watchdog Timer........................................................................................ 18418.1. Overview.................................................................................................................................. 18418.2. Features................................................................................................................................... 18418.3. Block Diagram..........................................................................................................................18518.4. Signal Description.................................................................................................................... 18518.5. Product Dependencies.............................................................................................................18518.6. Functional Description..............................................................................................................18618.7. Register Summary....................................................................................................................19118.8. Register Description.................................................................................................................191

19. RTC – Real-Time Counter.....................................................................................19719.1. Overview.................................................................................................................................. 19719.2. Features................................................................................................................................... 19719.3. Block Diagram..........................................................................................................................19719.4. Signal Description.................................................................................................................... 19819.5. Product Dependencies.............................................................................................................19819.6. Functional Description..............................................................................................................20019.7. Register Summary....................................................................................................................20519.8. Register Description.................................................................................................................207

20. DMAC – Direct Memory Access Controller........................................................... 23020.1. Overview.................................................................................................................................. 23020.2. Features................................................................................................................................... 23020.3. Block Diagram..........................................................................................................................23220.4. Signal Description.................................................................................................................... 23220.5. Product Dependencies.............................................................................................................23220.6. Functional Description..............................................................................................................23320.7. Register Summary....................................................................................................................25320.8. Register Description.................................................................................................................25420.9. Register Summary - SRAM......................................................................................................27720.10. Register Description - SRAM................................................................................................... 277

21. EIC – External Interrupt Controller........................................................................ 28321.1. Overview.................................................................................................................................. 28321.2. Features................................................................................................................................... 28321.3. Block Diagram..........................................................................................................................28321.4. Signal Description.................................................................................................................... 28421.5. Product Dependencies.............................................................................................................28421.6. Functional Description..............................................................................................................28521.7. Register Summary....................................................................................................................289



21.8. Register Description.................................................................................................................290

22. NVMCTRL – Non-Volatile Memory Controller....................................................... 29822.1. Overview.................................................................................................................................. 29822.2. Features................................................................................................................................... 29822.3. Block Diagram..........................................................................................................................29822.4. Signal Description.................................................................................................................... 29922.5. Product Dependencies.............................................................................................................29922.6. Functional Description..............................................................................................................30022.7. Register Summary....................................................................................................................30722.8. Register Description.................................................................................................................307

23. PORT - I/O Pin Controller......................................................................................31723.1. Overview.................................................................................................................................. 31723.2. Features................................................................................................................................... 31723.3. Block Diagram..........................................................................................................................31823.4. Signal Description.................................................................................................................... 31823.5. Product Dependencies.............................................................................................................31823.6. Functional Description..............................................................................................................32023.7. Register Summary....................................................................................................................32623.8. Register Description.................................................................................................................328

24. EVSYS – Event System........................................................................................ 34124.1. Overview.................................................................................................................................. 34124.2. Features................................................................................................................................... 34124.3. Block Diagram..........................................................................................................................34124.4. Signal Description.................................................................................................................... 34224.5. Product Dependencies.............................................................................................................34224.6. Functional Description..............................................................................................................34324.7. Register Summary....................................................................................................................34824.8. Register Description.................................................................................................................348

25. SERCOM – Serial Communication Interface.........................................................36025.1. Overview.................................................................................................................................. 36025.2. Features................................................................................................................................... 36025.3. Block Diagram..........................................................................................................................36125.4. Signal Description.................................................................................................................... 36125.5. Product Dependencies.............................................................................................................36125.6. Functional Description..............................................................................................................363

26. SERCOM USART – SERCOM Universal Synchronous and Asynchronous Receiverand Transmitter......................................................................................................36926.1. Overview.................................................................................................................................. 36926.2. USART Features...................................................................................................................... 36926.3. Block Diagram..........................................................................................................................37026.4. Signal Description.................................................................................................................... 37026.5. Product Dependencies.............................................................................................................37026.6. Functional Description..............................................................................................................372



26.7. Register Summary....................................................................................................................38426.8. Register Description.................................................................................................................384

27. SERCOM SPI – SERCOM Serial Peripheral Interface..........................................40127.1. Overview.................................................................................................................................. 40127.2. Features................................................................................................................................... 40127.3. Block Diagram..........................................................................................................................40227.4. Signal Description.................................................................................................................... 40227.5. Product Dependencies.............................................................................................................40227.6. Functional Description..............................................................................................................40427.7. Register Summary....................................................................................................................41327.8. Register Description.................................................................................................................414

28. SERCOM I2C – SERCOM Inter-Integrated Circuit................................................ 42728.1. Overview.................................................................................................................................. 42728.2. Features................................................................................................................................... 42728.3. Block Diagram..........................................................................................................................42828.4. Signal Description.................................................................................................................... 42828.5. Product Dependencies.............................................................................................................42828.6. Functional Description..............................................................................................................43028.7. Register Summary - I2C Slave.................................................................................................44928.8. Register Description - I2C Slave...............................................................................................44928.9. Register Summary - I2C Master...............................................................................................46328.10. Register Description - I2C Master............................................................................................ 464

29. TC – Timer/Counter...............................................................................................47929.1. Overview.................................................................................................................................. 47929.2. Features................................................................................................................................... 47929.3. Block Diagram..........................................................................................................................48029.4. Signal Description.................................................................................................................... 48029.5. Product Dependencies.............................................................................................................48129.6. Functional Description..............................................................................................................48229.7. Register Summary....................................................................................................................49429.8. Register Description.................................................................................................................496

30. TCC – Timer/Counter for Control Applications...................................................... 51130.1. Overview...................................................................................................................................51130.2. Features................................................................................................................................... 51130.3. Block Diagram..........................................................................................................................51230.4. Signal Description.................................................................................................................... 51230.5. Product Dependencies.............................................................................................................51230.6. Functional Description..............................................................................................................51430.7. Register Summary....................................................................................................................54530.8. Register Description.................................................................................................................547

31. ADC – Analog-to-Digital Converter........................................................................58231.1. Overview.................................................................................................................................. 58231.2. Features................................................................................................................................... 58231.3. Block Diagram..........................................................................................................................583



31.4. Signal Description.................................................................................................................... 58331.5. Product Dependencies.............................................................................................................58431.6. Functional Description..............................................................................................................58531.7. Register Summary....................................................................................................................59431.8. Register Description.................................................................................................................595

32. AC – Analog Comparators.....................................................................................61232.1. Overview.................................................................................................................................. 61232.2. Features................................................................................................................................... 61232.3. Block Diagram..........................................................................................................................61332.4. Signal Description.................................................................................................................... 61432.5. Product Dependencies.............................................................................................................61432.6. Functional Description..............................................................................................................61632.7. Register Summary....................................................................................................................62632.8. Register Description.................................................................................................................626

33. DAC – Digital-to-Analog Converter........................................................................63833.1. Overview.................................................................................................................................. 63833.2. Features................................................................................................................................... 63833.3. Block Diagram..........................................................................................................................63833.4. Signal Description.................................................................................................................... 63833.5. Product Dependencies.............................................................................................................63833.6. Functional Description..............................................................................................................64033.7. Register Summary....................................................................................................................64433.8. Register Description.................................................................................................................644

34. Electrical Characteristics....................................................................................... 65134.1. Disclaimer.................................................................................................................................65134.2. Absolute Maximum Ratings......................................................................................................65134.3. General Operating Ratings.......................................................................................................65134.4. Supply Characteristics..............................................................................................................65234.5. Maximum Clock Frequencies...................................................................................................65334.6. Power Consumption.................................................................................................................65434.7. Peripheral Power Consumption................................................................................................65834.8. I/O Pin Characteristics..............................................................................................................66034.9. Injection Current.......................................................................................................................66234.10. Analog Characteristics............................................................................................................. 66234.11. NVM Characteristics.................................................................................................................67434.12. Oscillators Characteristics........................................................................................................67534.13. Timing Characteristics..............................................................................................................680

35. Packaging Information...........................................................................................68635.1. Thermal Considerations........................................................................................................... 68635.2. Package Drawings................................................................................................................... 68735.3. Soldering Profile.......................................................................................................................691

36. Schematic Checklist.............................................................................................. 69236.1. Introduction...............................................................................................................................69236.2. Power Supply........................................................................................................................... 692



36.3. External Analog Reference Connections................................................................................. 69336.4. External Reset Circuit...............................................................................................................69536.5. Clocks and Crystal Oscillators..................................................................................................69636.6. Unused or Unconnected Pins...................................................................................................69636.7. Programming and Debug Ports................................................................................................697

37. Errata.....................................................................................................................70137.1. Die Revision E..........................................................................................................................70137.2. Die Revision F..........................................................................................................................705

38. Conventions...........................................................................................................70938.1. Numerical Notation...................................................................................................................70938.2. Memory Size and Type.............................................................................................................70938.3. Frequency and Time.................................................................................................................70938.4. Registers and Bits.................................................................................................................... 710

39. Acronyms and Abbreviations................................................................................. 711

40. Datasheet Revision History................................................................................... 71440.1. Rev.A – 01/2017.......................................................................................................................71440.2. Rev. O – 12/2016..................................................................................................................... 71440.3. Rev.N – 04/2016.......................................................................................................................71640.4. Rev.M – 01/2016...................................................................................................................... 71640.5. Rev.L – 12/2015....................................................................................................................... 71640.6. Rev.K – 11/2015....................................................................................................................... 71640.7. Rev.J – 10/2015....................................................................................................................... 71740.8. Rev. I – 09/2015....................................................................................................................... 71740.9. Rev. H – 08/2015......................................................................................................................71740.10. Rev. G – 03/2015..................................................................................................................... 71840.11. Rev. F – 03/2015...................................................................................................................... 71840.12. Rev. E – 02/2015......................................................................................................................71840.13. Rev. D – 01/2015..................................................................................................................... 71940.14. Rev. C – 12/2014..................................................................................................................... 71940.15. Rev. B – 10/2014......................................................................................................................71940.16. Rev. A – 07/2014......................................................................................................................719

41. Appendix A. Electrical Characteristics at 125°C....................................................72041.1. Disclaimer.................................................................................................................................72041.2. Absolute Maximum Ratings......................................................................................................72041.3. General Operating Ratings.......................................................................................................72041.4. Maximum Clock Frequencies...................................................................................................72141.5. Power Consumption.................................................................................................................72241.6. Analog Characteristics............................................................................................................. 72541.7. NVM Characteristics.................................................................................................................73241.8. Oscillators Characteristics........................................................................................................73341.9. Timing Characteristics..............................................................................................................738

42. Appendix B. Electrical Characteristics at 105°C....................................................73942.1. Disclaimer.................................................................................................................................739



42.2. Absolute Maximum Ratings......................................................................................................73942.3. General Operating Ratings.......................................................................................................73942.4. Maximum Clock Frequencies...................................................................................................74042.5. Power Consumption.................................................................................................................74142.6. Analog Characteristics............................................................................................................. 74442.7. NVM Characteristics.................................................................................................................75242.8. Oscillators Characteristics........................................................................................................75342.9. Timing Characteristics..............................................................................................................758

The Microchip Web Site.............................................................................................. 759

Customer Change Notification Service........................................................................759

Customer Support....................................................................................................... 759

Product Identification System......................................................................................759

Microchip Devices Code Protection Feature............................................................... 760

Legal Notice.................................................................................................................760

Trademarks................................................................................................................. 761

Quality Management System Certified by DNV...........................................................761

Worldwide Sales and Service......................................................................................762



1. DescriptionThe SAM D21L is a series of low-power microcontrollers using the 32-bit ARM® Cortex®-M0+ processor,and offered in 32- and 48-pin packages with up to 64KB Flash and 8KB of SRAM. The SAM D21Loperate at a maximum frequency of 48MHz and reach 2.46 CoreMark/MHz. They are designed for simpleand intuitive migration with identical peripheral modules, hex compatible code, identical linear addressmap and pin compatible migration paths between all devices in the product series. All devices includeintelligent and flexible peripherals, Event System for inter-peripheral signaling, and support for capacitivetouch button, slider and wheel user interfaces.

The SAM D21L microcontrollers provide the following features: In-system programmable Flash, twelve-channel direct memory access (DMA) controller, 12 channel Event System, programmable interruptcontroller, up to 52 programmable I/O pins, 32-bit real-time clock and calendar, up to five 16-bit Timer/Counters (TC) and three 24-bit Timer/Counters for Control (TCC), where each TC can be configured toperform frequency and waveform generation, accurate program execution timing or input capture withtime and frequency measurement of digital signals. The TCs can operate in 8- or 16-bit mode, selectedTCs can be cascaded to form a 32-bit TC, and three timer/counters have extended functions optimizedfor motor, lighting and other control applications. The series provide up to six Serial CommunicationModules (SERCOM) that each can be configured to act as an USART, UART, SPI, I2C up to 3.4MHz,SMBus, PMBus, and LIN slave; up to eighteen-channel 350ksps 12-bit ADC with programmable gain andoptional oversampling and decimation supporting up to 16-bit resolution, one 10-bit 350ksps DAC, fouranalog comparators with window mode; programmable Watchdog Timer, brown-out detector and power-on reset and two-pin Serial Wire Debug (SWD) program and debug interface.

All devices have accurate and low-power external and internal oscillators. All oscillators can be used as asource for the system clock. Different clock domains can be independently configured to run at differentfrequencies, enabling power saving by running each peripheral at its optimal clock frequency, and thusmaintaining a high CPU frequency while reducing power consumption.

The SAM D21L microcontrollers have two software-selectable sleep modes, idle and standby. In idlemode the CPU is stopped while all other functions can be kept running. In standby all clocks andfunctions are stopped expect those selected to continue running. The device supports SleepWalking. Thisfeature allows the peripheral to wake up from sleep based on predefined conditions, and thus allows theCPU to wake up only when needed, e.g. when a threshold is crossed or a result is ready. The EventSystem supports synchronous and asynchronous events, allowing peripherals to receive, react to andsend events even in standby mode.

The Flash program memory can be reprogrammed in-system through the SWD interface. The sameinterface can be used for non-intrusive on-chip debug of application code. A boot loader running in thedevice can use any communication interface to download and upgrade the application program in theFlash memory.

The SAM D21L microcontrollers are supported with a full suite of program and system development tools,including C compilers, macro assemblers, program debugger/simulators, programmers and evaluationkits.



2. Configuration SummarySAM D21G16L SAM D21ExL

Pins 48 32

General Purpose I/O-pins (GPIOs) 38 26

Flash 64KB 64/32KB

SRAM 8KB 8/4KB

Timer Counter (TC) instances 5 3

Waveform output channels per TC instance 2 2

Timer Counter for Control (TCC) instances 3 3

Waveform output channels per TCC 8/4/2 6/4/2

DMA channels 12 12

Serial Communication Interface (SERCOM)instances

6 4

Analog-to-Digital Converter (ADC) channels 18 14

Analog Comparators (AC) 4 4

Digital-to-Analog Converter (DAC) channels 1 1

Real-Time Counter (RTC) Yes Yes

RTC alarms 1 1

RTC compare values One 32-bit value or

two 16-bit values

One 32-bit value or

two 16-bit values

External Interrupt lines 16 16

Maximum CPU frequency 48MHz

Packages QFN QFN

TQFP

Oscillators 0.4-32MHz crystal oscillator (XOSC)

32.768kHz internal oscillator (OSC32K)

32KHz ultra-low-power internal oscillator (OSCULP32K)

8MHz high-accuracy internal oscillator (OSC8M)

48MHz Digital Frequency Locked Loop (DFLL48M)

96MHz Fractional Digital Phased Locked Loop (FDPLL96M)

Event System channels 12 12

SW Debug Interface Yes Yes

Watchdog Timer (WDT) Yes Yes



3. Ordering Information SAMD 21 E 15 L - M F T

Product FamilySAMD = General Purpose Microcontroller

21 = Cortex M0 + CPU, Basic Feature Set

E = 32 PinsG = 48 Pins

No character = Tray (Default) T = Tape and Reel

U = -40 - 85OC Matte Sn PlatingN = -40 - 105oC Matte Sn PlatingF = -40 - 125OC Matte Sn Plating

A = TQFPM = QFN

+ DMA + Analog/PWM Optimized

Product Series

Flash Memory Density

Device VariantA = Default VariantL = Pinout optimized for analog and PWM

Pin Count

Package Carrier

Package Grade

16 = 64KB15 = 32KB

Package Type

3.1 SAM D21ExLOrdering Code FLASH (bytes) SRAM (bytes) Temperature Range Package Carrier Type

ATSAMD21E15L-MNT 32K 4K 105°C QFN32 Tape & Reel

ATSAMD21E15L-MFT 32K 4K 125°C QFN32 Tape & Reel

ATSAMD21E15L-AFT 32K 4K 125°C TQFP32 Tape & Reel

ATSAMD21E16L-MNT 64K 8K 105°C QFN32 Tape & Reel

ATSAMD21E16L-MFT 64K 8K 125°C QFN32 Tape & Reel

ATSAMD21E16L-AFT 64K 8K 125°C TQFP32 Tape & Reel

3.2 SAM D21GxLOrdering Code FLASH (bytes) SRAM (bytes) Temperature Range Package Carrier Type

ATSAMD21G16L-MUT 64K 8K 85°C QFN48 Tape & Reel

ATSAMD21G16L-MNT 64K 8K 105°C QFN48 Tape & Reel

3.3 Device IdentificationThe DSU - Device Service Unit peripheral provides the Device Selection bits in the Device Identificationregister (DID.DEVSEL) in order to identify the device by software. The SAM D21L variants have a resetvalue of DID=0x1001drxx, with the LSB identifying the die number ('d'), the die revision ('r') and thedevice selection ('xx').



Table 3-1. SAM D21L Device Identification Values

Device Variant DID.DEVSEL Device ID (DID)

Reserved 0x00 - 0x61

SAMD21E16L 0x62 0x1001143E (Die revision E)

0x1001153E (Die revision F)

SAMD21E15L 0x63 0x1001143F (Die revision E)

0x1001153F (Die revision F)

Reserved 0x64 - 0x86

SAMD21G16L 0x87 0x10011457 (Die revision E)

0x10011557 (Die revision F)

Reserved 0x88 - 0xFF

Note: The device variant (last letter of the ordering number) is independent of the die revision(DSU.DID.REVISION): The device variant denotes functional differences, whereas the die revision marksevolution of the die. The device variant denotes functional differences, whereas the die revision marksevolution of the die.



4. Block Diagram

6 x SERCOM

8 x Timer Counter

REAL TIME COUNTER

AHB-APB BRIDGE C

M

MHIGH SPEED BUS MATRIX

POR

T

PO

RT

WATCHDOG TIMER

SERIAL WIRESWDIO

S

CORTEX-M0+ PROCESSOR Fmax 48 MHz

SWCLK

DEVICE SERVICE

UNIT

AHB-APB BRIDGE A

18-CHANNEL 12-bit ADC 350KSPS

AIN[19..0]

VREFA

AIN[3..0]

S

SRAM CONTROLLER

32/16/8/4KB RAM

M

RESET CONTROLLER

SLEEP CONTROLLER

CLOCK CONTROLLER

POWER MANAGER

RESETN

5 x TIMER / COUNTER

EVE

NT

SYST

EM

S

6 x SERCOM

4 x ANALOG COMPARATORS

SYSTEM CONTROLLER

XOUT XIN

OSCULP32K

OSC32K

OSC8M

DFLL48M

BOD33

XOSC

VREF

PERIPHERAL ACCESS CONTROLLER

AHB-APB BRIDGE B

VREFA

VOUT

10-bit DAC

EXTERNAL INTERRUPT CONTROLLER



EXTINT[15..0] NMI

GCLK_IO[7..0]

S

PAD0

WO1

PAD1PAD2PAD3

WO0

VREFB

256/128/64/32KB NVM

NVM CONTROLLER

Cache

S

DMA

3 x TIMER / COUNTERFOR CONTROL

WOn

IOBUS

FDPLL96MDMA

DMA

DMA

DMA

DMA

MIC

RO

TRAC

E BU

FFER

WO0WO1

(2)

GENERIC CLOCKCONTROLLER

CMP[1..0]

1. Some products have different number of SERCOM instances, Timer/Counter instances and ADCsignals. Refer to the Configuration Summary.

2. The three TCC instances have different configurations, including the number of Waveform Output(WO) lines. Refer to the TCC Configutations for details.

Related LinksConfiguration Summary



TCC Configurations



5. Pinout

5.1 SAM D21GxL

5.1.1 QFN48

PA21

PA02 1PA03 2PB04 3PB05 4

GNDANA 5VDDANA 6

PB08 7PB09 8PA04 9PA05 10PA06 11PA07 12

PA08

13PA

0914

PA10

15PA

1116

VDD

IO17

GN

D18

PB10

19PB

1120

PA12

21PA

1322

PA14

23PA

1524

VDDIO36GND35PA2534PA2433PA2332PA2231

30PA2029PA1928PA1827PA1726PA1625

PA27

3738PA

2839

RES

ETN

4041

GN

D

42VD

DC

OR

E

43VD

DIN

44PA

30

45PA

31

46PB

0247

PB03

48

DIGITAL PINANALOG PINOSCILLATORGROUNDINPUT SUPPLYREGULATED OUTPUT SUPPLYRESET PIN

PB00

PB01



5.2 SAM D21ExL

5.2.1 QFN32 / TQFP32

PB04

1

PB05

2PA02

3PA03

4PA04 5PA05 6PA06 7PA07 8

VDD

IO/A

NA

9G

ND

10PA

0811

PA09

12PA

1013

PA11

14PA

1415

PA15

16

PA2524PA2423PA2322PA2221PA1920PA1819PA1718PA1617

25R

ESET

N2627

GN

D

28VD

DC

OR

E

29VD

DIO

30PA

30

31PA

31

32PB

02PB

03

Digital PinAnalog PinOscillator PinGroundInput SupplyRegulated Output SupplyReset Pin



6. Signal Descriptions ListThe following table gives details on signal names classified by peripheral.

Signal Name Function Type Active Level

Analog Comparators - AC/AC1

AIN[3:0] AC Analog Inputs Analog

CMP[:0] AC Comparator Outputs Digital

Analog Digital Converter - ADC

AIN[17:0] ADC Analog Inputs Analog

VREFA ADC Voltage External Reference A Analog

VREFB ADC Voltage External Reference B Analog

Digital Analog Converter - DAC

VOUT DAC Voltage output Analog

VREFA DAC Voltage External Reference Analog

External Interrupt Controller - EIC

EXTINT[15:0] External Interrupts Input

NMI External Non-Maskable Interrupt Input

Generic Clock Generator - GCLK

GCLK_IO[7:0] Generic Clock (source clock or generic clock generatoroutput)

I/O

Power Manager - PM

RESETN Reset Input Low

Serial Communication Interface - SERCOMx

PAD[3:0] SERCOM I/O Pads I/O

System Control - SYSCTRL

XIN Crystal Input Analog/ Digital

XOUT Crystal Output Analog

Timer Counter - TCx

WO[1:0] Waveform Outputs Output

Timer Counter - TCCx

WO[1:0] Waveform Outputs Output

General Purpose I/O - PORT

PA25 - PA02 Parallel I/O Controller I/O Port A I/O




Signal Name Function Type Active Level


PB05 - PB00 Parallel I/O Controller I/O Port B I/O

PB11 - PB08 Parallel I/O Controller I/O Port B I/O



7. I/O Multiplexing and Considerations

7.1 Multiplexed SignalsEach pin is by default controlled by the PORT as a general purpose I/O and alternatively it can beassigned to one of the peripheral functions A, B, C, D, E, F, G or H. To enable a peripheral function on apin, the Peripheral Multiplexer Enable bit in the Pin Configuration register corresponding to that pin(PINCFGn.PMUXEN, n = 0-31) in the PORT must be written to one. The selection of peripheral functionA to H is done by writing to the Peripheral Multiplexing Odd and Even bits in the Peripheral Multiplexingregister (PMUXn.PMUXE/O) in the PORT.

This table describes the peripheral signals multiplexed to the PORT I/O pins.

Table 7-1. PORT Function MultiplexingPin I/O Pin Supply A B(1)(2) C D E F G H

SAMD21ExL SAMD21GxL EIC REF ADC AC AC1 DAC SERCOM(1)(2) SERCOM-ALT TC(3)

/TCC

TCC COM AC/

GCLK

1 1 PA02 VDDANA EXTINT[2] AIN[0] VOUT

2 2 PA03 VDDANA EXTINT[3] DAC/VREFA AIN[1]

3 3 PB04 VDDANA EXTINT[4] AIN[12] AIN[0]

4 4 PB05 VDDANA EXTINT[5] AIN[13] AIN[1]

7 PB08 VDDANA EXTINT[8] AIN[2] SERCOM4/PAD[0]

TC4/WO[0]

8 PB09 VDDANA EXTINT[9] AIN[3] SERCOM4/PAD[1]

TC4/WO[1]

5 9 PA04 VDDANA EXTINT[4] ADC/VREFB AIN[4] AIN[0] SERCOM0/PAD[0]

TCC0/WO[0]

6 10 PA05 VDDANA EXTINT[5] AIN[5] AIN[1] SERCOM0/PAD[1]

TCC0/WO[1]


TCC1/WO[0]


TCC1/WO[1]

11 13 PA08 VDDIO NMI AIN[16] SERCOM0/PAD[0]

SERCOM2/PAD[0]

TCC0/WO[0] TCC1/WO[2]

12 14 PA09 VDDIO EXTINT[9] AIN[17] SERCOM0/PAD[1]

SERCOM2/PAD[1]



SERCOM2/PAD[2]


GCLK_IO[4]


SERCOM2/PAD[3]


GCLK_IO[5]

19 PB10 VDDIO EXTINT[10] SERCOM4/PAD[2]

TC5/WO[0] TCC0/WO[4]

GCLK_IO[4]

20 PB11 VDDIO EXTINT[11] SERCOM4/PAD[3]


GCLK_IO[5]

21 PA12 VDDIO EXTINT[12] SERCOM2/PAD[0]

SERCOM4/PAD[0]


AC/CMP[0]


SERCOM4/PAD[1]


AC/CMP[1]

15 23 PA14 VDDIO EXTINT[14] SERCOM2/PAD[2]

SERCOM4/PAD[2]


GCLK_IO[0]


SERCOM4/PAD[3]


GCLK_IO[1]


SERCOM3/PAD[0]

TCC2/WO[0] TCC0/WO[6] GCLK_IO[2]


SERCOM3/PAD[1]

TCC2/WO[1] TCC0/WO[7] GCLK_IO[3]


SERCOM3/PAD[2]


AC/CMP[0]



Pin I/O Pin Supply A B(1)(2) C D E F G H

SAMD21ExL SAMD21GxL EIC REF ADC AC AC1 DAC SERCOM(1)(2) SERCOM-ALT TC(3)

/TCC

TCC COM AC/

GCLK


SERCOM3/PAD[3]


AC/CMP[1]


SERCOM3/PAD[2]


GCLK_IO[4]


SERCOM3/PAD[3]


GCLK_IO[5]


SERCOM5/PAD[0]


GCLK_IO[6]


SERCOM5/PAD[1]


GCLK_IO[7]

23 33 PA24(5) VDDIO EXTINT[12] SERCOM3/PAD[2]

SERCOM5/PAD[2]


AC1/CMP[0]

24 34 PA25(5) VDDIO EXTINT[13] SERCOM3/PAD[3]

SERCOM5/PAD[3]


AC1/CMP[1]

37 PA27 VDDIO EXTINT[15] GCLK_IO[0]

39 PA28 VDDIO EXTINT[8] GCLK_IO[0]


TCC1/WO[0] SWCLK GCLK_IO[0]


TCC1/WO[1] SWDIO(5)

45 PB00 AIN[8]

46 PB01 AIN[9]

31 47 PB02 VDDANA EXTINT[2] AIN[10] AIN[2] SERCOM5/PAD[0]

TC6/WO[0](6)

32 48 PB03 VDDANA EXTINT[3] AIN[11] AIN[3] SERCOM5/PAD[1]

TC6/WO[1](6)

1. All analog pin functions are on peripheral function B. Peripheral function B must be selected todisable the digital control of the pin.

2. Only some pins can be used in SERCOM I2C mode.3. Note that TC6 and TC7 are not supported on the SAM D21ExL and SAM D21GxL devices. Refer to

Configuration Summary for details.4. This function is only activated in the presence of a debugger.5. If the PA24 and PA25 pins are not connected, it is recommended to enable a pull-up on PA24 and

PA25 through input GPIO mode. The aim is to avoid an eventually extract power consumption(

Table 7-2. Oscillator Pinout

Oscillator Supply Signal I/O pin

XOSC VDDIO XIN PA14

XOUT PA15

7.2.2 Serial Wire Debug Interface PinoutOnly the SWCLK pin is mapped to the normal PORT functions. A debugger cold-plugging or hot-pluggingdetection will automatically switch the SWDIO port to the SWDIO function.

Table 7-3. Serial Wire Debug Interface Pinout

Signal Supply I/O pin

SWCLK VDDIO PA30

SWDIO VDDIO PA31

7.2.3 SERCOM I2C PinsTable 7-4. SERCOM Pins Supporting I2C

Device Pins Supporting I2C Hs mode

SAM D21LE PA08, PA09, PA16, PA17, PA22, PA23

SAM D21LG PA08, PA09, PA12, PA13, PA16, PA17, PA22, PA23

7.2.4 GPIO ClustersTable 7-5. GPIO Cluster

Package

Cluster GPIO Supply Pins connected to theCluster

48-pins 1 PA31, PA30 VDDIN pin42/GND pin40

2 PA28, PA27 VDDIN pin42/GND pin40 andVDDIO pin36/GND pin35

3 PA25, PA24, PA23, PA22, PA21, PA20, PA19, PA18,PA17, PA16, PA15, PA14, PA13, PA12, PB11, PB10

VDDIO pin36/GND pin35 andVDDIO pin17/GND pin18

4 PA11, PA10, PA09, PA08 VDDIO pin17/GND pin18

5 PA07, PA06, PA05, PA04, PB09, PB08 VDDANA pin6/GNDANA pin5

6 PA03, PA02, PB05, PB04, PB03, PB02, BP01, PB00 VDDANA pin6/GNDANA pin5

32-pins 1 PA31, PA30 VDDIO pin28/GND pin 26

2 PA25, PA24, PA23, PA22, PA19, PA18, PA17, PA16,PA15, PA14, PA11, PA10, PA09, PA08

VDDIO pin28/GND pin 26 andVDDANA pin9/GND pin10

3 PB05, PB04, PB03, PB02, PA07, PA06, PA05, PA04,PA03, PA02

VDDANA pin9/GND pin10

7.2.5 TCC ConfigurationsThe SAM D21L has three instances of the Timer/Counter for Control applications (TCC) peripheral, ,TCC[2:0]. The following table lists the features for each TCC instance.



Table 7-6. TCC Configuration Summary

TCC# Channels(CC_NUM)

WaveformOutput

(WO_NUM)

Countersize

Fault Dithering Outputmatrix

Dead TimeInsertion

(DTI)

SWAP Patterngeneration

0 4 8 24-bit Yes Yes Yes Yes Yes Yes

1 2 4 24-bit Yes Yes Yes

2 2 2 16-bit Yes

Note: The number of CC registers (CC_NUM) for each TCC corresponds to the number of compare/capture channels, so that a TCC can have more Waveform Outputs (WO_NUM) than CC registers.



8. Power Supply and Start-Up Considerations

8.1 Power Domain Overview

VOLTAGEREGULATOR

VDD

IN

VDD

CO

RE

GN

DADC

AC

DAC

OSC32K

VDD

ANA

GN

DAN

A

PA[7:2]

PB[9:0]

Digital Logic(CPU, peripherals)

DFLL48M

VDD

IO

OSC8M

XOSC

OSCULP32K

PA[31:16]

PB[31:10]

PA[15:14]

BOD33

POR

PA[13:8]BOD12

FDPLL96M

AC1

8.2 Power Supply Considerations

8.2.1 Power SuppliesThe device has several different power supply pins:

• VDDIO: Powers I/O lines, OSC8M and XOSC. Voltage is 1.62V to 3.63V.• VDDIN: Powers I/O lines and the internal regulator. Voltage is 1.62V to 3.63V.• VDDANA: Powers I/O lines and the ADC, AC, DAC, OSCULP32K, OSC32K. Voltage is 1.62V to

3.63V.• VDDCORE: Internal regulated voltage output. Powers the core, memories, peripherals, FDPLL96M,

and DFLL48M. Voltage is 1.2V.

The same voltage must be applied to both VDDIN, VDDIO and VDDANA. This common voltage isreferred to as VDD in the datasheet.

The ground pins, GND, are common to VDDCORE, VDDIO and VDDIN. The ground pin for VDDANA isGNDANA.



For decoupling recommendations for the different power supplies. Refer to Schematic Checklist fordetails.

Related LinksSchematic Checklist

8.2.2 Voltage RegulatorThe voltage regulator has two different modes:

• Normal mode: To be used when the CPU and peripherals are running• Low Power (LP) mode: To be used when the regulator draws small static current. It can be used in

standby mode

8.2.3 Typical Powering SchematicsThe SAM D21L uses a single supply from 1.62V to 3.63V.

The following figure shows the recommended power supply connection.

Figure 8-1. Power Supply Connection

(1.62V — 3.63V)Main Supply VDDIO

VDDANA

VDDIN

VDDCORE

GND

GNDANA

DEVICE

8.2.4 Power-Up Sequence

8.2.4.1 Minimum Rise RateThe integrated power-on reset (POR) circuitry monitoring the VDDANA power supply requires a minimumrise rate. Refer to the Electrical Characteristics for details.

Related LinksElectrical Characteristics

8.2.4.2 Maximum Rise RateThe rise rate of the power supply must not exceed the values described in Electrical Characteristics.Refer to the Electrical Characteristics for details.



Related LinksElectrical Characteristics

8.3 Power-UpThis section summarizes the power-up sequence of the device. The behavior after power-up is controlledby the Power Manager. Refer to PM – Power Manager for details.

Related LinksPM – Power Manager

8.3.1 Starting of ClocksAfter power-up, the device is set to its initial state and kept in reset, until the power has stabilizedthroughout the device. Once the power has stabilized, the device will use a 1MHz clock. This clock isderived from the 8MHz Internal Oscillator (OSC8M), which is divided by eight and used as a clock sourcefor generic clock generator 0. Generic clock generator 0 is the main clock for the Power Manager (PM).

Some synchronous system clocks are active, allowing software execution.

Refer to the “Clock Mask Register” section in PM – Power Manager for the list of default peripheral clocksrunning. Synchronous system clocks that are running are by default not divided and receive a 1MHz clockthrough generic clock generator 0. Other generic clocks are disabled except GCLK_WDT, which is usedby the Watchdog Timer (WDT).

Related LinksPM – Power Manager

8.3.2 I/O PinsAfter power-up, the I/O pins are tri-stated.

8.3.3 Fetching of Initial InstructionsAfter reset has been released, the CPU starts fetching PC and SP values from the reset address, whichis 0x00000000. This address points to the first executable address in the internal flash. The code readfrom the internal flash is free to configure the clock system and clock sources. Refer to PM – PowerManager, GCLK – Generic Clock Controller and SYSCTRL – System Controller for details. Refer to theARM Architecture Reference Manual for more information on CPU startup (http://www.arm.com).

Related LinksPM – Power ManagerSYSCTRL – System ControllerClock System

8.4 Power-On Reset and Brown-Out DetectorThe SAM D21L embeds three features to monitor, warn and/or reset the device:

• POR: Power-on reset on VDDANA• BOD33: Brown-out detector on VDDANA• BOD12: Voltage Regulator Internal Brown-out detector on VDDCORE. The Voltage Regulator

Internal BOD is calibrated in production and its calibration configuration is stored in the NVM UserRow. This configuration should not be changed if the user row is written to assure the correctbehavior of the BOD12.



http://www.arm.com

8.4.1 Power-On Reset on VDDANAPOR monitors VDDANA. It is always activated and monitors voltage at startup and also during all thesleep modes. If VDDANA goes below the threshold voltage, the entire chip is reset.

8.4.2 Brown-Out Detector on VDDANABOD33 monitors VDDANA. Refer to SYSCTRL – System Controller for details.

Related LinksSYSCTRL – System Controller

8.4.3 Brown-Out Detector on VDDCOREOnce the device has started up, BOD12 monitors the internal VDDCORE.



9. Product MappingFigure 9-1. SAM D21L Product Mapping

Code

SRAM

Undefined

Peripherals

Reserved

Undefined

Global Memory Space0x00000000

0x20000000

0x20008000

0x40000000

0x43000000

0x60000000

Internal SRAM

SRAM

AHB-APB Bridge A

AHB-APB Bridge B

AHB-APB Bridge C

AHB-APB

0x20000000 0x20007FFF

0x40000000

0x41000000

0x42000000

0x42FFFFFF

Reserved

PAC0

PM

SYSCTRL

GCLK

WDT

RTC

EIC

AHB-APB Bridge A0x40000000

0x40000400

0x40000800

0x40000C00

0x40001000

0x40001400

0x40001800

0x40FFFFFF 0x40001C00

AHB-APB Bridge B

Reserved

PAC1

DSU

NVMCTRL

PORT

0x41000000

0x41002000

0x41004000

0x41004400

0x41FFFFFF 0x41007000

SERCOM5(1)

PAC2

EVSYS

SERCOM0

SERCOM1

SERCOM2

SERCOM3

SERCOM4(1)

AHB-APB Bridge C

TC7(1)

TCC0

TCC1

TCC2

TC3

TC4

TC5

TC6(1)

ADC

AC

0x42000000

0x42000400

0x42000800

0x42000C00

0x42001000

0x42001400

0x42001800

0x42002000

0x42001C00

0x42003000

0x42003400

0x42003800

0x42003C00

0x42004000

0x42004400

0x42004800

Reserved0x42005800

0x60000200

0xFFFFFFFF

Reserved

System

0xE0000000

DAC0x42004C00

0x42002400

0x42002800

0x42002C00

Reserved

0x42005400

0x42005000Reserved

DMAC

Reserved

MTB

0x41004800

0x41005000

0x41006000

0xE0000000

0xE000E000

0xE000F000

0xE00FF000

0xE0100000 0xFFFFFFFF

System

Reserved

SCS

Reserved

ROMTable

Reserved

AC1

0x42FFFFFF1. Only available in SAMD21GxL.

Code0x00000000 0x00010000

0x1FFFFFFF

Internal Flash

Internal RWWsection

This figure represents the full configuration of the SAM D21L with maximum flash and SRAM capabilitiesand a full set of peripherals. Refer to the configuration summary for details.



10. Memories

10.1 Embedded Memories• Internal high-speed flash with Read-While-Write (RWW) capability on section of the array.• Internal high-speed flash• Internal high-speed RAM, single-cycle access at full speed

10.2 Physical Memory MapThe High-Speed bus is implemented as a bus matrix. All High-Speed bus addresses are fixed, and theyare never remapped in any way, even during boot. The 32-bit physical address space is mapped asfollow:

Table 10-1. Physical Memory Map

Memory Start address Size(1)

SAMD21x16L SAMD21x15L

Internal Flash 0x00000000 64Kbytes 32Kbytes

Internal RWW section 0x00010000 2Kbytes 1Kbytes

Internal SRAM 0x20000000 8Kbytes 4Kbytes

Peripheral Bridge A 0x40000000 64Kbytes 64Kbytes

Peripheral Bridge B 0x41000000 64Kbytes 64Kbytes

Peripheral Bridge C 0x42000000 64Kbytes 64Kbytes

1. x = G or E.

Table 10-2. Flash Memory Parameters(1)(2)

Device Flash size Number of pages Page size

SAMD21x16L 64Kbytes 1024 64 bytes


1. x = G or E.2. The number of pages (NVMP) and page size (PSZ) can be read from the NVM Pages and Page

Size bits in the NVM Parameter register in the NVMCTRL (PARAM.NVMP and PARAM.PSZ,respectively). Refer to NVM Parameter (PARAM) register for details.

Table 10-3. RWW section parameters

Device Flash size Number of pages Page size





10.3 NVM Calibration and Auxiliary SpaceThe device calibration data are stored in different sections of the NVM calibration and auxiliary spacepresented in Figure.Calibration and Auxiliary Space.

Figure 10-1. Calibration and Auxiliary Space

0x00800000

AUX0 offse t address

Automatic ca libra tion row Calibra tion and auxilia ry

space address offse t

AUX0 – NVM User Row

AUX1

0x00804000

0x00806000 AUX1 offse t address

0x00806000

Area 3 offse t address

Area 1: Reserved (64 bits )

Area 2: Device configura tion a rea (64 bits )

Area 1 address offse t

Area 2 offse t address

Area 3: Reserved (128bits )

Area 4: Software ca libra tion a rea (256bits )

0x00806008

0x00806010

0x00806020 Area 4 offse t address

AUX10x00806040

0x00000000

NVM base address + NVM s ize

NVM main address space

NVM Base Address

Calibra tion and auxilia ry space

0x00800000

NVM base address + 0x00800000

The values from the automatic calibration row are loaded into their respective registers at startup.

10.3.1 NVM User Row MappingThe NVM User Row contains calibration data that are automatically read at device power on.

The NVM User Row can be read at address 0x804000.

To write the NVM User Row refer to NVMCTRL – Non-Volatile Memory Controller.

Note that when writing to the user row the values do not get loaded by the other modules on the deviceuntil a device reset occurs.

Table 10-4. NVM User Row Mapping

Bit Position Name Usage

2:0 BOOTPROT Used to select one of eight different bootloader sizes. Refer toNVMCTRL – Non-Volatile Memory Controller. Default value = 7.

3 Reserved

6:4 EEPROM Used to select one of eight different EEPROM sizes. Refer toNVMCTRL – Non-Volatile Memory Controller. Default value = 7.

7 Reserved



Bit Position Name Usage

13:8 BOD33 Level BOD33 Threshold Level at power on. Refer to SYSCTRL BOD33register.Default value = 7.

14 BOD33 Enable BOD33 Enable at power on . Refer to SYSCTRL BOD33 register.Default value = 1.

16:15 BOD33 Action BOD33 Action at power on. Refer to SYSCTRL BOD33 register.Default value = 1.

24:17 Reserved Voltage Regulator Internal BOD (BOD12) configuration. These bitsare written in production and must not be changed. Default value =0x70.

25 WDT Enable WDT Enable at power on. Refer to WDT CTRL register.Default value = 0.

26 WDT Always-On WDT Always-On at power on. Refer to WDT CTRL register.Default value = 0.

30:27 WDT Period WDT Period at power on. Refer to WDT CONFIG register.Default value = 0x0B.

34:31 WDT Window WDT Window mode time-out at power on. Refer to WDT CONFIGregister.Default value = 0x05.

38:35 WDT EWOFFSET WDT Early Warning Interrupt Time Offset at power on. Refer to WDTEWCTRL register. Default value = 0x0B.

39 WDT WEN WDT Timer Window Mode Enable at power on. Refer to WDT CTRLregister. Default value = 0.

40 BOD33 Hysteresis BOD33 Hysteresis configuration at power on. Refer to SYSCTRLBOD33 register.Default value = 0.

41 Reserved Voltage Regulator Internal BOD(BOD12) configuration. This bit iswritten in production and must not be changed. Default value = 0.

47:42 Reserved

63:48 LOCK NVM Region Lock Bits. Refer to NVMCTRL – Non-Volatile MemoryController.Default value = 0xFFFF.

Related LinksNVMCTRL – Non-Volatile Memory ControllerBOD33CTRL

10.3.2 NVM Software Calibration Area MappingThe NVM Software Calibration Area contains calibration data that are measured and written duringproduction test. These calibration values should be read by the application software and written back tothe corresponding register.



The NVM Software Calibration Area can be read at address 0x806020.

The NVM Software Calibration Area can not be written.

Table 10-5. NVM Software Calibration Area Mapping

Bit Position Name Description

2:0 Reserved

14:3 Reserved

26:15 Reserved

34:27 ADC LINEARITY ADC Linearity Calibration. Should be written to ADC CALIBregister.

37:35 ADC BIASCAL ADC Bias Calibration. Should be written to ADC CALIBregister.

44:38 OSC32K CAL OSC32KCalibration. Should be written to SYSCTRL OSC32Kregister.

49:45 Reserved

54:50 Reserved

57:55 Reserved

63:58 DFLL48M COARSE CAL DFLL48M Coarse calibration value. Should be written toSYSCTRL DFLLVAL register.

73:64 Reserved

127:74 Reserved

10.3.3 Serial NumberEach device has a unique 128-bit serial number which is a concatenation of four 32-bit words containedat the following addresses:

Word 0: 0x0080A00C

Word 1: 0x0080A040

Word 2: 0x0080A044

Word 3: 0x0080A048

The uniqueness of the serial number is guaranteed only when using all 128 bits.



11. Processor And Architecture

11.1 Cortex M0+ ProcessorThe SAM D21L implements the ARM® Cortex®-M0+ processor, based on the ARMv6 Architecture andThumb®-2 ISA. The Cortex M0+ is 100% instruction set compatible with its predecessor, the Cortex-M0core, and upward compatible to Cortex-M3 and M4 cores. The ARM Cortex-M0+ implemented is revisionr0p1. For more information refer to http://www.arm.com.

11.1.1 Cortex M0+ ConfigurationTable 11-1. Cortex M0+ Configuration

Features Configurable option Device configuration

Interrupts External interrupts 0-32 28

Data endianness Little-endian or big-endian Little-endian

SysTick timer Present or absent Present

Number of watchpoint comparators 0, 1, 2 2

Number of breakpoint comparators 0, 1, 2, 3, 4 4

Halting debug support Present or absent Present

Multiplier Fast or small Fast (single cycle)

Single-cycle I/O port Present or absent Present

Wake-up interrupt controller Supported or not supported Not supported

Vector Table Offset Register Present or absent Present

Unprivileged/Privileged support Present or absent Absent(1)

Memory Protection Unit Not present or 8-region Not present

Reset all registers Present or absent Absent

Instruction fetch width 16-bit only or mostly 32-bit 32-bit

Note: 1. All software run in privileged mode only.

The ARM Cortex-M0+ core has two bus interfaces:• Single 32-bit AMBA-3 AHB-Lite system interface that provides connections to peripherals and all

system memory, which includes flash and RAM.• Single 32-bit I/O port bus interfacing to the PORT with 1-cycle loads and stores.

11.1.2 Cortex-M0+ Peripherals• System Control Space (SCS)

– The processor provides debug through registers in the SCS. Refer to the Cortex-M0+Technical Reference Manual for details (www.arm.com).

• System Timer (SysTick)



http://www.arm.comhttp://www.arm.com

– The System Timer is a 24-bit timer that extends the functionality of both the processor and theNVIC. Refer to the Cortex-M0+ Technical Reference Manual for details (www.arm.com).

• Nested Vectored Interrupt Controller (NVIC)– External interrupt signals connect to the NVIC, and the NVIC prioritizes the interrupts.

Software can set the priority of each interrupt. The NVIC and the Cortex-M0+ processor coreare closely coupled, providing low latency interrupt processing and efficient processing of latearriving interrupts. Refer to Nested Vector Interrupt Controller and the Cortex-M0+ TechnicalReference Manual for details (www.arm.com).

• System Control Block (SCB)– The System Control Block provides system implementation information, and system control.

This includes configuration, control, and reporting of the system exceptions. Refer to theCortex-M0+ Devices Generic User Guide for details (www.arm.com).

• Micro Trace Buffer (MTB)– The CoreSight MTB-M0+ (MTB) provides a simple execution trace capability to the Cortex-

M0+ processor. Refer to section Micro Trace Buffer and the CoreSight MTB-M0+ TechnicalReference Manual for details (www.arm.com).

11.1.3 Cortex-M0+ Address MapTable 11-2. Cortex-M0+ Address Map

Address Peripheral

0xE000E000 System Control Space (SCS)

0xE000E010 System Timer (SysTick)

0xE000E100 Nested Vectored Interrupt Controller (NVIC)

0xE000ED00 System Control Block (SCB)

0x41006000 (see also Product Mapping) Micro Trace Buffer (MTB)

11.1.4 I/O Interface

11.1.4.1 OverviewBecause accesses to the AMBA® AHB-Lite™ and the single cycle I/O interface can be made concurrently,the Cortex-M0+ processor can fetch the next instructions while accessing the I/Os. This enables singlecycle I/O accesses to be sustained for as long as needed. Refer to CPU Local Bus for more information.

Related LinksCPU Local Bus

11.1.4.2 DescriptionDirect access to PORT registers.

11.2 Nested Vector Interrupt Controller

11.2.1 OverviewThe Nested Vectored Interrupt Controller (NVIC) in the SAM D21L supports 32 interrupt lines with fourdifferent priority levels. For more details, refer to the Cortex-M0+ Technical Reference Manual(www.arm.com).



http://www.arm.comhttp://www.arm.comhttp://www.arm.comhttp://www.arm.comhttp://www.arm.com

11.2.2 Interrupt Line MappingEach of the 28 interrupt lines is connected to one peripheral instance, as shown in the table below. Eachperipheral can have one or more interrupt flags, located in the peripheral’s Interrupt Flag Status and Clear(INTFLAG) register. The interrupt flag is set when the interrupt condition occurs. Each interrupt in theperipheral can be individually enabled by writing a one to the corresponding bit in the peripheral’sInterrupt Enable Set (INTENSET) register, and disabled by writing a one to the corresponding bit in theperipheral’s Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated from theperipheral when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt requestsfor one peripheral are ORed together on system level, generating one interrupt request for eachperipheral. An interrupt request will set the corresponding interrupt pending bit in the NVIC interruptpending registers (SETPEND

sam d21el / sam d21glww1.microchip.com/downloads/en/devicedoc/40001883a.pdf · 32-bit arm-based...

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