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13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender , Alexander Wild, and Amir Moradi

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Page 1: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

13.04.17

SafeDRP: Yet Another Way TowardPower-Equalized Designs in FPGA

COSADE 2017

Maik Ender, Alexander Wild, and Amir Moradi

Page 2: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

2COSADE 2017 | SafeDRP | Maik Ender

▪ Variety of countermeasures

• Rekeying

• Masking

• Hiding

Motivation and Background

Page 3: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

3COSADE 2017 | SafeDRP | Maik Ender

▪ Variety of countermeasures

• Rekeying

• Masking

• Hiding

▪ This talk: power equalization on FPGAs

• Dynamic power consumption switches

Motivation and Background

Page 4: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

4COSADE 2017 | SafeDRP | Maik Ender

▪ Variety of countermeasures

• Rekeying

• Masking

• Hiding

▪ This talk: power equalization on FPGAs

• Dynamic power consumption switches

▪ Why do we need another scheme?

• Pitfalls in implementation

• Lastly published GliFreD has high resource consumption of FF

Motivation and Background

Page 5: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

5COSADE 2017 | SafeDRP | Maik Ender

▪ Variety of countermeasures

• Rekeying

• Masking

• Hiding

▪ This talk: power equalization on FPGAs

• Dynamic power consumption switches

▪ Why do we need another scheme?

• Pitfalls in implementation

• Lastly published GliFreD has high resource consumption of FF

▪ Idea: less FF while addressing all pitfalls

Motivation and Background

Page 6: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

6COSADE 2017 | SafeDRP | Maik Ender

Field Programmable Gate Array

Concept

Source: Electronics 2015; Optimally Fortifying Logic Reliability through Criticality Ranking; http://www.mdpi.com/2079-9292/4/1/150/htm

Page 7: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

7COSADE 2017 | SafeDRP | Maik Ender

Field Programmable Gate Array

Concept

Source: Electronics 2015; Optimally Fortifying Logic Reliability through Criticality Ranking; http://www.mdpi.com/2079-9292/4/1/150/htm

Page 8: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

8COSADE 2017 | SafeDRP | Maik Ender

▪ Differential encoding

▪ Valid values: 10 or 01

▪ No Inverter

Dual-Rail-Precharge (DRP)

Dual-Rail Logic

Page 9: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

9COSADE 2017 | SafeDRP | Maik Ender

▪ Differential encoding

▪ Valid values: 10 or 01

▪ No Inverter

Dual-Rail-Precharge (DRP)

Dual-Rail Logic Precharge Logic

▪ Alternates between

Precharge and logic value

▪ Precharge and evaluation

phase

Page 10: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

10COSADE 2017 | SafeDRP | Maik Ender

▪ Differential encoding

▪ Valid values: 10 or 01

▪ No Inverter

Dual-Rail-Precharge (DRP)

Dual-Rail Logic Precharge Logic

▪ Alternates between

Precharge and logic value

▪ Precharge and evaluation

phase

Dual-Rail Precharge Logic

▪ Differential encoding

• Precharge phase: 00 or 11

• Evaluation phase: 01 or 10

▪ One transition per phase

Page 11: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

11COSADE 2017 | SafeDRP | Maik Ender

▪ Differential encoding

▪ Valid values: 10 or 01

▪ No Inverter

Dual-Rail-Precharge (DRP)

Dual-Rail Logic Precharge Logic

▪ Alternates between

Precharge and logic value

▪ Precharge and evaluation

phase

Dual-Rail Precharge Logic

▪ Differential encoding

• Precharge phase: 00 or 11

• Evaluation phase: 01 or 10

▪ One transition per phase

Page 12: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

12COSADE 2017 | SafeDRP | Maik Ender

▪ Transition based on the

arriving signals

Pitfalls

Early Evaluation

Page 13: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

13COSADE 2017 | SafeDRP | Maik Ender

▪ Transition based on the

arriving signals

Pitfalls

Early Evaluation Glitches

▪ Undesired transition

Page 14: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

14COSADE 2017 | SafeDRP | Maik Ender

▪ Transition based on the

arriving signals

Pitfalls

Early Evaluation Glitches

▪ Undesired transition

Routing

▪ Different

capacities

Pictures Soruce: Wei He, et.al.; A Precharge-Absorbed DPL Logic for Reducing Early Propagation Effects on FPGA Implementations

Page 15: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

15COSADE 2017 | SafeDRP | Maik Ender

Idea of Our Advanced Hiding Schemes

LUT

Page 16: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

16COSADE 2017 | SafeDRP | Maik Ender

Idea of Our Advanced Hiding Schemes

LUT

LUT

LUT

LUT LUT

LUT

Page 17: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

17COSADE 2017 | SafeDRP | Maik Ender

Idea of Our Advanced Hiding Schemes

LUT

LUT

LUT

LUT LUT

LUT

Page 18: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

18COSADE 2017 | SafeDRP | Maik Ender

Idea of Our Advanced Hiding Schemes

LUT

LUT

LUT

LUT LUT

LUT• Early evaluation,

glitches

Page 19: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

19COSADE 2017 | SafeDRP | Maik Ender

Idea of Our Advanced Hiding Schemes

LUT

LUT

LUT

LUT LUT

LUT• Early evaluation,

glitches

• I/O-Handling

Page 20: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

20COSADE 2017 | SafeDRP | Maik Ender

Idea of Our Advanced Hiding Schemes

LUT

LUT

LUT

LUT LUT

LUT• Early evaluation,

glitches

• I/O-Handling

• Consider routing

Page 21: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

21COSADE 2017 | SafeDRP | Maik Ender

Idea of Our Advanced Hiding Schemes

LUT

LUT

LUT

LUT LUT

LUT• Early evaluation,

glitches

• I/O-Handling

• Consider routing

Page 22: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

22COSADE 2017 | SafeDRP | Maik Ender

Idea of Our Advanced Hiding Schemes

LUT

LUT

LUT

LUT LUT

LUT• Early evaluation,

glitches

active signal

• I/O-Handling

• Consider routing

Page 23: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

23COSADE 2017 | SafeDRP | Maik Ender

Idea of Our Advanced Hiding Schemes

LUT

LUT

LUT

LUT LUT

LUT• Early evaluation,

glitches

active signal

one after another

I/O-Handling

• Consider routing

Page 24: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

24COSADE 2017 | SafeDRP | Maik Ender

Idea of Our Advanced Hiding Schemes

LUT

LUT

LUT

LUT LUT

LUT• Early evaluation,

glitches

active signal

one after another

I/O-Handling

• Consider routing

Page 25: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

25COSADE 2017 | SafeDRP | Maik Ender

Idea of Our Advanced Hiding Schemes

LUT

LUT

LUT

LUT LUT

LUT• Early evaluation,

glitches

active signal

one after another

I/O-Handling

• Consider routing

Page 26: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

26COSADE 2017 | SafeDRP | Maik Ender

Idea of Our Advanced Hiding Schemes

LUT

LUT

LUT

LUT LUT

LUT• Early evaluation,

glitches

active signal

one after another

I/O-Handling

• Consider routing

Page 27: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

27COSADE 2017 | SafeDRP | Maik Ender

Idea of Our Advanced Hiding Schemes

LUT

LUT

LUT

LUT LUT

LUT• Early evaluation,

glitches

active signal

one after another

I/O-Handling

use FF/latches

Consider routing

FF

FF

Page 28: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

28COSADE 2017 | SafeDRP | Maik Ender

Idea of Our Advanced Hiding Schemes

LUT

LUT

LUT

LUT LUT

LUT• Early evaluation,

glitches

active signal

one after another

I/O-Handling

use FF/latches

Consider routing

FF

FF

Page 29: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

29COSADE 2017 | SafeDRP | Maik Ender

Idea of Our Advanced Hiding Schemes

LUT

LUT

LUT

LUT LUT

LUT• Early evaluation,

glitches

active signal

one after another

I/O-Handling

use FF/latches

Consider routing

FF

FF

Page 30: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

30COSADE 2017 | SafeDRP | Maik Ender

Idea of Our Advanced Hiding Schemes

LUT

LUT

LUT

LUT LUT

LUT• Early evaluation,

glitches

active signal

one after another

I/O-Handling

use FF/latches

Consider routing

FF

FF

Generate by Mixed-Mode Clock Manager (MMCM)

Page 31: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

31COSADE 2017 | SafeDRP | Maik Ender

Idea of Our Advanced Hiding Schemes

• Early evaluation,

glitches

active signal

one after another

• I/O-Handling

use FF/latches

• Consider routing

duplication

1. Place&Route

LUT

LUT

LUT

LUT LUT

LUT FF

FF

Page 32: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

32COSADE 2017 | SafeDRP | Maik Ender

Idea of Our Advanced Hiding Schemes

• Early evaluation,

glitches

active signal

one after another

• I/O-Handling

use FF/latches

• Consider routing

duplication

1. Place&Route

2. Clone

LUT

LUT

LUT

LUT LUT

LUT FF

FF

LUT

LUT

LUT

LUT LUT

LUT FF

FF

Page 33: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

33COSADE 2017 | SafeDRP | Maik Ender

Idea of Our Advanced Hiding Schemes

• Early evaluation,

glitches

active signal

one after another

• I/O-Handling

use FF/latches

• Consider routing

duplication

1. Place&Route

2. Clone

3. Place clone

LUT

LUT

LUT

LUT LUT

LUT FF

FF

LUT

LUT

LUT

LUT LUT

LUT FF

FF

Page 34: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

34COSADE 2017 | SafeDRP | Maik Ender

Idea of Our Advanced Hiding Schemes

• Early evaluation,

glitches

active signal

one after another

• I/O-Handling

use FF/latches

• Consider routing

duplication

1. Place&Route

2. Clone

3. Place clone

4. Invert

→ Equal routing

LUT

LUT

LUT

LUT LUT

LUT FF

FF

LUT

LUT

LUT

LUT LUT

LUT FF

FF

Page 35: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

35COSADE 2017 | SafeDRP | Maik Ender

Side-Channel EvaluationMeasurement Setup

Source Sakura in Specification Guide and http://satoh.cs.uec.ac.jp/SAKURA/hardware/SAKURA-X.html

Source Picoscope: https://www.picotech.com/oscilloscope/6407/high-speed-digitizer

Source IBM: https://commons.wikimedia.org/wiki/File:IBM_PC_5150.jpg User Zarex

Xilinx Kintex-7 on Sakura-X

Round based AES-128

http://satoh.cs.uec.ac.jp/SAKURA/hardware/SAKURA-X.html
https://www.picotech.com/oscilloscope/6407/high-speed-digitizer
https://commons.wikimedia.org/wiki/File:IBM_PC_5150.jpg
Page 36: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

36COSADE 2017 | SafeDRP | Maik Ender

Side-Channel EvaluationMeasurement Setup

Source Sakura in Specification Guide and http://satoh.cs.uec.ac.jp/SAKURA/hardware/SAKURA-X.html

Source Picoscope: https://www.picotech.com/oscilloscope/6407/high-speed-digitizer

Source IBM: https://commons.wikimedia.org/wiki/File:IBM_PC_5150.jpg User Zarex

Xilinx Kintex-7 on Sakura-X

PicoScope 6402B @ 1.25 GS/s

Round based AES-128

http://satoh.cs.uec.ac.jp/SAKURA/hardware/SAKURA-X.html
https://www.picotech.com/oscilloscope/6407/high-speed-digitizer
https://commons.wikimedia.org/wiki/File:IBM_PC_5150.jpg
Page 37: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

37COSADE 2017 | SafeDRP | Maik Ender

Side-Channel EvaluationMeasurement Setup

Source Sakura in Specification Guide and http://satoh.cs.uec.ac.jp/SAKURA/hardware/SAKURA-X.html

Source Picoscope: https://www.picotech.com/oscilloscope/6407/high-speed-digitizer

Source IBM: https://commons.wikimedia.org/wiki/File:IBM_PC_5150.jpg User Zarex

Xilinx Kintex-7 on Sakura-X

PicoScope 6402B @ 1.25 GS/s

Round based AES-128

10,000,000 Traces

http://satoh.cs.uec.ac.jp/SAKURA/hardware/SAKURA-X.html
https://www.picotech.com/oscilloscope/6407/high-speed-digitizer
https://commons.wikimedia.org/wiki/File:IBM_PC_5150.jpg
Page 38: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

38COSADE 2017 | SafeDRP | Maik Ender

Comparison

[17] A. Moradi and A. Wild. Assessment of Hiding the Higher-Order Leakages

in Hardware - what are the achievements versus overheads? In CHES 2015

[30] A. Wild, et.al. GliFreD: Glitch-Free Duplication – Towards Power-Equalized

Circuits on FPGAs. IEEE Transactions on Computers, 2017.

Page 39: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

39COSADE 2017 | SafeDRP | Maik Ender

Comparison

[17] A. Moradi and A. Wild. Assessment of Hiding the Higher-Order Leakages

in Hardware - what are the achievements versus overheads? In CHES 2015

[30] A. Wild, et.al. GliFreD: Glitch-Free Duplication – Towards Power-Equalized

Circuits on FPGAs. IEEE Transactions on Computers, 2017.

Page 40: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

40COSADE 2017 | SafeDRP | Maik Ender

Comparison

[17] A. Moradi and A. Wild. Assessment of Hiding the Higher-Order Leakages

in Hardware - what are the achievements versus overheads? In CHES 2015

[30] A. Wild, et.al. GliFreD: Glitch-Free Duplication – Towards Power-Equalized

Circuits on FPGAs. IEEE Transactions on Computers, 2017.

Page 41: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

41COSADE 2017 | SafeDRP | Maik Ender

▪ Reduced FF utilization

• 8.9 Improved GliFreD

Comparison

[17] A. Moradi and A. Wild. Assessment of Hiding the Higher-Order Leakages

in Hardware - what are the achievements versus overheads? In CHES 2015

[30] A. Wild, et.al. GliFreD: Glitch-Free Duplication – Towards Power-Equalized

Circuits on FPGAs. IEEE Transactions on Computers, 2017.

Page 42: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

42COSADE 2017 | SafeDRP | Maik Ender

▪ Reduced FF utilization

• 8.9 Improved GliFreD

• 17.3 GliFreD

Comparison

[17] A. Moradi and A. Wild. Assessment of Hiding the Higher-Order Leakages

in Hardware - what are the achievements versus overheads? In CHES 2015

[30] A. Wild, et.al. GliFreD: Glitch-Free Duplication – Towards Power-Equalized

Circuits on FPGAs. IEEE Transactions on Computers, 2017.

Page 43: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

43COSADE 2017 | SafeDRP | Maik Ender

▪ Reduced FF utilization

• 8.9 Improved GliFreD

• 17.3 GliFreD

Comparison

[17] A. Moradi and A. Wild. Assessment of Hiding the Higher-Order Leakages

in Hardware - what are the achievements versus overheads? In CHES 2015

[30] A. Wild, et.al. GliFreD: Glitch-Free Duplication – Towards Power-Equalized

Circuits on FPGAs. IEEE Transactions on Computers, 2017.

Page 44: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

44COSADE 2017 | SafeDRP | Maik Ender

▪ Reduced FF utilization

• 8.9 Improved GliFreD

• 17.3 GliFreD

Comparison

[17] A. Moradi and A. Wild. Assessment of Hiding the Higher-Order Leakages

in Hardware - what are the achievements versus overheads? In CHES 2015

[30] A. Wild, et.al. GliFreD: Glitch-Free Duplication – Towards Power-Equalized

Circuits on FPGAs. IEEE Transactions on Computers, 2017.

Page 45: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

45COSADE 2017 | SafeDRP | Maik Ender

▪ Reduced FF utilization

• 8.9 Improved GliFreD

• 17.3 GliFreD

▪ Reduced latency but GliFreD might reach a higher max.

frequency

Comparison

[17] A. Moradi and A. Wild. Assessment of Hiding the Higher-Order Leakages

in Hardware - what are the achievements versus overheads? In CHES 2015

[30] A. Wild, et.al. GliFreD: Glitch-Free Duplication – Towards Power-Equalized

Circuits on FPGAs. IEEE Transactions on Computers, 2017.

Page 46: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

46COSADE 2017 | SafeDRP | Maik Ender

▪ Signal-to-Noise ratio 𝑆𝑁𝑅 =𝑣𝑎𝑟(𝑆𝑖𝑔𝑛𝑎𝑙)

𝑣𝑎𝑟(𝑁𝑜𝑖𝑠𝑒)

• Dependency of the power traces to the plaintext

Side-Channel EvaluationMethods

Page 47: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

47COSADE 2017 | SafeDRP | Maik Ender

▪ Signal-to-Noise ratio 𝑆𝑁𝑅 =𝑣𝑎𝑟(𝑆𝑖𝑔𝑛𝑎𝑙)

𝑣𝑎𝑟(𝑁𝑜𝑖𝑠𝑒)

• Dependency of the power traces to the plaintext

▪ Information-Theoretic mutual information

• Amount of exploitable information

Side-Channel EvaluationMethods

Page 48: SafeDRP: Yet Another Way Toward Power-Equalized Designs in … · 2017-08-24 · 13.04.17 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA COSADE 2017 Maik Ender, Alexander

48COSADE 2017 | SafeDRP | Maik Ender

▪ Signal-to-Noise ratio 𝑆𝑁𝑅 =𝑣𝑎𝑟(𝑆𝑖𝑔𝑛𝑎𝑙)

𝑣𝑎𝑟(𝑁𝑜𝑖𝑠𝑒)

• Dependency of the power traces to the plaintext

▪ Information-Theoretic mutual information

• Amount of exploitable information

▪ Correlation power analysis (CPA)

• Common key recovery attack

• HW and bit model of intermediate S-Box state

Side-Channel EvaluationMethods

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49COSADE 2017 | SafeDRP | Maik Ender

▪ Signal-to-Noise ratio 𝑆𝑁𝑅 =𝑣𝑎𝑟(𝑆𝑖𝑔𝑛𝑎𝑙)

𝑣𝑎𝑟(𝑁𝑜𝑖𝑠𝑒)

• Dependency of the power traces to the plaintext

▪ Information-Theoretic mutual information

• Amount of exploitable information

▪ Correlation power analysis (CPA)

• Common key recovery attack

• HW and bit model of intermediate S-Box state

▪ Moments-Correlating DPA (MC-DPA)

• Key recovery attack w/o particular power model

Side-Channel EvaluationMethods

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50COSADE 2017 | SafeDRP | Maik Ender

▪ Signal-to-Noise ratio 𝑆𝑁𝑅 =𝑣𝑎𝑟(𝑆𝑖𝑔𝑛𝑎𝑙)

𝑣𝑎𝑟(𝑁𝑜𝑖𝑠𝑒)

• Dependency of the power traces to the plaintext

▪ Information-Theoretic mutual information

• Amount of exploitable information

▪ Correlation power analysis (CPA)

• Common key recovery attack

• HW and bit model of intermediate S-Box state

▪ Moments-Correlating DPA (MC-DPA)

• Key recovery attack w/o particular power model

▪ Semi-fix vs. random Welch’s t-test

• Overview of the existing detectable leakage

Side-Channel EvaluationMethods

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51COSADE 2017 | SafeDRP | Maik Ender

Side-Channel EvaluationProfiles

Duplication ± Active & Pre

✓ ✓

Profile 1 (SafeDRP)

Measurement Points

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52COSADE 2017 | SafeDRP | Maik Ender

Side-Channel EvaluationProfiles

Duplication ± Active & Pre

✓ ✓

Profile 1 (SafeDRP)

Duplication ± Active & Pre

✓

Profile 2

Measurement Points

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53COSADE 2017 | SafeDRP | Maik Ender

Side-Channel EvaluationProfiles

Duplication ± Active & Pre

✓ ✓

Profile 1 (SafeDRP)

Duplication ± Active & Pre

✓

Profile 2

Duplication ± Active & Pre

Profile 3 (Unprotected)

Measurement Points

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54COSADE 2017 | SafeDRP | Maik Ender

Duplication ± Active & Pre

✓ ✓

Profile 1 (SafeDRP)

Duplication ± Active & Pre

✓

Profile 2

Duplication ± Active & Pre

Profile 3 (Unprotected)

Side-Channel EvaluationSNR

𝑆𝑁𝑅 =𝑣𝑎𝑟(𝑆𝑖𝑔𝑛𝑎𝑙)

𝑣𝑎𝑟(𝑁𝑜𝑖𝑠𝑒)

Measurement Points

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55COSADE 2017 | SafeDRP | Maik Ender

Duplication ± Active & Pre

✓ ✓

Profile 1 (SafeDRP)

Duplication ± Active & Pre

✓

Profile 2

Duplication ± Active & Pre

Profile 3 (Unprotected)

Side-Channel EvaluationSNR

𝑆𝑁𝑅 =𝑣𝑎𝑟(𝑆𝑖𝑔𝑛𝑎𝑙)

𝑣𝑎𝑟(𝑁𝑜𝑖𝑠𝑒)

Measurement Points

Decrease Factor 20.03784

0.00018≈ 214

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56COSADE 2017 | SafeDRP | Maik Ender

Duplication ± Active & Pre

✓ ✓

Profile 1 (SafeDRP)

Duplication ± Active & Pre

✓

Profile 2

Duplication ± Active & Pre

Profile 3 (Unprotected)

Side-Channel EvaluationSNR

𝑆𝑁𝑅 =𝑣𝑎𝑟(𝑆𝑖𝑔𝑛𝑎𝑙)

𝑣𝑎𝑟(𝑁𝑜𝑖𝑠𝑒)

Measurement Points

Decrease Factor 30.05523

0.00018≈ 313

Decrease Factor 20.03784

0.00018≈ 214

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57COSADE 2017 | SafeDRP | Maik Ender

Duplication ± Active & Pre

✓ ✓

Profile 1 (SafeDRP)

Duplication ± Active & Pre

✓

Profile 2

Duplication ± Active & Pre

Profile 3 (Unprotected)

Side-Channel EvaluationIT (Mutual Information)

Measurement Points

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58COSADE 2017 | SafeDRP | Maik Ender

Duplication ± Active & Pre

✓ ✓

Profile 1 (SafeDRP)

Duplication ± Active & Pre

✓

Profile 2

Duplication ± Active & Pre

Profile 3 (Unprotected)

Side-Channel EvaluationIT (Mutual Information)

Decrease Factor 20.0267

0.00015≈ 183

Measurement Points

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59COSADE 2017 | SafeDRP | Maik Ender

Duplication ± Active & Pre

✓ ✓

Profile 1 (SafeDRP)

Duplication ± Active & Pre

✓

Profile 2

Duplication ± Active & Pre

Profile 3 (Unprotected)

Side-Channel EvaluationIT (Mutual Information)

Decrease Factor 20.0267

0.00015≈ 183

Measurement Points

Decrease Factor 30.0386

0.00015≈ 265

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60COSADE 2017 | SafeDRP | Maik Ender

Duplication ± Active & Pre

✓ ✓

Profile 1 (SafeDRP)

Duplication ± Active & Pre

✓

Profile 2

Duplication ± Active & Pre

Profile 3 (Unprotected)

Side-Channel EvaluationCPA HW S-Box Intermediate Model

Measurement Points

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61COSADE 2017 | SafeDRP | Maik Ender

Duplication ± Active & Pre

✓ ✓

Profile 1 (SafeDRP)

Duplication ± Active & Pre

✓

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Duplication ± Active & Pre

Profile 3 (Unprotected)

Side-Channel EvaluationCPA HW S-Box Intermediate Model

Decrease

Factor 29

Measurement Points

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62COSADE 2017 | SafeDRP | Maik Ender

Duplication ± Active & Pre

✓ ✓

Profile 1 (SafeDRP)

Duplication ± Active & Pre

✓

Profile 2

Duplication ± Active & Pre

Profile 3 (Unprotected)

Side-Channel EvaluationCPA HW S-Box Intermediate Model

Decrease

Factor 29

Measurement Points

Rule of Thumb (RoT):2,184,700 𝑇𝑟𝑎𝑐𝑒𝑠to recover the key

n ≈28

𝜌2

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63COSADE 2017 | SafeDRP | Maik Ender

Duplication ± Active & Pre

✓ ✓

Profile 1 (SafeDRP)

Duplication ± Active & Pre

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Duplication ± Active & Pre

Profile 3 (Unprotected)

Side-Channel EvaluationCPA HW S-Box Intermediate Model

RoT:𝜌2

𝜌1

2≈ 881

Decrease

Factor 29

Measurement Points

Rule of Thumb (RoT):2,184,700 𝑇𝑟𝑎𝑐𝑒𝑠to recover the key

n ≈28

𝜌2

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64COSADE 2017 | SafeDRP | Maik Ender

Duplication ± Active & Pre

✓ ✓

Profile 1 (SafeDRP)

Duplication ± Active & Pre

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Profile 3 (Unprotected)

Side-Channel EvaluationCPA HW S-Box Intermediate Model

RoT:𝜌2

𝜌1

2≈ 881

Decrease

Factor 29

Measurement Points

HW Model does not fit

Rule of Thumb (RoT):2,184,700 𝑇𝑟𝑎𝑐𝑒𝑠to recover the key

n ≈28

𝜌2

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65COSADE 2017 | SafeDRP | Maik Ender

Duplication ± Active & Pre

Profile 3 (Unprotected)

Duplication ± Active & Pre

✓

Profile 2

Duplication ± Active & Pre

✓ ✓

Profile 1 (SafeDRP)

Side-Channel EvaluationMC-DPA

Measurement Points

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66COSADE 2017 | SafeDRP | Maik Ender

Duplication ± Active & Pre

Profile 3 (Unprotected)

Duplication ± Active & Pre

✓

Profile 2

Duplication ± Active & Pre

✓ ✓

Profile 1 (SafeDRP)

Side-Channel EvaluationMC-DPA

Measurement Points

Rule of Thumb (RoT):244,000 𝑇𝑟𝑎𝑐𝑒𝑠

to recover the key

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67COSADE 2017 | SafeDRP | Maik Ender

Duplication ± Active & Pre

Profile 3 (Unprotected)

Duplication ± Active & Pre

✓

Profile 2

Duplication ± Active & Pre

✓ ✓

Profile 1 (SafeDRP)

Side-Channel EvaluationMC-DPA

Measurement Points

RoT:𝜌2

𝜌1

2≈ 327

Decrease Factor 18

Rule of Thumb (RoT):244,000 𝑇𝑟𝑎𝑐𝑒𝑠

to recover the key

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68COSADE 2017 | SafeDRP | Maik Ender

Duplication ± Active & Pre

Profile 3 (Unprotected)

Duplication ± Active & Pre

✓

Profile 2

Duplication ± Active & Pre

✓ ✓

Profile 1 (SafeDRP)

Side-Channel EvaluationMC-DPA

Measurement Points

RoT:𝜌2

𝜌1

2≈ 327

Decrease Factor 18

Rule of Thumb (RoT):244,000 𝑇𝑟𝑎𝑐𝑒𝑠

to recover the key

RoT:𝜌3

𝜌1

2≈ 468

Decrease Factor 21

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69COSADE 2017 | SafeDRP | Maik Ender

Side-Channel EvaluationWelch’s T-Test

• Semi-fix vs. random

• 5th round first 64 bit

zero [1]

• 1,000,000 Traces

• Leakage only in 5th

round

[1] Evaluating the Duplication of Dual-Rail

Precharge Logics on FPGAs; Alexander

Wild, Amir Moradi, Tim Güneysu;

COSDAE 2015

Measurement Points

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70COSADE 2017 | SafeDRP | Maik Ender

▪ Improved DRP scheme

• Reduce the FF utilization

• Complex control logic

▪ Addressing all pitfalls

• Avoiding glitches

• Preventing early evaluation

• Mitigate the imbalanced routings

▪ Combination [2] with sound masking scheme for a

practical secure implementation

Conclusion

[2] A. Wild and A. Moradi; Assessment of Hiding the Higher-Order Leakage in Hardware

– what are the achievements versus overheads?; CHES 2015

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71COSADE 2017 | SafeDRP | Maik Ender

▪ Improved DRP scheme

• Reduce the FF utilization

• Complex control logic

▪ Addressing all pitfalls

• Avoiding glitches

• Preventing early evaluation

• Mitigate the imbalanced routings

▪ Combination [2] with sound masking scheme for a

practical secure implementation

Conclusion

[2] A. Wild and A. Moradi; Assessment of Hiding the Higher-Order Leakage in Hardware

– what are the achievements versus overheads?; CHES 2015

Thank you!

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72COSADE 2017 | SafeDRP | Maik Ender


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