© Semiconductor Components Industries, LLC, 2016

August, 2017 − Rev. 11 Publication Order Number:

RSL10CN/D

RSL10

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• 384 kB/,

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WLCSP51CASE 567MT

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XXXXXX = Specific Device CodeA = Assembly LocationWL = Wafer LotY or YY = YearWW = Work WeekG or � = Pb−Free Package

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Device Package Shipping†

ORDERING INFORMATION

NCH−RSL10−101WC51−ABG

WLCSP51(Pb−Free)

5000 / Tape &Reel

†For information on tape and reel specifications,including part orientation and tape sizes, pleaserefer to our Tape and Reel Packaging SpecificationBrochure, BRD8011/D.

NCH−RSL10−101Q48−ABG(Note 1)

QFN48(Pb−Free)

3000 / Tape &Reel

481

QFN48CASE 485BA

1. QFN48 version: production ready: July 2017

(QFN48) (WLCSP51)

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RSL10

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RSL10���

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Radio PHY

Baseband controllerBluetooth 5 (LE 2M) and custom protocol

Power Management

LPDSP3232−bit Dual Harvard core

ARM� Cortex�-M3

Processor

Interfaces

Oscillators

Timers

IP Protection

JTAG

SWJ−DP

DMA

RAMs andFlash

ADC

PCM

I2C

UART

ADC (4x)

DMIC(2x)

PWM(2x)

GPIO

XTAL_32 kHz

XTAL_48 MHz

Battery

OD

Figure 1. RSL10 Block Diagram

SPI(2x)

BusArbiters

Sample Rate ConverterAudio Sink Clock

Counters

Table 1. ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Min Max Unit

VBAT Power supply voltage 3.63 V

VDDO I/O supply voltage 3.63 V

VSSRF RF front−end ground −0.3 V

VSSA Analog ground −0.3 V

VSSD Digital core and I/O ground −0.3 V

Vin Voltage at any input pin VSSD − 0.3 VDDC + 0.3 V

T functional Functional temperature range −40 85 °C

T storage Storage temperature range −40 85 °C

Caution: Class 2 ESD Sensitivity, JESD22−A114−B (2000 V)

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionalityshould not be assumed, damage may occur and reliability may be affected.(����) ����� �����������，�������。�������，������� �，��� !����，"#�$%。

Table 2. RECOMMENDED OPERATING CONDITIONS

Description Symbol Conditions Min Typ Max Units

Supply voltage operating range VBAT Input supply voltage on VBAT pin 1.1 1.25 3.3 V

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyondthe Recommended Operating Ranges limits may affect device reliability.&'�(�)*：

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Table 3. ELECTRICAL PERFORMANCE SPECIFICATIONS Unless otherwise noted, the specifications mentioned in the table below are valid at 25°C at VBAT = VDDO = 1.25 V.

Description Symbol Conditions Min Typ Max Units

OVERALL

Current consumption RX,VBAT = 1.25 V

IVBAT RX Mode, ON Semiconductor propri-etary audio streaming protocol at 7 kHzaudio BW, 5.5 ms delay.

− 1.8 − mA

Current consumption TX,VBAT = 1.25 V

IVBAT TX Mode, ON Semiconductor propri-etary audio streaming protocol at 7 kHzaudio BW, 5.5 ms delay.

− 1.8 − mA

Deep sleep current,example 1, VBAT = 1.25 V

Ids1 Wake up from wake up pin. − 50 − nA

Deep sleep current,example 2, VBAT = 1.25 V

Ids2 Embedded 32 kHz oscillator runningwith interrupts from timer or external pin.

− 90 − nA

Deep sleep current,example 3, VBAT = 1.25 V

Ids3 As Ids2 but with 8 kB RAM data reten-tion.

− 300 − nA

Standby Mode current,VBAT = 1.25 V

Istb Digital blocks and memories are notclocked and are powered at a reducedvoltage.

− 30 − �A

Current consumption RX,VBAT = 3 V

IVBAT RX Mode, ON Semiconductor propri-etary audio streaming protocol at 7 kHzaudio BW, 5.5 ms delay.

− 0.9 − mA

Current consumption TX,VBAT = 3 V

IVBAT TX Mode, ON Semiconductor propri-etary audio streaming protocol at 7 kHzaudio BW, 5.5 ms delay.

− 0.9 − mA

Deep sleep current,example 1, VBAT = 3 V

Ids1 Wake up form wake up pin. − 25 − nA

Deep sleep current,example 2, VBAT = 3 V

Ids2 Embedded 32 kHz oscillator runningwith interrupts from timer or external pin.

− 40 − nA

Deep sleep current,example 3, VBAT = 3 V

Ids3 As Ids2 but with 8 kB RAM data reten-tion.

− 100 − nA

Standby Mode current,VBAT = 3 V

Istb Digital blocks and memories are notclocked and are powered at a reducedvoltage.

− 17 − �A

EEMBC CoreMark BENCHMARK for the ARM Cortex−M3 Processor and the LPDSP32 DSP

ARM Cortex−M3 processor running from RAM

At 48 MHz SYSCLKUsing the IAR 8.10.1 C compiler

159.1 CoreMark

LPDSP32 running from RAM At 48 MHz SYSCLKUsing the 2017.03 release of theSynopsys LPDSP32 C compiler

122.9 CoreMark

ARM Cortex−M3 processor andLPDSP32 running from RAM,VBAT = 1.25 V

At 48 MHz SYSCLK 104.9 CoreMark/mA

ARM Cortex−M3 processor andLPDSP32 running from RAM,VBAT = 3 V

At 48 MHz SYSCLK 248.5 CoreMark/mA

INTERNALLY GENERATED VDDC: Digital Block Supply Voltage

Supply voltage: operating range VDDC 0.9 1.15 1.32(Note 2)

V

Supply voltage: trimming range VDDCRANGE 0.75 1.38 V

Supply voltage: trimming step VDDCSTEP − 10 − mV

INTERNALLY GENERATED VDDM: Memories Supply Voltage

Supply voltage: operating range VDDM 1.08 1.15 1.32(Note 3)

V

Supply voltage: trimming range VDDMRANGE 0.75 1.38 V

Supply voltage: trimming step VDDMSTEP − 10 − mV

INTERNALLY GENERATED VDDRF: Radio Front end supply voltage

Supply voltage: operating range VDDRF 1.00 1.10 1.32 (Notes4 and 5)

V

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Table 3. ELECTRICAL PERFORMANCE SPECIFICATIONS Unless otherwise noted, the specifications mentioned in the table below are valid at 25°C at VBAT = VDDO = 1.25 V.

Description UnitsMaxTypMinConditionsSymbol

INTERNALLY GENERATED VDDRF: Radio Front end supply voltage

Supply voltage: trimming range VDDRFRANGE 0.75 1.38 V

Supply voltage: trimming step VDDRFSTEP − 10 − mV

INTERNALLY GENERATED VDDPA: Optional Radio Power Amplifier Supply Voltage

Supply voltage: operating range VDDPA 1.05 1.3 1.68 V

Supply voltage: trimming range VDDPARANGE 1.05 1.68 V

Supply voltage: trimming step VDDPASTEP − 10 − mV

Supply voltage: trimming step DCDCSTEP − 10 − mV

VDDO PAD SUPPLY VOLTAGE: Digital Level High Voltage

Digital I/O supply VDDO − VBAT − V

INDUCTIVE BUCK DC−DC CONVERTER

VBAT range when the DC−DCconverter is active (Note 6)

DCDCIN_RANGE

1.4 3.3 V

VBAT range when the LDO isactive

LDOIN_RANGE

1.1 3.3 V

Output voltage: trimming range DCDCOUT_RANGE

1.0 1.2 1.32 V

Supply voltage: trimming step DCDCSTEP − 10 − mV

POWER−ON RESET

POR voltage VBATPOR 0.4 0.8 1.0 V

RADIO FRONT−END: General Specifications

RF input impedance Zin Single ended − 50 − �

Input reflection coefficient S11 All channels − − −8 dB

Data rate FSK / MSK / GFSK RFSK OQPSK as MSK 62.5 1000 3000 kbps

Data rate 4−FSK − − 4000 kbps

On−air data rate bps GFSK 250 2000 kbps

RADIO FRONT−END: Crystal and Clock Specifications

Xtal frequency FXTAL Fundamental 48 MHz

Equiv. series Res. ESRXTAL 20 − 80 �

Differential equivalent loadcapacitance

CLXTAL 6 8 10 pF

Settling time − 0.5 1.5 ms

RADIO FRONT−END: Synthesizer Specifications

Frequency range FRF Supported carrier frequencies 2360 − 2500 MHz

RX frequency step RX Mode frequency synthesizer reso-lution

− − 100 Hz

TX frequency step TX Mode frequency synthesizer reso-lution

− − 600 Hz

PLL Settling time, RX tPLL_RX RX Mode − 15 25 �s

PLL Settling time, TX tPLL_TX TX mode, BLE modulation − 5 10 �s

RADIO FRONT−END: Receive Mode Specifications

Current consumption at 1 Mbps,VBAT = 1.25 V

IBATRFRX VDDRF =1.1 V, 100% duty cycle − 5.6 − mA

Current consumption at 2 Mbps,VBAT = 1.25 V

IBATRFRX VDDRF =1.1 V, 100% duty cycle − 6.2 − mA

Current consumption at 1 Mbps,VBAT = 3 V, DC−DC

IBATRFRX VDDRF =1.1 V, 100% duty cycle − 3.0 − mA

Current consumption at 2 Mbps,VBAT = 3 V, DC−DC

IBATRFRX VDDRF =1.1 V, 100% duty cycle − 3.4 − mA

RX Sensitivity, 0.25 Mbps 0.1% BER (Note 7) − −97 − dBm

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Table 3. ELECTRICAL PERFORMANCE SPECIFICATIONS Unless otherwise noted, the specifications mentioned in the table below are valid at 25°C at VBAT = VDDO = 1.25 V.

Description UnitsMaxTypMinConditionsSymbol

RADIO FRONT−END: Receive Mode Specifications

RX Sensitivity, 0.5 Mbps 0.1% BER (Note 7) − −96 − dBm

RX Sensitivity, 1 Mbps, BLE 0.1% BER (Note 7) Single−ended onchip antenna match to 50 �

− −94 − dBm

RX Sensitivity, 2 Mbps, BLE 0.1% BER (Note 7) − −92 − dBm

RSSI effective range Without AGC − 60 − dB

RSSI step size − 2.4 − dB

RX AGC range − 48 − dB

RX AGC step size Programmable − 6 − dB

Max usable signal level 0.1% BER 0 5 − dBm

RADIO FRONT−END: Transmit Mode Specifications

Tx peak power consumption atVBAT = 1.25 V (Note 8)

IBATRFTX Tx power 0 dBm, VDDRF = 1.07 V,VDDPA: off, LDO mode

− 8.9 − mA

Tx power 3 dBm, VDDRF = 1.1 V, VDDPA = 1.26 V, LDO mode

− 17.4 − mA

Tx power 6 dBm, VDDRF = 1.1 V, VDDPA = 1.65 V, LDO mode

− 25 − mA

Tx peak power consumption atVBAT = 3 V (Note 8)

IBATRFTX Tx power 0 dBm, VDDRF = 1.07 V,VDDPA: off, DC−DC mode

− 4.6 − mA

Tx power 3 dBm, VDDRF = 1.1 V, VDDPA = 1.26 V, DC−DC mode

− 8.6 − mA

Tx power 6 dBm, VDDRF = 1.1 V, VDDPA = 1.65V, DC−DC mode

− 12 − mA

Transmit power range BLE or 802.15.4 OQPSK −17 +0.5 +6 dBm

Transmit power step size Full band. − 2 − dB

Transmit power accuracy Tx power 3 dBm. Full band. Relative tothe typical value.

−1 − +1 dB

Tx power 0 dBm. Full band. Relative tothe typical value.

−1.1 − 1.5 dB

Power in 2nd harmonic 0 dBm mode. 50 � for “Typ” value. PTfor “Max” value (Note 9)

− −31 −18 dBm

Power in 3rd harmonic 0 dBm mode. 50 � for “Typ” value. PTfor “Max” value (Note 9)

− −40 −31 dBm

Power in 4th harmonic 0 dBm mode. 50 � for “Typ” value. PTfor “Max” value (Note 9)

− −49 −42 dBm

ADC

Resolution ADCRES 8 12 14 bits

Input voltage range ADCRANGE 0 − 2 V

INL ADCINL −2 − +2 mV

DNL ADCDNL −1 − +1 mV

Channel sampling frequency ADCCH_SF For the 8 channels sequentially, SLOWCLK = 1 MHz

0.0195 − 6.25 kHz

32 kHz ON−CHIP RC OSCILLATOR

Untrimmed Frequency FreqUNTR 20 32 50 kHz

Trimming steps Steps 1.5 %

3 MHz ON−CHIP RC OSCILLATOR

Untrimmed Frequency FreqUNTR 2 3 5 MHz

Trimming steps Steps 1.5 %

Hi Speed mode Fhi 10 MHz

32 kHz ON−CHIP CRYSTAL OSCILLATOR (Note 10)

Output Frequency Freq32k Depends on xtal parameters 32768 Hz

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Table 3. ELECTRICAL PERFORMANCE SPECIFICATIONS Unless otherwise noted, the specifications mentioned in the table below are valid at 25°C at VBAT = VDDO = 1.25 V.

Description UnitsMaxTypMinConditionsSymbol

32 kHz ON−CHIP CRYSTAL OSCILLATOR (Note 10)

Startup time 1 3 s

Internal load trimming range Steps of 0.4 pF 0 25.2 pF

External load Capacitance Maximum external capacity allowed(package, routing, etc.)

3.5 pF

ESR 100 k�

Duty Cycle 40 50 60 %

DC CHARACTERISTICS OF THE DIGITAL PADS − With VDDO = 2.97 V – 3.3 V, nominal: 3.0 V Logic

Voltage level for high input VIH 2 VDDO+0.3 V

Voltage level for low input VIL VSSD−0.3

0.8 V

DC CHARACTERISTICS OF THE DIGITAL PADS − With VDDO = 1.1 V – 1.32 V, nominal: 1.2 V Logic

Voltage level for high Input VIH 0.65*VDDO

VDDO+0.3 V

Voltage level for low input VIL VSSD−0.3

0.35* VDDO V

DIO DRIVE STRENGTH

DIO drive strength IDIO 2 12 12 mA

FLASH SPECIFICATIONS

Endurance of the 384 kB of flash 100,000 write/erasecycles

Endurance for sections NVR1,NVR2, and NVR3 (6 kB in total)

1000 write/erasecycles

Retention 25 years

2. The maximum VDDC voltage cannot exceed the VBAT input voltage or the VCC output from the buck converter.3. The maximum VDDM voltage cannot exceed the VBAT input voltage or the VCC output from the buck converter.4. The maximum VDDRF voltage cannot exceed the VBAT input voltage or the VCC output from the buck converter.5. The VDDRF calibrated targets are:

− 1.10 V (TX power > 0 dBm, with optimal RX sensitivity)− 1.07 V (TX power = 0 dBm)− 1.26 V (TX power = 3 dBm)

The VDDPA calibrated targets are:− 1.30 V− 1.26 V (TX power = 3 dBm, assumes VDDRF = 1.10 V)− 1.65 V (TX power = 6 dBm, assumes VDDRF = 1.10 V)

6. The LDO can be used to regulate down from VBAT and generate VCC. For VBAT values higher than 1.5 V, the LDO is less efficient andit is possible to save power by activating the DC−DC converter to generate VCC.

7. Signal generated by RF tester8. All values are based on evaluation board performance at the antenna connector, including the harmonic filter loss9. Harmonics need to be filtered with an external filter (See “RF Filter” on Table 5).10.These specifications have been validated with the Epson Toyocom MC – 306 crystal

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Productperformance may not be indicated by the Electrical Characteristics if operated under different conditions. (����) :;<=>?，“�@A%”�-����B.�CDE����F%�GH。��7�IE��34，�F%����“�@A%”�-�.�%�GH��!。

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Table 4. RECOMMENDED VDDC and VDDM LEVEL

Operating Frequency (MHz) Minimum VDDC Voltage (V) VDDM Voltage (V) Restriction

0 – 24 0.92 1.08 The ADC will be functional in low frequencymode and between 0 and 85°C only.

0 – 24 1 1.08 None

24 – 48 1.05 1.08 None

NOTE: The VDDC and VDDM regulators have to be trimmed at least 10 mV above the minimum voltages indicated in Table 4.

Table 5. RECOMMENDED EXTERNAL COMPONENTS

Components Function Recommended typical value Tolerance

Cap (VBAT−VSSA) VBAT decoupling 4.7 �F +100 nF + 100 pF (Note 11) ±20%

Cap (VDDO−VSSD) VDDO decoupling 1 �F ±20%

Cap (VDDRF−VSSRF) VDDRF decoupling 2.2 �F ±20%

Cap (VCC−VSSA) VCC decoupling Low ESR 2.2 �F (Note 12) or 4.7 �F ±20%

Cap (VDDA−VSSA) VDDA decoupling 1 �F ±20%

Cap (CAP0−CAP1) Pump capacitor for the charge pump 1 �F ±20%

Inductor (DC−DC) DC−DC converter inductance Low ESR 2.2 �H (See Table 6 below) ±20%

Xtal_32 kHz Xtal for 32 kHz oscillator − MC – 306, Epson− CM8V−T1A, Micro Crystal Switzerland

Xtal_48 MHz Xtal for 48 MHz oscillator 8Q−48.000MEEV−T, TXC Corporation, Taiwan

RF filter External harmonic filter 1.5 pF / 3 nH / 1.5 pF / 1.8 nH ±20%

NOTE: All capacitors used must have good RF performance.11. The recommended decoupling capacitance uses 3 capacitors with the values specified12.Example: AMK105BJ225_P, Taiyo Yuden

Table 6. RECOMMENDED DC−DC CONVERTER INDUCTANCE TABLE

Manufacturer Part Number Case Size Comments

Taiyo Yuden CKP2012N_2R2 0805 SMD withTmax = 1.0 mm

A degradation of 1 dB in the RX sensitivity is expected in DC−DC mode(Vbat = 3.3 V) versus LDO mode operation.

Taiyo Yuden CBMF1608T2R2M 0603 SMD withTmax = 1.0 mm

A degradation of <1 dB in RX sensitivity is expected in DC−DC mode(Vbat = 3.3 V) versus LDO mode operation. Also, the current drawn fromthe battery will be 4−10% higher than when the CKP2012N_2R2 is used

depending on operation mode and settings.

NOTE: Values have been measured on the QFN version of the RSL10 development board.

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RSL10

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Table 7. BUMP AND COATING SPECIFICATIONS

Subject Specification

Bump metallization Sn 97.7%/Ag 2.3%

Backside coating specification Lintec Adwill LC2850

Backside coating thickness 25 �m

Figure 2. RSL10 Application Diagram, 3.3 V

NOTE: DC−DC inductance is not needed. RSL10should be configured in LDO mode and theDC−DC converter should not be used.

Figure 3. RSL10 Application Diagram, 1.25 V

RSL10

VS

SPA

VS

SA

VB

AT

VD

DC

VSSA

VD

C

100pF

VSSA

4.7uF

VS

SD

VD

DO

1.4 − 3.6V

VSSD

1uF

RF

XTAL48_P

VD

DR

F

XTAL48_N

VSSA

2.2uF

XTAL32k_IN

VD

DA

XTAL32k_OUT

VSSA

1uF

Cpump

cap0

VS

SR

F

cap1

VC

C

2.2uH

VD

DM

1uF

3nH

1.5pF 1.5pF

1.8nH

VSSA

100nF

VSSA

VS

S VD

DS

YN

_SW

VD

DR

F_S

W

4.7uF

VS

SPA

VS

SA

VB

AT

VD

DC

RSL10

VSSA

4.7uF

VS

SD

VD

DO

1.25V

VSSD

1uF

RF

XTAL48_P

VD

DR

F

XTAL48_N

VSSA

2.2uF

XTAL32k_IN

VD

DA

XTAL32k_OUT

VSSA

1uF

Cpump

cap0

VS

SR

F

VC

C

cap1 VD

DM

1uF

3nH

1.5pF 1.5pF

1.8nH

VSSA

100pF

VSSA

100nF

VSSA

VS

S VD

DS

YN

_SW

VD

DR

F_S

W

4.7uF

VBAT

VBAT

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Table 8. CHIP INTERFACE SPECIFICATIONS

Pad Name DescriptionPower

Domain I/O A/D PullPad #,

WLCSPPad #,QFN48

VBAT Battery input voltage VBAT I P K5,K7,K10 9

VDC DC−DC output voltage to external LC filter O A J11 10

VCC DC−DC filtered output I P/A K11 12

XTAL32_IN Xtal input pin for 32 kHz xtal I/O A L10 14

XTAL32_OUT Xtal output pin for 32 kHz xtal I/O A L11 13

VSSA Analog ground I/O P E10 8

RES RESERVED I D D F8 11

VDDA Charge pump output for analog and flash supplies VDDA I/O P/A F11 5

VDDRF LDO’s output for radio voltage supply I/O P/A A11 48

CAP0 Pump capacitor connection O A H11 7

CAP1 Pump capacitor connection O A G10 6

AOUT Analog test pin O A L6 4

VDDRF_SW Supply pin for the RF VDDRF_SW P/A A9 47

VDDSYN_SW Supply pin for the radio synthesizer P/A B8 45

VSSRF RF analog ground I/O P B9 46

XTAL48_N Negative input for the 48 MHz xtal block I/O A A6 43

XTAL48_P Positive input for the 48 MHz xtal block I/O A A8 44

VDDPA Radio power amplifier voltage supply VDDPA I/O P/A C11 2

VSSPA Radio power amplifier ground I/O P D11 3

RF RF signal input/output (Antenna) RF I/O A B11 1

VPP Flash high voltage access VPP I/O A J6 17

RSL10

www.onsemi.cn11

Table 8. CHIP INTERFACE SPECIFICATIONS

Pad NamePad #,QFN48

Pad #,WLCSPPullA/DI/O

PowerDomainDescription

NRESET Reset pin VDDO I D U L9 16

WAKEUP Wake−up pin for power modes I A L8 15

VDDC LDO output for Core logic voltage supply I/O P H6 19

VDDM LDO output for memories voltage supply I/O P F4 21

VDDO Digital I/O voltage supply I P B4 36

VSSD Digital ground pad for I/O I/O P F3, D6, F9 28, 35

VSS (*) Substrate connection for the RF part I/O P B6 42

EXTCLK External clock input / Internal clock output I/O D U F1 31

DIO[0] Digital input output / ADC 0 I/O A/D U/D L4 18

DIO[1] Digital input output / ADC 1 I/O A/D U/D L3 20

DIO[2] Digital input output / ADC 2 I/O A/D U/D L2 23

DIO[3] Digital input output / ADC 3 I/O A/D U/D L1 25

DIO[4] Digital input output 4 I/O D U/D K2 24

DIO[5] Digital input output 5 I/O D U/D K1 27

DIO[6] Digital input output 6 I/O D U/D J1 29

DIO[7] Digital input output 7 I/O D U/D H1 30

DIO[8] Digital input output 8 I/O D U/D G2 26

DIO[9] Digital input output 9 I/O D U/D E2 22

DIO[10] Digital input output 10 I/O D U/D D1 32

DIO[11] Digital input output 11 I/O D U/D B2 38

DIO[12] Digital input output 12 I/O D U/D A1 37

DIO[13] Digital input output / CM3−JTAG Test Reset I/O D U/D A2 39

DIO[14] Digital input output / CM3−JTAG Test Data In I/O D U/D A3 41

DIO[15] Digital input output / CM3−JTAG Test Data Out I/O D U/D A4 40

JTCK CM3−JTAG Test Clock I/O D U C1 33

JTMS CM3−JTAG Test Mode State I/O D U B1 34

*VSS should be connected to VSSRF at the PCB level.

NOTE: It is recommended that the QFN package metal slug be left open/floating for optimal Rx sensitivity performance

Legend:Type: A = analog; D = digital; I = input; O = output; P = powerPull: U = pull up; D = pull downPull up: selectable between 10 k� and 250 k�Pull down: 250 k�All digital pads have a Schmitt trigger input.All DIO pads have a programmable I2C low pass filter.

RSL10

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Memory type Data Width Memory Size Accessed by

Program memory (ROM) 32 4 kB ARM Cortex−M3 processor

Program memory (RAM) 32 4 instances of 8 kB ARM Cortex−M3 processor

Program memory (RAM) 40 4 instances of 10 kB LPDSP32 / ARM Cortex−M3 processor

Data memory (RAM) 32 1 instances of 8 kB ARM Cortex−M3 processor

Data memory (RAM) 32 2 instances of 8 kB ARM Cortex−M3 processor / LPDSP32

Data memory (RAM) 32 6 instances of 8 kB LPDSP32 / ARM Cortex−M3 processor

Data memory (RAM) 32 2 instances of 8 kB Baseband / ARM Cortex−M3 processor

Flash 32 384 kB ARM Cortex−M3 processor / Flash copier

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RSL10

www.onsemi.cn16

PACKAGE DIMENSIONS

QFN48 6x6, 0.4PCASE 485BA

ISSUE A

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NOTES:1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.2. CONTROLLING DIMENSIONS: MILLIMETERS.3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN0.15 AND 0.30mm FROM TERMINAL TIP

4. COPLANARITY APPLIES TO THE EXPOSEDPAD AS WELL AS THE TERMINALS.

DIM MIN MAXMILLIMETERS

A 0.80 1.00A1 0.00 0.05A3 0.20 REFb 0.15 0.25D 6.00 BSCD2 4.40 4.60E 6.00 BSC

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4.66

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*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

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MOLD CMPDEXPOSED Cu

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PKGOUTLINE

RSL10

www.onsemi.cn17

PACKAGE DIMENSIONS

WLCSP51, 2.364x2.325CASE 567MT

ISSUE A

SEATINGPLANE

0.05 C

NOTES:1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.2. CONTROLLING DIMENSION: MILLIMETERS.3. COPLANARITY APPLIES TO SPHERICAL

CROWNS OF SOLDER BALLS.4. PACKAGE CENTER AND FOOTPRINT CENTER

ARE NOT COINCIDENT. REFER TO DIMENSION FFOR OFFSETS.

2X

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b 0.09 0.10

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F 0.0198 BSC

*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

0.05 C2X TOP VIEW

SIDE VIEWNOTE 3

RECOMMENDED

PITCH

0.1051X

DIMENSIONS: MILLIMETERS

0.252

0.126

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4 6 8 9 10 11

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A2 0.237 0.250A3 0.022 0.025

0.12

0.3810.0900.2630.028

0.0198

A2

RSL10

www.onsemi.cn18

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PUBLICATION ORDERING INFORMATIONN. American Technical Support: 800−282−9855 Toll FreeUSA/Canada

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RSL10CN/D

ON Semiconductor is licensed by the Philips Corporation to carry the I2C bus protocol.AirFuel is a trademark of Air Routing International Corporation.Bluetooth is a registered trademark of Bluetooth SIG.ARM and Cortex are registered trademarks of ARM Limited (or its subsidiaries).

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