rpc upscope meeting jay hauser 05 feb 20101/11 overview of the csc phase i upgrade plans me4/2...

RPC Upscope Meeting Jay Hauser 05 Feb 2010 1/11

Overview of the CSC Phase I Upgrade plans Overview of the CSC Phase I Upgrade plans

• ME4/2 upgrade: 72 new large chambers• for high-luminosity triggering in 1.1-1.8

• Flash ADC board for cathode digitization• ME1/1 to handle high rates

• ME1/1 to restore trigger and improve reconstruction for 2.1-2.4

• Upgrade ME1/1 associated TMB and DMB boards

• Schedule and “to-do” list


ME4/2 and ME1/1 upgradesME4/2 and ME1/1 upgradesME4/2 and ME1/1 upgradesME4/2 and ME1/1 upgrades

R-Z cross-section

“Empty” YE3 disk ready for ME4/2


ME4/2 upgrade motivationME4/2 upgrade motivationME4/2 upgrade motivationME4/2 upgrade motivation

• Triggering with & without the ME4/2 upgrade:• The high-luminosity Level 1 trigger threshold is reduced

from 48 18 GeV/c

Target Rate 5 kHz

Ingo Bloch, Norbert Neumeister, Rick Wilkinson

Simulation result (May ’09)(Vadim Khotilovich, Alexei Safonov)

• Efficiency gaps for good quality TF tracks disappear with addition of ME4/2


“Digital CFEB” cathode board“Digital CFEB” cathode board

• CSC principle: digitize cathode charges to ~1%, interpolate for fine position

• Current CFEB: the ADC is multiplexed 16:1• Requires analog charge storage ASIC (SCA)

• Serial digitization after L1A

• Digital CFEB uses Flash ADCs:• Continuous and deadtimeless digitization

SCA

ADC+-ref

16 FPGA12 bits

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mux

21 bitsChan-link

21:3

To DMB over Skewclear

280 Mbps6 layers

ADC

+-

ref

16 FPGA

8 pairs

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6 layers

SerialOpt. Trnscvr

To DMB over Fiber~1Gbps

MGT ADC

+-

8

8

ref

8 pairs

16 pairsPipeline/FIFOs

Serial LVDS


ME1/1 Restoration of 2.1-2.4ME1/1 Restoration of 2.1-2.4• High- section of ME1/1

• Cathode strips are currently ganged 3:1

• Plan:• Install DCFEB boards on ME1/1• Move existing CFEBs from ME1/1 to ME4/2• Takes ~2.5 months per endcap• 72 new TMB and DMB boards needed to

accommodate additional inputs, optolinks

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Channel 16

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ElectronicsChannel 1

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Strips: 1 16 17 32 33 48

…

US-CMS CD0 group Jay Hauser 24 Feb 2009 7

DMB/TMB modificationsDMB/TMB modifications

• Needed for 72 ME1/1 chambers:• Option for 7 DCFEBs/chamber requires optical links I/O

• More reliable than Skewclear copper

• Requires more FPGA space and faster processing in TMB (mezzanine card Virtex2 Virtex6)

Sk

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ear-

SC

SI

con

nec

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Sk

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DMB TMB


ME4/2 PlanningME4/2 Planning

• 2008-9: a ME4/2 prototype chamber was built at FNAL and installed at CERN

• same design as ME2/2 and ME3/2 but some critical vendors and parts have changed

• installed in CMS with 4 spare chambers for “battle testing”

• working fine

• Qualification of additional parts vendors (especially FR4 skins)

• Production plans are well understood, but funding t0 not yet established

• Otherwise, the B904 plan seems to be taking shape


ME4/2 Upgrade ScheduleME4/2 Upgrade ScheduleME4/2 Upgrade ScheduleME4/2 Upgrade Schedule

t0 + 0 months CD2 approval, money flows, begin work on Bldg 904

t0 + 3 months orders sent out for all parts

t0 + 6 months production tooling shipped to CERN and assembled in Bldg 904

t0 + 9 months chamber parts delivered, shipped to CERN

t0 + 12 months production begins at Bldg 904 at 2 CSCs/month

t0 + 15 months production ramps to 4 CSCs/month

t0 + 18 months FAST site begins assembly & testing at CERN (Bldg 904?), spare CFEB boards installed on ME4/2s

t0 + 24 months 42 CSCs finished and tested -- ready for installation of 1st endcap, recover 200 CFEB boards from ME1/1s

t0 + 33 months all 76 CSCs finished

t0 + 36 months final 36 chambers ready for installation on 2nd endcap


Overall schedule (if FY2011 start)Overall schedule (if FY2011 start)


Muon upgrade to-do listMuon upgrade to-do list

• DCFEB first prototype ready soon (~April)• Could DCFEBs be installed in 2012 on ME1/1? If

funded and pushed…

• Design started on other associated electronics upgrades for ME1/1

• TMB and DMB boards hardware and firmware

• Chamber assembly:• B904 assembly area currently being developed• ~May send FNAL assembly machines to CERN• Later in 2010 send parts for several chambers to

CERN, use these to develop assembly space and train factory personnel (depends on production t0)


Backup SlidesBackup Slides


New ALCT mezzanine card prototypeNew ALCT mezzanine card prototypeNew ALCT mezzanine card prototypeNew ALCT mezzanine card prototype

10.3125 Gbps optical transceiver

SerializerDeserializer

FPGAXC4VLX25-11FF668

Link reference oscillator

Front-end Clock and Time marker Reset inputs

Inputs from front-end discriminators

10.3125 Gbps eye diagram (receiver’s electrical output after 100 m of fiber)

MTCC data:from KeyWireGroupto WeightedWireGroup

• Position Position resolution resolution improvement:improvement:

• Prototype:Prototype:

Alex Madorsky


Neutron backgrounds: a typical event at LHCNeutron backgrounds: a typical event at LHCNeutron backgrounds: a typical event at LHCNeutron backgrounds: a typical event at LHC

• From 1999 study using Gamma Irradiation Facility

• Study of LHC-like neutron background conditions (gamma ray source)

• One event, 6 layers, charge per strip as a function of time (into page)

• 10x higher backgrounds will give quite substantial occupancy…

• Clearly, simulations are crucial


Muon Port Card upgradeMuon Port Card upgrade• Currently MPC Sector

Processor limited to 3 CSC stubs per 60 degree sector

• High Pt muon plus low-Pt muons or accidentals can lose muon stubs

• Efficiency loss grows dramatically with luminosity

• Phase 1 replacement of Sector Processors:

• Optical links >10 Gb data transfer rate (vs. 1.6 Gb)

• Other end of links (MPCs) must also be upgraded

• MPC replacement (60 boards):• ser/des can reduce CSC muon stub

bottleneck further• use faster FPGA to maintain current

latency

EMU/ME1/1 meeting 25 February,2008, V.Karjavin

Read out integration issues:

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On-chamber integration issues:

Cooling plates of stay the same

- Design of the new covers and fixtures for CFEBs

- Replacement of the cooling pads

Replacement of the “3 to 1” R/O back to 3 CFEBs

On chamber cabling:

- input cables from CSC to CFEB for ME1/1b stay the same

- Procurement of the new input cables from CSC to CFEB for ME1/1a

- LV cables stay the same (length should be confirmed)

ME1/1b

ME1/1a


Off-chamber integration issues:

1

2

3

1. Output from CSC – for optics better to locate patch panel 2. Cables excess storage place – loops for optics must be foreseen3. Input in vertical trays (covered by ME2,3 chambers) – scenarios for optic

cables installation (dismantle skewclear cables?)


Off-chamber integration issues:

Redesign of ME1/1 Patch panel

- Dismantle skewclear cables

- Fixation of optic cables

- Optics connection to chamber – patch panel?


Phase 2 upgrade To-Do itemsPhase 2 upgrade To-Do items

• Understand background rates from real data

• Understand implications of backgrounds:• Trigger rates, data bottlenecks, performance

degradation

• SEU rates

• Electronics radiation hardness

• Understand implications of track trigger upgrade

• Understand benefits of better trigger primitive resolution

rpc upscope meeting jay hauser 05 feb 20101/11 overview of the csc phase i upgrade plans me4/2...

Documents

spare cfeb boards

assembly space

chambers ready

cern bldg

me11 chambers

dcfeb boards

l1adigital cfeb

firmwarechamber assembly