rockwel-collins tech day veloce - amazon s3 · 2014. 5. 22. · digital encoder digital tv...
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ROCKWEL-COLLINSTECH DAYVELOCE
May 2014
Henry Nguyen – Application Engineer
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
Agenda
Veloce Product Overview
— Technology
— Modeling Interfaces
— Acceleration
Consulting
Proposed System Overview
Veloce Overview, May 20142
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
Real Veloce Customers – Real Value
CDMA Chipsets
Embedded processors
Networking & Wireless
Digital TV
Broadband, Networking
Digital Camera
Embedded CPUs
Digital Encoder
Digital TV
Broadband
SoC on FPGA
Networking & Wireless
Set-top Box
Veloce Overview, May 2014
Graphics, chipsets
Cinema Cameras
3
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
TECHNOLOGY
Veloce
Veloce Overview, May 20144
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
Veloce Overview
module ddr1_core (DOUT, DIN, WA, RA, WE);input [23 : 0] WA, RA;input [7 : 0] DIN;input WE;output [7 : 0] DOUT;reg [7 : 0] DOUT;reg [7 : 0] mem [16777215 : 0];
always @ (posedge WE)begin
mem[WA] = DIN;end
always @ (RA)begin
DOUT = mem[RA];end
endmodule
RTL Design Crystal SoC
Compiler
Download
Runtime
Compiler
Veloce Overview, May 20145
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
Veloce Overview
module ddr1_core (DOUT, DIN, WA, RA, WE);input [23 : 0] WA, RA;input [7 : 0] DIN;input WE;output [7 : 0] DOUT;reg [7 : 0] DOUT;reg [7 : 0] mem [16777215 : 0];
always @ (posedge WE)begin
mem[WA] = DIN;end
always @ (RA)begin
DOUT = mem[RA];end
endmodule
RTL Design Crystal SoC
Maximus 800M Gates
Compiler
Download
Runtime
Compiler
Veloce Overview, May 20145
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
Veloce Full Custom Emulation IC
Veloce Overview, May 2014
Veloce emulation SoC— Full debug visibility— Fast, predictable compile— Embedded logic analyzer— Debug control
Advanced Verification Board— Fast and deterministic compile flow— 100% visibility & debug without recompile— Simulation-like interactive debug— True asynchronous clock support— Hi Bandwidth co-model channels
Dedicated visibility HW – No capacity & performance impact
96KMacro
Elements
32 MB SDRAM
32 MB SDRAM
MacroElements
(500K Gates Equivalent)
1M Bytes SRAM
TraceController
DebugEngine
VirtualWire Logic
96KMacro
Elements
32 MB SDRAM
32 MB SDRAM
MacroElements
(1M Gates Equivalent)
2.2M Bytes SRAM
TraceController
DebugEngine
VirtualWire Logic
1.2 Billion Transistors
6
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
Specifications
Features Veloce 2 Maximus Benefits
Design capacity 800 Million Gates Larger designs
Run Time Performance Up to 1.5 MHz Shorter runtimes
Modes
• In-Circuit Emulation• Hardware/ Software Co-Verification
• Transaction-Based Verification• Embedded Testbench
• System Level Integration• Early Software Validation
• Reuse Test Bench between simulation and Acceleration
• Accelerated Verification
Design memory
Per Crystal: 2.25MBUp to 2 GB / System Larger designs
Improved capacityPer board: 2 GB128 GB / System
Power consumption 50 KW
# of Users Up to 64
Veloce Overview, May 20147
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
MODELING INTERFACES
Mentor’s Interface Solutions
Veloce Overview, May 2014
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
Mentor Delivers a Comprehensive Set of Emulation Solutions to Meet Verification Needs
USBPCIePhysical I/O
Veloce Transactors
OVM/UVM SystemVerilog C/SystemC
Simulation Acceleration
TBX
....
RTL SoC Design
iSolve Solutions
Virtual Device Solutions
USB
Virtual PeripheralsEthernet Video ....
Software Debug
Codelink
SW DebugVStream
VideoJTAG
Co-M
odel Channels
Physical Peripherals
Note: VSTREAM is a registered ARM product
Audio
Veloce Overview, May 2014
Lauterbach
9
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
Mentor Delivers a Comprehensive Set of Emulation Solutions to Meet Verification Needs
USBPCIePhysical I/O
Veloce Transactors
OVM/UVM SystemVerilog C/SystemC
Simulation Acceleration
TBX
....
RTL SoC Design
iSolve Solutions
Virtual Device Solutions
USB
Virtual PeripheralsEthernet Video ....
Software Debug
Codelink
SW DebugVStream
VideoJTAG
Co-M
odel Channels
Physical Peripherals
Note: VSTREAM is a registered ARM product
Audio
Veloce Overview, May 2014
Lauterbach
9
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
iSolve SolutionsPortfolio of Vertical-Market Applications
• DDR2, DDR3, LPDDR, LPDDR2, GDDR5, ONFi 2.1 Flash,Samsung NOR, eMMC, Serial Flash
• AMBA/AXI transactors• Arm9, Arm11, Cortex Families
Memory,Processors Multimedia
USB 2.0/3.0
SATA 2.6
WirelessNetworking
MultimediaStorageNetworking
Automation
Mobile
3G CellularSet Top Box
2D/3D Graphics
Handheld Devices
HDTV
Gb Ethernet
10G Ethernet
W-CDMA
3GHSPA
PCI ExpressGen 2.0 [3.0]
• 3G/4G Wireless Testers(e.g. Rohde & Schwarz, Anite)• Raw Data
• TCP• IP • Graphics (RGB/YUV)
• Video + Audio Simultaneously
• Latest data formats for DVD, DigitalTV, Home Cinema
• Mobile multimedia –SMIA
• HDTV standards• HDMI 1.3/1.4, DVI 1.0• 3D HDMI extensions• HDCP• DisplayPort 1.1a• Generic I/O
Disk Drives
DVD Writers
• USB Peripheral and Host
• LeCroy USB Tester
Networking
Multimedia
Multimedia
Storage Mobile
Computer Peripherals
Storage
LTE40G
Ethernet
100G Ethernet
Veloce Overview, May 201410
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
Replace traditional JTAG with Codelink
Codelink post-emulation SW debug
Codelink Logfile
GHS Veloce2 Overview, Mar 201311
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
Off-line Debug with Codelink
JTAG SW debugOne user
GHS Veloce2 Overview, Mar 201312
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
Off-line Debug with Codelink
Codelink SW debug
JTAG SW debugOne user
GHS Veloce2 Overview, Mar 201312
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
Off-line Debug with Codelink
Codelink SW debug
JTAG SW debugOne user
GHS Veloce2 Overview, Mar 201312
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
Off-line Debug with Codelink
Batch run with Codelink logger
Codelink SW debug
JTAG SW debugOne user
Codelink SW debug• For many users• Playback and linking with
RTL waveforms
GHS Veloce2 Overview, Mar 201312
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
ACCELERATION
Veloce2
Veloce Overview, May 201413
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
Transaction-based Acceleration
Transactors & Design
DesignDesign
AXI X-actorAXI X-actor
PCIeX-actorPCIeX-actor
USB X-actorUSB X-actor
SATAX-actorSATAX-actor
Un-timedTransactionsSV or SystemC
High-speed Interface
Testbench
Design and testbench acceleration using hardware emulation
— Ties methodologies, environments and flows
Reduce overall development effort— Simplifies transactor development— Automates generation of re-usable
high-speed bus functional model— Synthesizes design and timed interface
to the emulator
Benefits— Lower cost with one testbench for
simulation and acceleration— More verification cycles earlier in design
cycle— Orders of magnitude performance gain— Rapid turn-around of changes
14 Veloce Overview, May 2014
Up to 1,000x Faster Than Simulation
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
MonitorMonitor MonitorMonitor
DUTDUT ResponderDriverDriver
Accelerating OVM/UVM on Veloce
CoverageCoverage
SlaveSlaveStimulus
Gen/Master
StimulusGen/
Master
ScoreboardScoreboard
TestController
15
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
MonitorMonitor MonitorMonitor
DUTDUT ResponderDriverDriver
Accelerating OVM/UVM on Veloce
CoverageCoverage
SlaveSlaveStimulus
Gen/Master
StimulusGen/
Master
ScoreboardScoreboard
VeloceTBX
TestController
DUTDUTDriverDriver
MonitorMonitor MonitorMonitor
Responder
XRTLTransactors
TLM(DPI/SCEMI-II)
15
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com16
Accelerated TransactorsVeloce
Dis
play
Pr
oces
sor
Beha
vior
al T
estb
ench
QuestaTB
Veloce Overview, May 2014
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
Simulator / Emulator Interoperability
Veloce Overview, May 201417
SCE-MI 2.0 & SV Virtual InterfaceOne testbench for simulation and acceleration
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
Debug Productivity Gain with Assertions
Integrated 0-In compiler— Native compilation of assertions
Multiple Languages and Libraries— SVA/PSL— OVL— QVL (protocol monitors and checkers)
– AXI, AHB, APB, DDR, Ethernet, HDMI, OCP, PCIe, SATA, SAS, USB, …
– Arbiter, FIFO, Encoder/Decoder, CRC, …
Assertion Support— Enable/Disable assertions at runtime— Stop on assertion firing or trigger
waveform capture— Log name, timestamp, total count and
messages
Find bugs faster!
Veloce Overview, May 201418
Design WithAssertions
AssertionFiles
HDL Analysis
RTL Mapping
Assertion Synthesis
Veloce Partitioning & Scheduling
Veloce Database
Faster, More Efficient Debug = Higher Productivity
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
In Summary Veloce Hardware Assisted Verification
Design Cycle
Verif
icat
ion
Perf
orm
ance Embedded SW
IntegrationEmulation
System Verification
Simulation & ABVAcceleration
Block-level Verification
Transaction-basedAcceleration
Chip-level Verification
Veloce = Productivity & Ease-of-Use
Emulation solutions that work across design flows and enable early integration
19 Veloce Overview, May 2014
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
CONSULTING
Veloce2
Veloce Overview, May 201420
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
Service Packaging Overview PicturePr
ojec
t M
anag
emen
tMachine
Installation
DesignMigration
Control &Automation Scripts
OptimizedVeloce Environment
Functional Design
Customer/MGCResources
TestbenchMigration
TransactorIntegration
Milestone 1
Milestone 2
Milestone 3
MCDTransactors
ITPrerequisites
MEDTransactors
CustomTransactors
Emul
atio
n En
viro
nmen
t As
sess
men
t
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
Critical Dimensions of Emulation Deployment
1. Compatibility of Design Structures with Veloce— Are test structures used today compatible with Veloce?— Assistance in Migrating to Veloce Testbenches
2. Partitioning of existing Testbenches & Verification IP between Veloce and simulation
3. Transactor Gap Analysis and Integration Plan
4. Test Control & Automation
5. Triage/Debug Flows
6. Team Development/ Training
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
Mentor Consulting:Veloce Deployment Package
Low Risk Path to Deployment
Focused on Creating Self-Sufficient Veloce Team
Structured Approach
Sample Deployment Steps:— Assessment & Planning
– Current State– Project Goals– Risks…
— Solution Architecture– Successful Bring-up– Address 5 Critical Dimensions– Transactor Assessment
— Design-Specific Playbook– Transactor Creation– Testbench Migration…
Veloce Overview, May 201423
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
DEMONSTRATION
Veloce2
Veloce Overview, May 201424
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ETHERNET
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
VirtuaLAB Ethernet Extended Architecture
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
Multi Co-Model activity— Up to 96 PHYs
Setup and monitor
Tcl Interface
Auto-compression and ftpfor recorded sessionsfor offline local analysis
Control through WAN
Controller for Multi-EPGM
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
Multi Co-Model activity— Up to 96 PHYs
Setup and monitor
Tcl Interface
Auto-compression and ftpfor recorded sessionsfor offline local analysis
Control through WAN
Controller for Multi-EPGM
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
Design Emulation Limits Dimensional Expansion24D to 96D Expansion VVED Emulation Ports Limits
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
Design Emulation Limits Dimensional Expansion24D to 96D Expansion VVED Emulation Ports Limits
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
Traffic Analysis (1/3)
Leverage of the Ethernet Solution capabilities
Inline with Signature activity
Packet Filtering
Packet Signature/ PFC
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
Traffic Analysis (1/3)
Leverage of the Ethernet Solution capabilities
Inline with Signature activity
Packet Filtering
Packet Signature/ PFC
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
Traffic Analysis (2/3)
Signature injection / detection
Ability to mark some packets as signed
In depth “Traffic Analysis” based on signature
General Traffic Analysis Filter with customizable rules
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
Traffic Analysis (3/3)
Traffic Analysis View— GUI: Traffic Analysis Filter and Statistics
— Business Layer
— TCL
— Saving/Loading to XML file
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
VirtuaLAB Ethernet Activities
Multi Co-model hosts + Controller (3.0.1)
Cross protocol Bundles (3.1.1 pre1)
Virtual LAN (3.1.1 pre1)
PPM counters
Packet Signature + Traffic Analysis (3.1.1 pre2)
Line Rate Effectiveness (3.1.1 pre3)
Priority Flow Control PFC (IP)
Wire Delay (IP)
Other— Dynamic tab creation— Custom Jumbo
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
MULTIMEDIA
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
CAGE Architecture
The Solution provides a complete flow for multimedia related DUTs
Capture
Analyzer
Generator
Exerciser
It can mimic either a multimedia source ORa multimedia sink
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
HDMI 2.0 (1 of 2)
HDMI Data Scrambling— To reduce the Electo-Magnetic Interference (EMI) and Radio
Frequency Interference (RFI) generated by the 3 data channels: TMDS Channels 0, 1 and 2
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
HDMI 2.0 (2 of 2)
Character Error Detection— The HDMI receiver checks each incoming character as to whether
it is valid in context. If not valid, increment a character error counter.
HDMI Forum Vendor Specific Data Block— Added to the first CEA Extension
Introducing YCbCr 4:2:0 pixel format
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
VirtuaLAB SoC Example
HDMIp_XGMII_DDR3_SFLASH SoC— HDMI Parallel— XGMII— Serial Flash— DDR3
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
Thank You
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com39