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VHDL SEQUENTIAL STATEMENTS
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SEQUENTIAL STATEMENTS
The order or sequence of sequential statements is very important
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Allow to describe the behavior of a
circuit as a sequence of related events
Can be used to model, simulate and synthesize:
Combinational logic circuits
Sequential logic circuits
They are used inside of:
Processes
Functions
Procedures
PROCESS
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PROCESS STATEMENT
A process, with all the sequential statements, is
a simple concurrent statement. That is, a process
is executed in just one delta time
From the traditional programming view, it is an
infinite loop
Multiple processes can be executed in parallel
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A process is a concurrent statement,
but it is the primary mode of introducing
sequential statements
ANATOMY OF A PROCESS©
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execution
wait
A process has two states: execution and wait
Once the process has been executed, it will wait for the next satisfied condition
Until a condition is satisfied
PROCESS - SYNTAX©
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process sensitivity_list
[declarations;]
begin
sequential_statements;
end process;
process
[declarations;]
begin
sequential_statements;
wait on sensitivity_list;
end process;
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PROCESS SYNTAX
[process_label:] process [(sensitivity_list)] [is]
[process_data_object_declarations]
begin
variable_assignment_statement
signal_assignment_statement
wait_statement
if_statement
case_statement
loop_statement
null_statement
exit_statement
next_statement
assertion_statement
report_statement
procedure_call_statement
return_statement
[wait on sensitivity_list]
end process [process_label];
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Sequential statements
PARTS OF A PROCESS sensitivity_list
List of all the signals that are able to trigger the process
Simulation tools monitor events on these signals
Any event on any signal in the sensitivity list will cause to execute the process at least once
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sequential_statements
All the sequential statements that will be
executed each time that the process is activated
declarations
Declarative part. Types, functions, procedures
and variables can be declared in this part
Each declaration is local to the process
SIGNAL BEHAVIOR IN A PROCESS
While a process is running ALL the SIGNALS in
the system remain unchanged -> Signals are
in effect CONSTANTS during process
execution, EVEN after a signal assignment,
the signal will NOT take a new value
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SIGNALS are updated at
the end of a process
SIGNAL - PROCESS
Signals are the interface between VHDL’s concurrent
domain and the sequential domain within a process
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Signals are a mean of communication between
processes -> VHDL can be seen as a network of
processes intercommunicating via signals
VARIABLE BEHAVIOR IN A PROCESS
While a process is running ALL the Variables in
the system are updates IMMEDIATELY by a
variable assignment statement
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CLOCKED PROCESS
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CLOCKED PROCESS
If a signal is not assigned a value in a clocked process, the signal will retain the old value
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Clocked processes lead to all the signals assigned
inside the process resulting in a flip-flop
Variables can also give a flip-flop in a clocked process. If a variable is read before it is assigned a value, it will result in a flip-flop for the variable (bad practice!)
A clocked process can result in combinational logic
besides the flip-flop(s). All logic caused by a signal
assignment in a clocked process will end up on the
“left” of the flip-flop (before the flip-flop’s input)
CLOCKED PROCESS
entity ff_example is
port(
d : in std_logic;
clk : in std_logic;
q : out std_logic);
end entity;
architecture rtl of ff_example is
begin
ff_d: process (clk)
begin
if (rising_edge(clk)) then
q <= d;
end if;
end process ff_d;
end rtl;
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CLOCKED PROCESS
entity ff_example is
port(
d, clk, rst: in std_logic;
q: out std_logic);
end entity;
architecture rtl of ff_example is
begin
ff_d_srst: process (clk)
begin
if (rising_edge(clk)) then
if (rst=‘1’) then
q <= ‘0’;
else
q <= d;
end if;
end if;
end process ff_d_srst;
end rtl;
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CLOCKED PROCESS
entity ff_example is
port(
d, clk, rst: in std_logic;
q: out std_logic);
end entity;
architecture rtl of ff_example is
begin
ff_d_arst: process (clk, rst)
begin
if (rst=‘1’) then
q <= ‘0’;
else if (rising_edge (clk)) then
q <= d;
end if;
end process ff_d_arst;
end rtl;
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CLOCKED PROCESS
architecture rtl of example is
signal q: std_logic;
begin
FD1_B1: process (clk, rst)
begin
if (rst='1') then
q <= '0';
elsif (clk'event and clk='1') then
if (en='1') then
q <= …;-- some boolean expression(B1)
end if;
end if;
end process;
q1 <= q and ..... -- some boolean expression(B2)
end rtl;
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CLOCKED PROCESS - COUNTER©
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter_ud is
generic(cnt_w: natural:= 4)
port (
-- clock & reset inputs
clk : in std_logic;
rst : in std_logic;
-- control input signals
up_dw : in std_logic;
-- ouptuts
count : out std_logic_vector(cnt_w-1 downto 0));
end counter_ud;
CLOCKED PROCESS - COUNTER©
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architecture rtl of counter_ud is
-- signal declarations
signal count_i: unsigned(cnt_w-1 downto 0);
begin
count_proc: process(clk, rst)
begin
if(rst='0') then
count_i <= (others => '0');
elsif(rising_edge(clk)) then
if(up_dw = '1') then -- up
count_i <= count_i + 1;
else -- down
count_i <= count_i - 1;
end if;
end if;
end process count_proc;
count <= std_logic_vector(count_i);
end architecture rtl;
COMBINATIONAL PROCESS
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COMBINATIONAL PROCESS
In a combinational process all the input signals must be contained in the sensitivity list
If a signal is omitted from the sensitivity list, the VHDL simulation and the synthesized hardware will behave differently
All the output signals from the process must be assigned a value each time the process is executed. If this condition is not satisfied, the signal will retain its value (latch !)
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COMBINATIONAL PROCESS
a_process: process (a_in, b_in)
begin
c_out <= not(a_in and b_in);
d_out <= not b_in;
end process a_process;
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b_process: process (c_in, d_in)
begin
e_out <= not(d_in and c_in);
f_out <= not c_in;
end process a_process;
COMBINATIONAL PROCESS
entity example3 is
port ( a, b, c: in bit;
z, y: out bit);
end example3;
architecture beh of example3 is
begin
process (a, b, c)
begin
if c='1' then
z <= a;
else
y <= b;
end if;
end process;
end beh;
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COMBINATIONAL VS CLOCKED
PROCESS
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COMBINATIONAL VS CLOCKED PROCESS©
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. . . .
architecture rtl of com_ex is
begin
ex_c: process (a,b)
begin
z <= a and b;
end process ex_c;
end rtl;
. . . .
architecture rtl of reg_ex is
begin
ex_r: process (clk)
begin
if (rising_edge(clk)) then
z <= a and b;
end if;
end process ex_r;
end rtl;
COMBINATIONAL VS CLOCKED PROCESS©
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entity example4 is
port ( clock, d: in std_logic;
q : out std_logic);
end example4;
architecture rtl of example4 is
begin
ex_4: process (clock)
begin
q <= d;
end process ex_4;
end rtl;
COMBINATIONAL VS CLOCKED PROCESS©
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entity example4_1 is
port ( clock, d: in std_logic;
q : out std_logic);
end example4_1;
architecture rtl of example4 is
begin
ex_4_1: process (clock)
begin
if (clock) then
q <= d;
end if;
end process ex_4_1;
end rtl;
COMBINATIONAL VS CLOCKED PROCESS©
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entity example4_2 is
port ( clock, d: in std_logic;
q : out std_logic);
end example4_2;
architecture rtl of example4 is
begin
ex_4_2: process (clock)
begin
if (clock=‘1’) then
q <= d;
end if;
end process ex_4_2;
end rtl;
COMBINATIONAL VS CLOCKED PROCESS
Sinthesis ? ? ?
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