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RT7247A

DS7247A-02 December 2012 www.richtek.com1

Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

Applicationsz Wireless AP/Routerz Set-Top-Boxz Industrial and Commercial Low Power Systemsz LCD Monitors and TVsz Green Electronics/Appliancesz Point of Load Regulation of High-Performance DSPs

2A, 18V, 340kHz Synchronous Step-Down Converter

General DescriptionThe RT7247A is a high efficiency, monolithic synchronousstep-down DC/DC converter that can deliver up to 2Aoutput current from a 4.5V to 18V input supply. TheRT7247A's current mode architecture and externalcompensation allow the transient response to beoptimized over a wide input range and loads. Cycle-by-cycle current limit provides protection against shortedoutputs, and soft-start eliminates input current surge duringstart-up. The RT7247A also provides under voltageprotection and thermal shutdown protection. The lowcurrent (

RT7247A

2DS7247A-02 December 2012www.richtek.com


Functional Pin Description Pin No. Pin Name Pin Function

1 BOOT Bootstrap for High Side Gate Driver. Connect a 0.1F or greater ceramic capacitor from BOOT to SW pins. 2 VIN Input Supply Voltage, 4.5V to 18V. Must bypass with a suitable large ceramic capacitor. 3 SW Switch Node. Connect this pin to an external L-C filter. 4,

9 (Exposed Pad) GND Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation.

5 FB Feedback Input. It is used to regulate the output of the converter to a set value via an external resistive voltage divider.

6 COMP Compensation Node. COMP is used to compensate the regulation control loop. Connect a series RC network from COMP to GND. In some cases, an additional capacitor from COMP to GND is required.

7 EN Enable Input. A logic high enables the converter; a logic low forces the IC into shutdown mode reducing the supply current to less than 3A. Attach this pin to VIN with a 100k pull-up resistor for automatic startup.

8 SS Soft-Start Control Input. SS controls the soft-start period. Connect a capacitor from SS to GND to set the soft-start period. A 0.1F capacitor sets the soft-start period to 13.5ms.

Ordering Information

Note :

Richtek products are :

` RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.

` Suitable for use in SnPb or Pb-free soldering processes.

Package TypeSP : SOP-8 (Exposed Pad-Option 2)

RT7247A

Lead Plating SystemG : Green (Halogen Free and Pb Free)

H : UVP HiccupL : UVP Latch-OffN : UVP Disabled

Pin Configurations(TOP VIEW)

SOP-8 (Exposed Pad)

BOOTVINSW

GND

SSEN

FBCOMP

GND2

3

4 5

6

7

8

9

RT7247A

3DS7247A-02 December 2012 www.richtek.com


Function Block Diagram

RSENSE+-

+-

+-UV

Comparator

Oscillator

Foldback Control

0.4V

Internal Regulator

+-

1.8V

Shutdown Comparator

Current Sense Amplifier

BOOT

VIN

GND

SW

FB

EN

COMP

VA VCC

6A

Slope Comp

Current Comparator

+-

EA0.8V

S

R

Q

Q

SS

+-

1.2V

Lockout Comparator

VCC

+

150m5k

VA

130m

Operation

Shutdown ComparatorActivate internal regulator once EN input level is largerthan the target level. Force IC to enter shutdown modewhen the EN input level is lower than 0.4V.

Internal RegulatorProvide internal power for logic control and switch gatedrivers.

Lockout ComparatorActivate the Current Comparator, release lock-out logic,and enable the switches as EN input level is larger thanlockout voltage. Otherwise, the switches still locks out.

OscillatorThe oscillator provides internal clock and controls theconverter's switching frequency.

Foldback ControlDynamically adjust the internal clock. It provides a slowerfrequency as a lower FB voltage.

UV ComparatorAs FB voltage is lower than the UV voltage, it will activatea UV protect scheme.

Error AmpThe output voltage COMP of the error amplifier is adjustedcomparing FB signal with the internal reference voltageand SS signal.

Current Sense AmplifierRSENSE detects the peak current of the high-side switch.This signal is amplified by the Current Sense Amplifierand added with a Slope Compensation. Then, it controlsthe switches by comparing this signal with the COMPvoltage.

RT7247A



Electrical Characteristics(VIN = 12V, TA = 25C, unless otherwise specified)

Absolute Maximum Ratings (Note 1)z Supply Input Voltage, VIN ------------------------------------------------------------------------------------------ 0.3V to 20Vz Switch Voltage, SW ------------------------------------------------------------------------------------------------ 0.3V to (VIN + 0.3V)

RT7247A



Parameter Symbol Test Conditions Min Typ Max Unit

Logic-High VIH 2 -- 18 EN Input Voltage

Logic-Low VIL -- -- 0.4 V

Input Under Voltage Lockout Threshold VUVLO VIN Rising 3.8 4.2 4.5 V

Input Under Voltage Lockout Hysteresis VUVLO -- 320 -- mV Soft-Start Current ISS VSS = 0V -- 6 -- A Soft-Start Period tSS CSS = 0.1F -- 13.5 -- ms Thermal Shutdown TSD -- 150 -- C

Note 1. Stresses beyond those listed Absolute Maximum Ratings may cause permanent damage to the device. These arestress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in

the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may

affect device reliability.

Note 2. JA is measured at TA = 25C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. JC ismeasured at the exposed pad of the package.

Note 3. Devices are ESD sensitive. Handling precaution is recommended.Note 4. The device is not guaranteed to function outside its operating conditions.

RT7247A



Typical Application Circuit

VOUT (V) R1 (k) R2 (k) RC (k) CC (nF) L (H) COUT (F) 8 27 3 27 3.3 22 22 x 2 5 62 11.8 20 3.3 15 22 x 2

3.3 75 24 13 3.3 10 22 x 2 2.5 25.5 12 9.1 3.3 6.8 22 x 2 1.5 10.5 12 4.7 3.3 3.6 22 x 2 1.2 12 24 3.6 3.3 3.6 22 x 2 1 3 12 3 3.3 3.6 22 x 2

Table 1. Suggested Components Selection

VIN

EN

GND

BOOT

FB

SW

7

5

2

3

1L

10H0.1F

22F x 2

R175k

R224k

VOUT3.3V

10F x 2

VIN4.5V to 18V

RT7247A

SS8CSS

COMP

CC3.3nF

RC13k

CPOpen

64, 9 (Exposed Pad)

CBOOTCIN

0.1F

COUT

Chip Enable

RT7247A



Typical Operating Characteristics Efficiency vs. Output Current

0

10

20

30

40

50

60

70

80

90

100

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2

Output Current (A)

Effi

cien

cy (%

)

VOUT = 3.3V

VIN = 4.5VVIN = 12VVIN = 17V

Output Voltage vs. Input Voltage

3.27

3.28

3.29

3.30

3.31

3.32

3.33

4 6 8 10 12 14 16 18

Input Voltage (V)

Out

put

Vol

tage

(V)

VOUT = 3.3V, IOUT = 1A

Reference Voltage vs. Temperature

0.75

0.76

0.77

0.78

0.79

0.80

0.81

0.82

0.83

0.84

0.85

-50 -25 0 25 50 75 100 125

Temperature (C)

Ref

eren

ce V

olta

ge (V

)



Output Voltage vs. Output Current

3.280

3.285

3.290

3.295

3.300

3.305

3.310

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2

Output Current (A)

Out

put V

olta

ge (V

)

VOUT = 3.3V


Switching Frequency vs. Input Voltage

300

310

320

330

340

350

360

370

380

3 6 9 12 15 18Input Voltage (V)

Sw

itchi

ng F

requ

ency

(kH

z) 1


Switching Frequency vs. Temperature

300

310

320

330

340

350

360

370

380

-50 -25 0 25 50 75 100 125

Temperature (C)

Sw

itchi

ng F

requ

ency

(kH

z) 1



RT7247A



Time (10ms/Div)

Power On from VIN

VOUT(2V/Div)

VIN(5V/Div)

IL(2A/Div)

VIN = 12V, VOUT = 3.3V, IOUT = 2A

Time (10ms/Div)

Power Off from VIN

VOUT(2V/Div)

VIN(5V/Div)

IL(2A/Div)


Time (2.5s/Div)

Output Ripple VoltageVOUT

(5mV/Div)

VSW(5V/Div)

IL(1A/Div)


Time (100s/Div)

Load Transient Response

VOUT(100mV/Div)

IOUT(1A/Div)

VIN = 12V, VOUT = 3.3V, IOUT = 1A to 2A

Current Limit vs. Temperature

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

-50 -25 0 25 50 75 100 125

Temperature (C)

Cur

rent

Lim

it (A

)

VOUT = 3.3V

VIN = 12VVIN = 17V

Time (100s/Div)

Load Transient Response

VOUT(100mV/Div)

IOUT(1A/Div)

VIN = 12V, VOUT = 3.3V, IOUT = 0A to 2A

RT7247A



Time (10ms/Div)

Power On from EN

VOUT(2V/Div)

VEN(5V/Div)

IL(1A/Div)


Time (10ms/Div)

Power Off from EN

VOUT(2V/Div)

VEN(5V/Div)

IL(1A/Div)


RT7247A



Application Information

Output Voltage SettingThe resistive divider allows the FB pin to sense the outputvoltage as shown in Figure 1.

Figure 1. Output Voltage Setting

The output voltage is set by an external resistive voltagedivider according to the following equation :

OUT REFR1V = V 1R2

+ Where VREF is the reference voltage (0.8V typ.).

External Bootstrap DiodeConnect a 0.1F low ESR ceramic capacitor between theBOOT pin and SW pin. This capacitor provides the gatedriver voltage for the high side MOSFET.

It is recommended to add an external bootstrap diodebetween an external 5V and BOOT pin for efficiencyimprovement when input voltage is lower than 5.5V or dutyratio is higher than 65% .The bootstrap diode can be alow cost one such as IN4148 or BAT54. The external 5Vcan be a 5V fixed input from system or a 5V output of theRT7247A. Note that the external boot voltage must belower than 5.5V

Figure 2. External Bootstrap Diode

Chip Enable OperationThe EN pin is the chip enable input. Pulling the EN pinlow (2V,

RT7247A



Under Voltage Protection

Hiccup ModeFor the RT7247AH, it provides Hiccup Mode Under VoltageProtection (UVP). When the VFB voltage drops below 0.4V,the UVP function will be triggered to shut down switchingoperation. If the UVP condition remains for a period, theRT7247AH will retry automatically. When the UVPcondition is removed, the converter will resume operation.The UVP is disabled during soft-start period.

Figure 5. Hiccup Mode Under Voltage Protection

Latch-Off ModeFor the RT7247AL, it provides Latch-Off Mode UnderVoltage Protection (UVP). When the FB voltage dropsbelow half of the feedback reference voltage, VFB, UVPwill be triggered and the RT7247AL will shut down in Latch-Off Mode. In shutdown condition, the RT7247AL can bereset by EN pin or power input VIN.

Figure 6. Latch-Off Mode Under Voltage Protection

OUT OUTLIN

V VI = 1f L V

Having a lower ripple current reduces not only the ESRlosses in the output capacitors but also the output voltageripple. High frequency with small ripple current can achievethe highest efficiency operation. However, it requires alarge inductor to achieve this goal.

For the ripple current selection, the value of IL = 0.24(IMAX)will be a reasonable starting point. The largest ripplecurrent occurs at the highest VIN. To guarantee that the

Over Temperature ProtectionThe RT7247A features an Over Temperature Protection(OTP) circuitry to prevent from overheating due toexcessive power dissipation. The OTP will shut downswitching operation when junction temperature exceeds150C. Once the junction temperature cools down byapproximately 20C, the converter will resume operation.To maintain continuous operation, the maximum junctiontemperature should be lower than 125C.

Inductor SelectionThe inductor value and operating frequency determine theripple current according to a specific input and outputvoltage. The ripple current IL increases with higher VINand decreases with higher inductance.

Clamp ModeFor the RT7247AN, it provides inductor current clampmode.

Figure 7. Clamp Mode

Time (1ms/Div)

Clamp Mode

VOUT(2V/Div)

ILX(1A/Div)

IOUT = Short

Time (25ms/Div)

Hiccup Mode

VOUT(2V/Div)

ILX(1A/Div)

IOUT = Short

Time (25s/Div)

Latch-Off Mode

VOUT(2V/Div)

ILX(2A/Div)

IOUT = Short

RT7247A



OUT INRMS OUT(MAX)IN OUT

V VI = I 1V V

CIN and COUT SelectionThe input capacitance, CIN, is needed to filter thetrapezoidal current at the source of the high side MOSFET.To prevent large ripple current, a low ESR input capacitorsized for the maximum RMS current should be used. Theapproximate RMS current equation is given :

This formula has a maximum at VIN = 2VOUT, whereIRMS = IOUT / 2. This simple worst case condition iscommonly used for design because even significantdeviations do not offer much relief.

Choose a capacitor rated at a higher temperature thanrequired. Several capacitors may also be paralleled tomeet size or height requirements in the design.

For the input capacitor, two 10F low ESR ceramiccapacitors are suggested. For the suggested capacitor,please refer to Table 3 for more details.

The selection of COUT is determined by the required ESRto minimize voltage ripple.

Moreover, the amount of bulk capacitance is also a keyfor COUT selection to ensure that the control loop is stable.

OUT LOUT1V I ESR

8fC +

The output ripple will be the highest at the maximum input

voltage since IL increases with input voltage. Multiplecapacitors placed in parallel may be needed to meet theESR and RMS current handling requirement. Higher values,lower cost ceramic capacitors are now becoming availablein smaller case sizes. Their high ripple current, high voltagerating and low ESR make them ideal for switching regulatorapplications. However, care must be taken when thesecapacitors are used at input and output. When a ceramiccapacitor is used at the input and the power is suppliedby a wall adapter through long wires, a load step at theoutput can induce ringing at the input, VIN. At best, thisringing can couple to the output and be mistaken as loopinstability. At worst, a sudden inrush of current throughthe long wires can potentially cause a voltage spike atVIN large enough to damage the part.

Thermal ConsiderationsFor continuous operation, do not exceed the maximumoperation junction temperature 125C. The maximumpower dissipation depends on the thermal resistance ofIC package, PCB layout, the rate of surroundings airflowand temperature difference between junction to ambient.The maximum power dissipation can be calculated byfollowing formula :

PD(MAX) = (TJ(MAX) TA ) / JA

Where TJ(MAX) is the maximum operation junctiontemperature , TA is the ambient temperature and the JA isthe junction to ambient thermal resistance.

For recommended operating condition specifications, themaximum junction temperature is 125C. The junction toambient thermal resistance JA is layout dependent. ForSOP-8 (Exposed Pad) package, the thermal resistanceJA is 75C/W on the standard JEDEC 51-7 four-layersthermal test board. The maximum power dissipation atTA = 25C can be calculated by following formula :

Table 2. Suggested Inductors for TypicalApplication Circuit

Component Supplier Series

Dimensions (mm)

TDK VLF10045 10 x 9.7 x 4.5 TDK SLF12565 12.5 x 12.5 x 6.5

TAIYO YUDEN NR8040 8 x 8 x 4

OUT OUTL(MAX) IN(MAX)

V VL = 1f I V

The inductor's current rating (caused a 40C temperaturerising from 25C ambient) should be greater than themaximum load current and its saturation current shouldbe greater than the short circuit peak current limit. Pleasesee Table 2 for the inductor selection reference.

ripple current stays below the specified maximum, theinductor value should be chosen according to the followingequation :

Loop stability can be checked by viewing the load transientresponse as described in a later section.

The output ripple, VOUT , is determined by :

RT7247A



PD(MAX) = (125C 25C) / (75C/W) = 1.333W(min.copper area PCB layout)

PD(MAX) = (125C 25C) / (49C/W) = 2.04W(70mm2copper area PCB layout)

The thermal resistance JA of SOP-8 (Exposed Pad) isdetermined by the package architecture design and thePCB layout design. However, the package architecturedesign has been designed. If possible, it's useful to increasethermal performance by the PCB layout copper design.The thermal resistance JA can be decreased by addingcopper area under the exposed pad of SOP-8 (ExposedPad) package.

As shown in Figure 8, the amount of copper area to whichthe SOP-8 (Exposed Pad) is mounted affects thermalperformance. When mounted to the standardSOP-8 (Exposed Pad) pad (Figure 8.a), JA is 75C/W.Adding copper area of pad under the SOP-8 (ExposedPad) (Figure 8.b) reduces the JA to 64C/W. Even further,increasing the copper area of pad to 70mm2 (Figure 8.e)reduces the JA to 49C/W.

The maximum power dissipation depends on operatingambient temperature for fixed TJ(MAX) and thermalresistance JA. The Figure 9 of derating curves allows thedesigner to see the effect of rising ambient temperatureon the maximum power dissipation allowed.

Figure 9. Derating Curve of Maximum Power Dissipation

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

0 25 50 75 100 125

Ambient Temperature (C)

Pow

er D

issi

patio

n (W

)

Copper Area 70mm2

50mm2

30mm2

10mm2

Min.Layout

Four-Layer PCB

(a) Copper Area = (2.3 x 2.3) mm2, JA = 75C/W

(b) Copper Area = 10mm2, JA = 64C/W

(c) Copper Area = 30mm2 , JA = 54C/W

(d) Copper Area = 50mm2 , JA = 51C/W

(e) Copper Area = 70mm2 , JA = 49C/W

Figure 8. Thermal Resistance vs. Copper Area LayoutDesign

RT7247A



Layout ConsiderationFollow the PCB layout guidelines for optimal performanceof the RT7247A.

` Keep the traces of the main current paths as short andwide as possible.

` Put the input capacitor as close as possible to the devicepins (VIN and GND).

` SW node is with high frequency voltage swing andshould be kept at small area. Keep analog componentsaway from the SW node to prevent stray capacitive noisepick-up.

` Connect feedback network behind the output capacitors.Keep the loop area small. Place the feedbackcomponents near the RT7247A.

` An example of PCB layout guide is shown in Figure 10for reference.

Figure 10. PCB Layout Guide

Table 3. Suggested Capacitors for CIN and COUT Location Component Supplier Part No. Capacitance (F) Case Size

CIN MURATA GRM31CR61E106K 10 1206

CIN TDK C3225X5R1E106K 10 1206 CIN TAIYO YUDEN TMK316BJ106ML 10 1206

COUT MURATA GRM31CR60J476M 47 1206

COUT TDK C3225X5R0J476M 47 1210 COUT MURATA GRM32ER71C226M 22 1210 COUT TDK C3225X5R1C22M 22 1210

VIN

VOUT

GND

CIN

GND

CP

CC

RC

SW

VOUT

COUT

L

R1

R2

Input capacitor must be placed as close to the IC as possible.

SW node is with high frequency voltage swing and should be kept at small area. Keep analog components away from the SW node to prevent stray capacitive noise pick-up

The feedback components must be connected as close to the device as possible.

BOOTVINSW

GND

SSEN

FBCOMP

GND2

3

4 5

6

7

8

9

CSS

GND VIN

RENCBOOT

RT7247A


Richtek Technology Corporation5F, No. 20, Taiyuen Street, Chupei CityHsinchu, Taiwan, R.O.C.Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers shouldobtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannotassume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to beaccurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of thirdparties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

Outline Dimension

A

BJ

F

H

M

C

D

I

Y

X

EXPOSED THERMAL PAD(Bottom of Package)

8-Lead SOP (Exposed Pad) Plastic Package

Dimensions In Millimeters Dimensions In Inches Symbol

Min Max Min Max

A 4.801 5.004 0.189 0.197

B 3.810 4.000 0.150 0.157

C 1.346 1.753 0.053 0.069

D 0.330 0.510 0.013 0.020

F 1.194 1.346 0.047 0.053

H 0.170 0.254 0.007 0.010

I 0.000 0.152 0.000 0.006

J 5.791 6.200 0.228 0.244

M 0.406 1.270 0.016 0.050

X 2.000 2.300 0.079 0.091 Option 1

Y 2.000 2.300 0.079 0.091

X 2.100 2.500 0.083 0.098 Option 2

Y 3.000 3.500 0.118 0.138

JohnTypewritten textUser Manual and basic schematic included.

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